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References: <cover.1544643238.git.alistair.francis@wdc.com>
	<2560616ffb8a0e8c3001e3c5490c8bc1463468d0.1544643238.git.alistair.francis@wdc.com>
From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <4c5a2e04-2c85-9c46-b807-31b447da8730@linaro.org>
Date: Wed, 12 Dec 2018 17:23:08 -0600
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Subject: Re: [Qemu-devel] [PATCH v1 05/23] riscv: Add the tcg-target header
 file
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To: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>

On 12/12/18 1:43 PM, Alistair Francis wrote:
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ddfeb32c6c..aa88ee176e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -262,6 +262,7 @@ S: Maintained
>  F: target/riscv/
>  F: hw/riscv/
>  F: include/hw/riscv/
> +F: tcg/riscv/

This section is for RISC-V the target.
Your new entry belongs in RISC-V the TCG host.

See the "Tiny Code Generator (TCG)" header.


r~