From: Harsh Prateek Bora <harshpb@linux.ibm.com>
To: Aditya Gupta <adityag@linux.ibm.com>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, "Nicholas Piggin" <npiggin@gmail.com>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Sourabh Jain" <sourabhjain@linux.ibm.com>,
"Mahesh J Salgaonkar" <mahesh@linux.ibm.com>,
"Hari Bathini" <hbathini@linux.ibm.com>
Subject: Re: [PATCH 4/7] hw/ppc: Add MDST/MDDT/MDRT table structures and offsets
Date: Tue, 11 Mar 2025 10:41:32 +0530 [thread overview]
Message-ID: <4c87e14e-460e-4a59-b8e2-85ead830ee59@linux.ibm.com> (raw)
In-Reply-To: <20250217071934.86131-5-adityag@linux.ibm.com>
On 2/17/25 12:49, Aditya Gupta wrote:
> Add the MDST, MDDT, MDRT tables offsets and structures as per current
> skiboot upstream:
>
> commit bc7b85db1e7e ("opal-ci: Remove centos7")
>
> These structures will be later populated when preserving memory regions
> for MPIPL
>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> ---
> hw/ppc/pnv_sbe.c | 113 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 113 insertions(+)
>
> diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
> index 79818177fc36..361a3854307d 100644
> --- a/hw/ppc/pnv_sbe.c
> +++ b/hw/ppc/pnv_sbe.c
These should have been added in include/hw/ppc/pnv_sbe.h
> @@ -84,6 +84,119 @@
>
> static uint64_t mpipl_skiboot_base = 0x30000000 /*default SKIBOOT_BASE*/;
>
> +/* Following offsets are copied from Skiboot source code */
> +/* Use 768 bytes for SPIRAH */
> +#define SPIRAH_OFF 0x00010000
> +#define SPIRAH_SIZE 0x300
> +
> +/* Use 256 bytes for processor dump area */
> +#define PROC_DUMP_AREA_OFF (SPIRAH_OFF + SPIRAH_SIZE)
> +#define PROC_DUMP_AREA_SIZE 0x100
> +
> +#define PROCIN_OFF (PROC_DUMP_AREA_OFF + PROC_DUMP_AREA_SIZE)
> +#define PROCIN_SIZE 0x800
> +
> +/* Offsets of MDST and MDDT tables from skiboot base */
> +#define MDST_TABLE_OFF (PROCIN_OFF + PROCIN_SIZE)
> +#define MDST_TABLE_SIZE 0x400
> +
> +#define MDDT_TABLE_OFF (MDST_TABLE_OFF + MDST_TABLE_SIZE)
> +#define MDDT_TABLE_SIZE 0x400
> +
> +#define CPU_CTL_OFF (MDDT_TABLE_OFF + MDDT_TABLE_SIZE)
> +#define CPU_CTL_SIZE 0x2000
> +
> +/* MPIPL reserved regions (offset by skiboot_base to access) */
> +#define MDST_TABLE_BASE (mpipl_skiboot_base + MDST_TABLE_OFF)
> +#define MDDT_TABLE_BASE (mpipl_skiboot_base + MDDT_TABLE_OFF)
> +#define PROC_DUMP_AREA_BASE (mpipl_skiboot_base + PROC_DUMP_AREA_OFF)
> +
> +#define __packed __attribute__((packed))
> +
> +/* Metadata to capture before triggering MPIPL */
> +struct mpipl_metadata {
CamelCase for structs? Applies for other structs below.
> + /* Crashing PIR is required to create OPAL dump */
> + uint32_t crashing_pir;
> + /* Kernel expects OPAL to presrve tag and pass it back via OPAL API */
> + uint64_t kernel_tag;
> + /* Post MPIPL kernel boot memory size */
> + uint64_t boot_mem_size;
> +} __packed;
> +
> +/* Structure version */
> +#define OPAL_MPIPL_VERSION 0x01
> +
> +/* Preserved memory details */
> +struct opal_mpipl_region {
> + __be64 src;
> + __be64 dest;
> + __be64 size;
> +};
> +
> +struct opal_mpipl_fadump {
> + uint8_t version;
> + uint8_t reserved[7];
> + __be32 crashing_pir; /* OPAL crashing CPU PIR */
> + __be32 cpu_data_version;
> + __be32 cpu_data_size;
> + __be32 region_cnt;
> + struct opal_mpipl_region *region;
> +};
> +
> +/*
> + * This is our dump result table after MPIPL. Hostboot will write to this
> + * memory after moving memory content from source to destination memory.
> + */
> +#define MDRT_TABLE_BASE (mpipl_skiboot_base + 0x01c00000)
> +#define MDRT_TABLE_SIZE 0x00008000
> +
> +/*
> + * This is our dump metadata area. We will use this memory to save metadata
> + * (like crashing CPU details, payload tags) before triggering MPIPL.
> + */
> +#define DUMP_METADATA_AREA_BASE (mpipl_skiboot_base + 0x01c08000)
> +#define DUMP_METADATA_AREA_SIZE 0x8000
> +
> +/*
> + * Memory Dump Source Table
> + *
> + * Format of this table is same as Memory Dump Source Table (MDST)
> + * defined in HDAT spec.
> + */
> +struct mdst_table {
> + __be64 addr;
> + uint8_t data_region; /* DUMP_REGION_* */
> + uint8_t dump_type; /* DUMP_TYPE_* */
> + __be16 reserved;
> + __be32 size;
> +} __packed;
> +
> +/* Memory dump destination table (MDDT) */
> +struct mddt_table {
> + __be64 addr;
> + uint8_t data_region;
> + uint8_t dump_type;
> + __be16 reserved;
> + __be32 size;
> +} __packed;
If both mdst_table and mddt_table are supposed to be same, we could have
just one mdxt_table and variable instances could be named mdst/mddt.
Thanks
Harsh
> +
> +/*
> + * Memory dump result table (MDRT)
> + *
> + * List of the memory ranges that have been included in the dump. This table is
> + * filled by hostboot and passed to OPAL on second boot. OPAL/payload will use
> + * this table to extract the dump.
> + */
> +struct mdrt_table {
> + __be64 src_addr;
> + __be64 dest_addr;
> + uint8_t data_region;
> + uint8_t dump_type; /* unused */
> + __be16 reserved; /* unused */
> + __be32 size;
> + __be64 padding; /* unused */
> +} __packed;
> +
> static void pnv_sbe_set_host_doorbell(PnvSBE *sbe, uint64_t val)
> {
> val &= SBE_HOST_RESPONSE_MASK; /* Is this right? What does HW do? */
next prev parent reply other threads:[~2025-03-11 5:12 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-17 7:19 [PATCH 0/7] Implement MPIPL for PowerNV Aditya Gupta
2025-02-17 7:19 ` [PATCH 1/7] hw/ppc: Log S0/S1 Interrupt triggers by OPAL Aditya Gupta
2025-03-11 4:38 ` Harsh Prateek Bora
2025-03-13 18:43 ` Aditya Gupta
2025-02-17 7:19 ` [PATCH 2/7] hw/ppc: Implement S0 SBE interrupt as cpu_pause then host reset Aditya Gupta
2025-03-11 4:45 ` Harsh Prateek Bora
2025-03-13 18:45 ` Aditya Gupta
2025-02-17 7:19 ` [PATCH 3/7] hw/ppc: Handle stash command in PowerNV SBE Aditya Gupta
2025-03-11 4:50 ` Harsh Prateek Bora
2025-03-13 18:46 ` Aditya Gupta
2025-02-17 7:19 ` [PATCH 4/7] hw/ppc: Add MDST/MDDT/MDRT table structures and offsets Aditya Gupta
2025-03-11 5:11 ` Harsh Prateek Bora [this message]
2025-03-13 18:50 ` Aditya Gupta
2025-02-17 7:19 ` [PATCH 5/7] hw/ppc: Preserve Memory Regions as per MDST/MDDT tables Aditya Gupta
2025-03-11 5:18 ` Harsh Prateek Bora
2025-03-13 18:54 ` Aditya Gupta
2025-02-17 7:19 ` [PATCH 6/7] hw/ppc: [WIP] Add Processor Dump Area offsets in Pnv SBE Aditya Gupta
2025-03-11 5:23 ` Harsh Prateek Bora
2025-03-13 18:56 ` Aditya Gupta
2025-02-17 7:19 ` [PATCH 7/7] hw/ppc: Implement MPIPL in PowerNV Aditya Gupta
2025-03-11 5:41 ` Harsh Prateek Bora
2025-03-13 19:00 ` Aditya Gupta
2025-02-27 3:37 ` [PATCH 0/7] Implement MPIPL for PowerNV Nicholas Piggin
2025-02-27 6:23 ` Aditya Gupta
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