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[88.10.102.251]) by smtp.gmail.com with ESMTPSA id t203sm2781008wmf.42.2019.09.05.03.48.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Sep 2019 03:48:07 -0700 (PDT) To: Richard Henderson , qemu-devel@nongnu.org References: <20190904193059.26202-1-richard.henderson@linaro.org> <20190904193059.26202-61-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <4ca91971-bfdd-976a-5b9d-d38b42f826a7@redhat.com> Date: Thu, 5 Sep 2019 12:48:06 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190904193059.26202-61-richard.henderson@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-devel] [PATCH v4 60/69] target/arm: Split gen_nop_hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/4/19 9:30 PM, Richard Henderson wrote: > Now that all callers pass a constant value, split the switch > statement into the individual trans_* functions. >=20 > Reviewed-by: Peter Maydell > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 67 +++++++++++++++--------------------------- > 1 file changed, 24 insertions(+), 43 deletions(-) >=20 > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 69092c12c3..d076c962ea 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -3061,46 +3061,6 @@ static void gen_exception_return(DisasContext *s= , TCGv_i32 pc) > gen_rfe(s, pc, load_cpu_field(spsr)); > } > =20 > -/* > - * For WFI we will halt the vCPU until an IRQ. For WFE and YIELD we > - * only call the helper when running single threaded TCG code to ensur= e > - * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we > - * just skip this instruction. Currently the SEV/SEVL instructions > - * which are *one* of many ways to wake the CPU from WFE are not > - * implemented so we can't sleep like WFI does. > - */ > -static void gen_nop_hint(DisasContext *s, int val) > -{ > - switch (val) { > - /* When running in MTTCG we don't generate jumps to the yield = and > - * WFE helpers as it won't affect the scheduling of other vCPU= s. > - * If we wanted to more completely model WFE/SEV so we don't b= usy > - * spin unnecessarily we would need to do something more invol= ved. > - */ > - case 1: /* yield */ > - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { > - gen_set_pc_im(s, s->base.pc_next); > - s->base.is_jmp =3D DISAS_YIELD; > - } > - break; > - case 3: /* wfi */ > - gen_set_pc_im(s, s->base.pc_next); > - s->base.is_jmp =3D DISAS_WFI; > - break; > - case 2: /* wfe */ > - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { > - gen_set_pc_im(s, s->base.pc_next); > - s->base.is_jmp =3D DISAS_WFE; > - } > - break; > - case 4: /* sev */ > - case 5: /* sevl */ > - /* TODO: Implement SEV, SEVL and WFE. May help SMP performanc= e. */ > - default: /* nop */ > - break; > - } > -} > - > #define CPU_V001 cpu_V0, cpu_V0, cpu_V1 > =20 > static inline void gen_neon_add(int size, TCGv_i32 t0, TCGv_i32 t1) > @@ -8194,19 +8154,40 @@ DO_SMLAWX(SMLAWT, 1, 1) > =20 > static bool trans_YIELD(DisasContext *s, arg_YIELD *a) > { > - gen_nop_hint(s, 1); > + /* > + * When running single-threaded TCG code, use the helper to ensure= that > + * the next round-robin scheduled vCPU gets a crack. When running= in > + * MTTCG we don't generate jumps to the helper as it won't affect = the > + * scheduling of other vCPUs. > + */ > + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { > + gen_set_pc_im(s, s->base.pc_next); > + s->base.is_jmp =3D DISAS_YIELD; > + } > return true; > } > =20 > static bool trans_WFE(DisasContext *s, arg_WFE *a) > { > - gen_nop_hint(s, 2); > + /* > + * When running single-threaded TCG code, use the helper to ensure= that > + * the next round-robin scheduled vCPU gets a crack. In MTTCG mod= e we > + * just skip this instruction. Currently the SEV/SEVL instruction= s, > + * which are *one* of many ways to wake the CPU from WFE, are not > + * implemented so we can't sleep like WFI does. > + */ > + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { > + gen_set_pc_im(s, s->base.pc_next); > + s->base.is_jmp =3D DISAS_WFE; > + } > return true; > } > =20 > static bool trans_WFI(DisasContext *s, arg_WFI *a) > { > - gen_nop_hint(s, 3); > + /* For WFI, halt the vCPU until an IRQ. */ > + gen_set_pc_im(s, s->base.pc_next); > + s->base.is_jmp =3D DISAS_WFI; > return true; > } Reviewed-by: Philippe Mathieu-Daud=C3=A9