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([2001:b07:6468:f312:c46c:2acb:d8d2:21d8]) by smtp.gmail.com with ESMTPSA id e20sm15646151wrc.34.2019.09.19.08.16.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Sep 2019 08:16:46 -0700 (PDT) Subject: Re: [PATCH 6/7] target/i386: add VMX features From: Paolo Bonzini To: Liran Alon References: <1568716480-9973-1-git-send-email-pbonzini@redhat.com> <1568716480-9973-7-git-send-email-pbonzini@redhat.com> <60820b32-42df-dbc0-9fc7-81821b2e42cb@redhat.com> Openpgp: preference=signencrypt Message-ID: <4cbabffc-f2dd-35f8-e4cd-161f539b3fec@redhat.com> Date: Thu, 19 Sep 2019 17:16:45 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <60820b32-42df-dbc0-9fc7-81821b2e42cb@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, ehabkost@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 19/09/19 16:54, Paolo Bonzini wrote: > I will add defines for fixed_vmx_basic, fixed_vmx_misc and > fixed_vmx_ept_mask, though. ... like this: diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8447ece..c62e3b6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -779,14 +779,19 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) /* VMX MSR features */ +#define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull +#define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) +#define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) +#define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) +#define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 29865c3..7c5ad26 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -2500,7 +2500,10 @@ static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f) * Bits 0-30, 32-44 and 50-53 come from the host. KVM should * not change them for backwards compatibility. */ - uint64_t fixed_vmx_basic = kvm_vmx_basic & 0x003c1fff7fffffffULL; + uint64_t fixed_vmx_basic = kvm_vmx_basic & + (MSR_VMX_BASIC_VMCS_REVISION_MASK | + MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK | + MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK); /* * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can @@ -2509,14 +2512,17 @@ static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f) * not support dual-monitor treatment and probably never will; mask * them out as well. */ - uint64_t fixed_vmx_misc = kvm_vmx_misc & 0x0e00001f; + uint64_t fixed_vmx_misc = kvm_vmx_misc & + (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK | + MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK); /* * EPT memory types should not change either, so we do not bother * adding features for them. */ uint64_t fixed_vmx_ept_mask = - (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ? 0x4100ull : 0); + (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ? + MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0); uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask; kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS, Paolo