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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id m12sm4819733pjr.14.2021.10.29.10.38.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Oct 2021 10:38:53 -0700 (PDT) Subject: Re: [PATCH 07/31] target/loongarch: Add loongarch csr/iocsr instruction support To: yangxiaojuan , qemu-devel@nongnu.org References: <1634628917-10031-1-git-send-email-yangxiaojuan@loongson.cn> <1634628917-10031-8-git-send-email-yangxiaojuan@loongson.cn> <75e6250e-6cb5-6557-b9dd-ea3fdb0436e2@loongson.cn> From: Richard Henderson Message-ID: <4cc6e69b-56ca-4439-d88c-46ae1b5c2a6c@linaro.org> Date: Fri, 29 Oct 2021 10:38:51 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <75e6250e-6cb5-6557-b9dd-ea3fdb0436e2@loongson.cn> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.512, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, thuth@redhat.com, chenhuacai@loongson.cn, philmd@redhat.com, mark.cave-ayland@ilande.co.uk, laurent@vivier.eu, peterx@redhat.com, f4bug@amsat.org, alistair.francis@wdc.com, maobibo@loongson.cn, gaosong@loongson.cn, pbonzini@redhat.com, bmeng.cn@gmail.com, alex.bennee@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/28/21 11:26 PM, yangxiaojuan wrote: > (1) For the iocsr registers, most of them act on the interrupt controller, the read and write will go to interrupt's mmio read/write. > So I modified the addr to their mmio range. The ext interrupt controller use the sysbus's function to handle the interrupt cascade and > sysbus_mmio_map to map the address which use the system memory region. So if I use a different address space, I realize a different > sysbus_mmio_map function use a different address space, is it feasible ? You shouldn't need a different function at all. All of the difference will be in how you construct the mmio region: create a new address space, and add the mmio region to that address space at the correct base address. > (2)Can you help me review the remaining patches? Thanks. The remaining patches are harder for me to review, because I'm not as familiar with the fine details in hw/, but I'll try. r~