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Fri, 02 Aug 2024 06:30:38 -0700 (PDT) Message-ID: <4cdcacde-a5f8-4365-bd6c-65e98a77eada@linaro.org> Date: Fri, 2 Aug 2024 23:30:32 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 10/18] bsd-user: Add RISC-V thread setup and initialization support To: Ajeet Singh , qemu-devel@nongnu.org Cc: Warner Losh , Mark Corbin , Ajeet Singh , Jessica Clarke , Kyle Evans References: <20240802083423.142365-1-itachis@FreeBSD.org> <20240802083423.142365-11-itachis@FreeBSD.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240802083423.142365-11-itachis@FreeBSD.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/2/24 18:34, Ajeet Singh wrote: > From: Mark Corbin > > Implemented functions for setting up and initializing threads in the > RISC-V architecture. > The 'target_thread_set_upcall' function sets up the stack pointer, > program counter, and function argument for new threads. > The 'target_thread_init' function initializes thread registers based on > the provided image information. > > Signed-off-by: Mark Corbin > Signed-off-by: Ajeet Singh > Co-authored-by: Jessica Clarke > Co-authored-by: Kyle Evans > --- > bsd-user/riscv/target_arch_thread.h | 47 +++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > create mode 100644 bsd-user/riscv/target_arch_thread.h > > diff --git a/bsd-user/riscv/target_arch_thread.h b/bsd-user/riscv/target_arch_thread.h > new file mode 100644 > index 0000000000..faabb9fb45 > --- /dev/null > +++ b/bsd-user/riscv/target_arch_thread.h > @@ -0,0 +1,47 @@ > +/* > + * RISC-V thread support > + * > + * Copyright (c) 2019 Mark Corbin > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see . > + */ > + > +#ifndef TARGET_ARCH_THREAD_H > +#define TARGET_ARCH_THREAD_H > + > +/* Compare with cpu_set_upcall() in riscv/riscv/vm_machdep.c */ > +static inline void target_thread_set_upcall(CPURISCVState *regs, > + abi_ulong entry, abi_ulong arg, abi_ulong stack_base, > + abi_ulong stack_size) > +{ > + abi_ulong sp; > + > + sp = (abi_ulong)(stack_base + stack_size) & ~(16 - 1); > + > + regs->gpr[xSP] = sp; > + regs->pc = entry; > + regs->gpr[xA0] = arg; > +} > + > +/* Compare with exec_setregs() in riscv/riscv/machdep.c */ exec_machdep.c. > +static inline void target_thread_init(struct target_pt_regs *regs, > + struct image_info *infop) > +{ > + regs->sepc = infop->entry; > + regs->regs[xRA] = infop->entry; > + regs->regs[10] = infop->start_stack; /* a0 */ xA0 > + regs->regs[xSP] = infop->start_stack & ~(16 - 1); ROUND_DOWN. r~