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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id p3sm8110059pfg.184.2020.02.14.12.15.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Feb 2020 12:15:23 -0800 (PST) Subject: Re: [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200214175116.9164-1-peter.maydell@linaro.org> <20200214175116.9164-11-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <4d592ed0-10c3-683b-84d8-cf17a2d491dc@linaro.org> Date: Fri, 14 Feb 2020 12:15:21 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200214175116.9164-11-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/14/20 9:51 AM, Peter Maydell wrote: > The AArch32 DBGDIDR defines properties like the number of > breakpoints, watchpoints and context-matching comparators. On an > AArch64 CPU, the register may not even exist if AArch32 is not > supported at EL1. > > Currently we hard-code use of DBGDIDR to identify the number of > breakpoints etc; this works for all our TCG CPUs, but will break if > we ever add an AArch64-only CPU. We also have an assert() that the > AArch32 and AArch64 registers match, which currently works only by > luck for KVM because we don't populate either of these ID registers > from the KVM vCPU and so they are both zero. > > Clean this up so we have functions for finding the number > of breakpoints, watchpoints and context comparators which look > in the appropriate ID register. > > This allows us to drop the "check that AArch64 and AArch32 agree > on the number of breakpoints etc" asserts: > * we no longer look at the AArch32 versions unless that's the > right place to be looking > * it's valid to have a CPU (eg AArch64-only) where they don't match > * we shouldn't have been asserting the validity of ID registers > in a codepath used with KVM anyway > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 7 +++++++ > target/arm/internals.h | 42 +++++++++++++++++++++++++++++++++++++++ > target/arm/debug_helper.c | 6 +++--- > target/arm/helper.c | 21 +++++--------------- > 4 files changed, 57 insertions(+), 19 deletions(-) Reviewed-by: Richard Henderson r~