From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48263) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUEEl-000350-KW for qemu-devel@nongnu.org; Tue, 04 Dec 2018 12:12:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUE5s-0008FJ-0Y for qemu-devel@nongnu.org; Tue, 04 Dec 2018 12:02:48 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:34616) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gUE5r-0008Ee-Qt for qemu-devel@nongnu.org; Tue, 04 Dec 2018 12:02:43 -0500 Received: by mail-wr1-f67.google.com with SMTP id j2so16768262wrw.1 for ; Tue, 04 Dec 2018 09:02:43 -0800 (PST) References: <154393964026.28192.13536237934563059985.stgit@gimli.home> <154394076572.28192.17922483382108051842.stgit@gimli.home> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <4d705555-4d3f-5db9-f58c-ad18ef2e1348@redhat.com> Date: Tue, 4 Dec 2018 18:02:39 +0100 MIME-Version: 1.0 In-Reply-To: <154394076572.28192.17922483382108051842.stgit@gimli.home> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [for-4.0 PATCH v3 1/9] pcie: Create enums for link speed and width List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex Williamson , qemu-devel@nongnu.org Cc: Geoffrey McRae , "Michael S. Tsirkin" On 4/12/18 17:26, Alex Williamson wrote: > In preparation for reporting higher virtual link speeds and widths, > create enums and macros to help us manage them. > > Cc: Michael S. Tsirkin > Cc: Marcel Apfelbaum > Tested-by: Geoffrey McRae > Signed-off-by: Alex Williamson Reviewed-by: Philippe Mathieu-Daudé > --- > hw/pci/pcie.c | 7 ++++--- > hw/vfio/pci.c | 3 ++- > include/hw/pci/pcie_regs.h | 23 +++++++++++++++++++++-- > 3 files changed, 27 insertions(+), 6 deletions(-) > > diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c > index 6c91bd44a0a5..914a5261a79b 100644 > --- a/hw/pci/pcie.c > +++ b/hw/pci/pcie.c > @@ -68,11 +68,12 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) > pci_set_long(exp_cap + PCI_EXP_LNKCAP, > (port << PCI_EXP_LNKCAP_PN_SHIFT) | > PCI_EXP_LNKCAP_ASPMS_0S | > - PCI_EXP_LNK_MLW_1 | > - PCI_EXP_LNK_LS_25); > + QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) | > + QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT)); > > pci_set_word(exp_cap + PCI_EXP_LNKSTA, > - PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25); > + QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) | > + QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT)); > > if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { > pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, > diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c > index 5c7bd9698496..74f9a46b4be0 100644 > --- a/hw/vfio/pci.c > +++ b/hw/vfio/pci.c > @@ -1897,7 +1897,8 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, > PCI_EXP_TYPE_ENDPOINT << 4, > PCI_EXP_FLAGS_TYPE); > vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, > - PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25, ~0); > + QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) | > + QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT), ~0); > vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); > } > > diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h > index a95522a13b04..ad4e7808b8ac 100644 > --- a/include/hw/pci/pcie_regs.h > +++ b/include/hw/pci/pcie_regs.h > @@ -34,10 +34,29 @@ > > /* PCI_EXP_LINK{CAP, STA} */ > /* link speed */ > -#define PCI_EXP_LNK_LS_25 1 > +typedef enum PCIExpLinkSpeed { > + QEMU_PCI_EXP_LNK_2_5GT = 1, > + QEMU_PCI_EXP_LNK_5GT, > + QEMU_PCI_EXP_LNK_8GT, > + QEMU_PCI_EXP_LNK_16GT, > +} PCIExpLinkSpeed; > + > +#define QEMU_PCI_EXP_LNKCAP_MLS(speed) (speed) > +#define QEMU_PCI_EXP_LNKSTA_CLS QEMU_PCI_EXP_LNKCAP_MLS > + > +typedef enum PCIExpLinkWidth { > + QEMU_PCI_EXP_LNK_X1 = 1, > + QEMU_PCI_EXP_LNK_X2 = 2, > + QEMU_PCI_EXP_LNK_X4 = 4, > + QEMU_PCI_EXP_LNK_X8 = 8, > + QEMU_PCI_EXP_LNK_X12 = 12, > + QEMU_PCI_EXP_LNK_X16 = 16, > + QEMU_PCI_EXP_LNK_X32 = 32, > +} PCIExpLinkWidth; > > #define PCI_EXP_LNK_MLW_SHIFT ctz32(PCI_EXP_LNKCAP_MLW) > -#define PCI_EXP_LNK_MLW_1 (1 << PCI_EXP_LNK_MLW_SHIFT) > +#define QEMU_PCI_EXP_LNKCAP_MLW(width) (width << PCI_EXP_LNK_MLW_SHIFT) > +#define QEMU_PCI_EXP_LNKSTA_NLW QEMU_PCI_EXP_LNKCAP_MLW > > /* PCI_EXP_LINKCAP */ > #define PCI_EXP_LNKCAP_ASPMS_SHIFT ctz32(PCI_EXP_LNKCAP_ASPMS) > >