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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id 67sm2058492pfe.168.2020.03.14.23.57.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Mar 2020 23:57:57 -0700 (PDT) Subject: Re: [PATCH v5 48/60] target/riscv: vector mask-register logical instructions References: <86d7d5d0-37c9-e1c3-49d5-984d40e9c4a9@linaro.org> To: qemu-devel , liuzhiwei From: Richard Henderson X-Forwarded-Message-Id: <86d7d5d0-37c9-e1c3-49d5-984d40e9c4a9@linaro.org> Message-ID: <4d8c2d9f-8c26-db73-ce87-002c0118ef4e@linaro.org> Date: Sat, 14 Mar 2020 23:57:55 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <86d7d5d0-37c9-e1c3-49d5-984d40e9c4a9@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Ho hum, failed to send to the list first time. -------- Forwarded Message -------- Subject: Re: [PATCH v5 48/60] target/riscv: vector mask-register logical instructions Date: Sat, 14 Mar 2020 23:41:59 -0700 From: Richard Henderson To: LIU Zhiwei [ Patch didn't make it to the list, so reviewing https://github.com/romanheros/qemu/commit/8c782677c21909f80c481cfd7ab58c076761642c ] This is ok as-is, so Reviewed-by: Richard Henderson But you can do better. > > /* Vector Mask-Register Logical Instructions */ > #define GEN_MM_TRANS(NAME) \ > static bool trans_##NAME(DisasContext *s, arg_r *a) \ > { \ > if (vext_check_isa_ill(s, RVV)) { \ > uint32_t data = 0; \ > gen_helper_gvec_4_ptr * fn = gen_helper_##NAME; \ > data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ > data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ > tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ > vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), \ > cpu_env, 0, s->vlen / 8, data, fn); \ > return true; \ > } \ > return false; \ > } > GEN_MM_TRANS(vmand_mm) > GEN_MM_TRANS(vmnand_mm) > GEN_MM_TRANS(vmandnot_mm) > GEN_MM_TRANS(vmxor_mm) > GEN_MM_TRANS(vmor_mm) > GEN_MM_TRANS(vmnor_mm) > GEN_MM_TRANS(vmornot_mm) > GEN_MM_TRANS(vmxnor_mm) For vl_eq_vlmax, we should use gvec. For mlen == 1, nothing more is needed, as all bits are significant. For mlen > 1, we can use tcg_gen_gvec_andi(MO_64, vreg_ofs(s, a->rd), vreg_ofs(s, a->rd), pred_mlen_masks[log2_mlen], s->vlen / 8, s->vlen / 8); where pred_mlen_masks[] are as discussed vs 49/60 (vmpopc). It might be worth noticing vmclr.mm, which of course does not require that andi. > /* Vector Mask-Register Logical Instructions */ > #define GEN_VEXT_MASK_VV(NAME, OP) \ > void HELPER(NAME)(void *vd, void *v0, void *vs1, \ > void *vs2, CPURISCVState *env, uint32_t desc) \ > { \ > uint32_t mlen = vext_mlen(desc); \ > uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ > uint32_t vl = env->vl; \ > uint32_t i; \ > int a, b; \ > for (i = 0; i < vl; i++) { \ > a = vext_elem_mask(vs1, mlen, i); \ > b = vext_elem_mask(vs2, mlen, i); \ > vext_set_elem_mask(vd, mlen, i, OP(b, a)); \ > } \ > if (i == 0) { \ > return; \ > } \ > for (; i < vlmax; i++) { \ > vext_set_elem_mask(vd, mlen, i, 0); \ > } \ > } > #define DO_NAND(N, M) (!(N & M)) > #define DO_ANDNOT(N, M) (N & !M) > #define DO_NOR(N, M) (!(N | M)) > #define DO_ORNOT(N, M) (N | !M) > #define DO_XNOR(N, M) (!(N ^ M)) Again, these operations can be done in units of uint64_t, applying the pred_msize_mask and the residual "rmask" that I mentoned wrt vmpopc. This would mean that you'd want bitwise, not logical nots above in your DO_* macros. r~