* Re: [PATCH v5 48/60] target/riscv: vector mask-register logical instructions [not found] <86d7d5d0-37c9-e1c3-49d5-984d40e9c4a9@linaro.org> @ 2020-03-15 6:57 ` Richard Henderson 0 siblings, 0 replies; 2+ messages in thread From: Richard Henderson @ 2020-03-15 6:57 UTC (permalink / raw) To: qemu-devel, liuzhiwei Ho hum, failed to send to the list first time. -------- Forwarded Message -------- Subject: Re: [PATCH v5 48/60] target/riscv: vector mask-register logical instructions Date: Sat, 14 Mar 2020 23:41:59 -0700 From: Richard Henderson <richard.henderson@linaro.org> To: LIU Zhiwei <zhiwei_liu@c-sky.com> [ Patch didn't make it to the list, so reviewing https://github.com/romanheros/qemu/commit/8c782677c21909f80c481cfd7ab58c076761642c ] This is ok as-is, so Reviewed-by: Richard Henderson <richard.henderson@linaro.org> But you can do better. > > /* Vector Mask-Register Logical Instructions */ > #define GEN_MM_TRANS(NAME) \ > static bool trans_##NAME(DisasContext *s, arg_r *a) \ > { \ > if (vext_check_isa_ill(s, RVV)) { \ > uint32_t data = 0; \ > gen_helper_gvec_4_ptr * fn = gen_helper_##NAME; \ > data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ > data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ > tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ > vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), \ > cpu_env, 0, s->vlen / 8, data, fn); \ > return true; \ > } \ > return false; \ > } > GEN_MM_TRANS(vmand_mm) > GEN_MM_TRANS(vmnand_mm) > GEN_MM_TRANS(vmandnot_mm) > GEN_MM_TRANS(vmxor_mm) > GEN_MM_TRANS(vmor_mm) > GEN_MM_TRANS(vmnor_mm) > GEN_MM_TRANS(vmornot_mm) > GEN_MM_TRANS(vmxnor_mm) For vl_eq_vlmax, we should use gvec. For mlen == 1, nothing more is needed, as all bits are significant. For mlen > 1, we can use tcg_gen_gvec_andi(MO_64, vreg_ofs(s, a->rd), vreg_ofs(s, a->rd), pred_mlen_masks[log2_mlen], s->vlen / 8, s->vlen / 8); where pred_mlen_masks[] are as discussed vs 49/60 (vmpopc). It might be worth noticing vmclr.mm, which of course does not require that andi. > /* Vector Mask-Register Logical Instructions */ > #define GEN_VEXT_MASK_VV(NAME, OP) \ > void HELPER(NAME)(void *vd, void *v0, void *vs1, \ > void *vs2, CPURISCVState *env, uint32_t desc) \ > { \ > uint32_t mlen = vext_mlen(desc); \ > uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ > uint32_t vl = env->vl; \ > uint32_t i; \ > int a, b; \ > for (i = 0; i < vl; i++) { \ > a = vext_elem_mask(vs1, mlen, i); \ > b = vext_elem_mask(vs2, mlen, i); \ > vext_set_elem_mask(vd, mlen, i, OP(b, a)); \ > } \ > if (i == 0) { \ > return; \ > } \ > for (; i < vlmax; i++) { \ > vext_set_elem_mask(vd, mlen, i, 0); \ > } \ > } > #define DO_NAND(N, M) (!(N & M)) > #define DO_ANDNOT(N, M) (N & !M) > #define DO_NOR(N, M) (!(N | M)) > #define DO_ORNOT(N, M) (N | !M) > #define DO_XNOR(N, M) (!(N ^ M)) Again, these operations can be done in units of uint64_t, applying the pred_msize_mask and the residual "rmask" that I mentoned wrt vmpopc. This would mean that you'd want bitwise, not logical nots above in your DO_* macros. r~ ^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH v5 00/60] target/riscv: support vector extension v0.7.1
@ 2020-03-12 14:58 LIU Zhiwei
2020-03-12 14:58 ` [PATCH v5 48/60] target/riscv: vector mask-register logical instructions LIU Zhiwei
0 siblings, 1 reply; 2+ messages in thread
From: LIU Zhiwei @ 2020-03-12 14:58 UTC (permalink / raw)
To: richard.henderson, alistair23, chihmin.chao, palmer
Cc: guoren, qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang,
LIU Zhiwei
This patchset implements the vector extension for RISC-V on QEMU.
You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v3).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode programs.
You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh.
Features:
* support specification riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/)
* support basic vector extension.
* support Zvlsseg.
* support Zvamo.
* not support Zvediv as it is changing.
* SLEN always equals VLEN.
* element width support 8bit, 16bit, 32bit, 64bit.
Changelog:
v5
* fixup a bug in tb flags.
v4
* no change
v3
* move check code from execution-time to translation-time
* use a continous memory block for vector register description.
* vector registers as direct fields in RISCVCPUState.
* support VLEN configure from qemu command line.
* support ELEN configure from qemu command line.
* support vector specification version configure from qemu command line.
* probe pages before real load or store access.
* use probe_page_check for no-fault operations in linux user mode.
* generation atomic exit exception when in parallel environment.
* fixup a lot of concrete bugs.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (60):
target/riscv: add vector extension field in CPURISCVState
target/riscv: implementation-defined constant parameters
target/riscv: support vector extension csr
target/riscv: add vector configure instruction
target/riscv: add vector stride load and store instructions
target/riscv: add vector index load and store instructions
target/riscv: add fault-only-first unit stride load
target/riscv: add vector amo operations
target/riscv: vector single-width integer add and subtract
target/riscv: vector widening integer add and subtract
target/riscv: vector integer add-with-carry / subtract-with-borrow
instructions
target/riscv: vector bitwise logical instructions
target/riscv: vector single-width bit shift instructions
target/riscv: vector narrowing integer right shift instructions
target/riscv: vector integer comparison instructions
target/riscv: vector integer min/max instructions
target/riscv: vector single-width integer multiply instructions
target/riscv: vector integer divide instructions
target/riscv: vector widening integer multiply instructions
target/riscv: vector single-width integer multiply-add instructions
target/riscv: vector widening integer multiply-add instructions
target/riscv: vector integer merge and move instructions
target/riscv: vector single-width saturating add and subtract
target/riscv: vector single-width averaging add and subtract
target/riscv: vector single-width fractional multiply with rounding
and saturation
target/riscv: vector widening saturating scaled multiply-add
target/riscv: vector single-width scaling shift instructions
target/riscv: vector narrowing fixed-point clip instructions
target/riscv: vector single-width floating-point add/subtract
instructions
target/riscv: vector widening floating-point add/subtract instructions
target/riscv: vector single-width floating-point multiply/divide
instructions
target/riscv: vector widening floating-point multiply
target/riscv: vector single-width floating-point fused multiply-add
instructions
target/riscv: vector widening floating-point fused multiply-add
instructions
target/riscv: vector floating-point square-root instruction
target/riscv: vector floating-point min/max instructions
target/riscv: vector floating-point sign-injection instructions
target/riscv: vector floating-point compare instructions
target/riscv: vector floating-point classify instructions
target/riscv: vector floating-point merge instructions
target/riscv: vector floating-point/integer type-convert instructions
target/riscv: widening floating-point/integer type-convert
instructions
target/riscv: narrowing floating-point/integer type-convert
instructions
target/riscv: vector single-width integer reduction instructions
target/riscv: vector wideing integer reduction instructions
target/riscv: vector single-width floating-point reduction
instructions
target/riscv: vector widening floating-point reduction instructions
target/riscv: vector mask-register logical instructions
target/riscv: vector mask population count vmpopc
target/riscv: vmfirst find-first-set mask bit
target/riscv: set-X-first mask bit
target/riscv: vector iota instruction
target/riscv: vector element index instruction
target/riscv: integer extract instruction
target/riscv: integer scalar move instruction
target/riscv: floating-point scalar move instructions
target/riscv: vector slide instructions
target/riscv: vector register gather instruction
target/riscv: vector compress instruction
target/riscv: configure and turn on vector extension from command line
target/riscv/Makefile.objs | 2 +-
target/riscv/cpu.c | 49 +
target/riscv/cpu.h | 89 +-
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 +-
target/riscv/helper.h | 1075 +++++
target/riscv/insn32-64.decode | 11 +
target/riscv/insn32.decode | 366 ++
target/riscv/insn_trans/trans_rvv.inc.c | 2386 ++++++++++++
target/riscv/translate.c | 24 +-
target/riscv/vector_helper.c | 4745 +++++++++++++++++++++++
11 files changed, 8824 insertions(+), 13 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
create mode 100644 target/riscv/vector_helper.c
--
2.23.0
^ permalink raw reply [flat|nested] 2+ messages in thread* [PATCH v5 48/60] target/riscv: vector mask-register logical instructions 2020-03-12 14:58 [PATCH v5 00/60] target/riscv: support vector extension v0.7.1 LIU Zhiwei @ 2020-03-12 14:58 ` LIU Zhiwei 0 siblings, 0 replies; 2+ messages in thread From: LIU Zhiwei @ 2020-03-12 14:58 UTC (permalink / raw) To: richard.henderson, alistair23, chihmin.chao, palmer Cc: guoren, qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, LIU Zhiwei Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 9 ++++++ target/riscv/insn32.decode | 8 +++++ target/riscv/insn_trans/trans_rvv.inc.c | 28 +++++++++++++++++ target/riscv/vector_helper.c | 40 +++++++++++++++++++++++++ 4 files changed, 85 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b0bb617b42..9301ce0e00 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1074,3 +1074,12 @@ DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmandnot_mm, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmxor_mm, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmor_mm, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f1efc8886d..76a9bae8bb 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -539,6 +539,14 @@ vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm # Vector widening ordered and unordered float reduction sum vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm +vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r +vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r +vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r +vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r +vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r +vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r +vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r +vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index ad864c9742..065b415abb 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2052,3 +2052,31 @@ GEN_OPFVV_TRANS(vfredmin_vs, reduction_check) /* Vector Widening Floating-Point Reduction Instructions */ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) + +/* + *** Vector Mask Operations + */ +/* Vector Mask-Register Logical Instructions */ +#define GEN_MM_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_r *a) \ +{ \ + if (vext_check_isa_ill(s, RVV)) { \ + uint32_t data = 0; \ + gen_helper_gvec_4_ptr * fn = gen_helper_##NAME; \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), \ + cpu_env, 0, s->vlen / 8, data, fn); \ + return true; \ + } \ + return false; \ +} +GEN_MM_TRANS(vmand_mm) +GEN_MM_TRANS(vmnand_mm) +GEN_MM_TRANS(vmandnot_mm) +GEN_MM_TRANS(vmxor_mm) +GEN_MM_TRANS(vmor_mm) +GEN_MM_TRANS(vmnor_mm) +GEN_MM_TRANS(vmornot_mm) +GEN_MM_TRANS(vmxnor_mm) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index d325fe5e2e..9e9d172cda 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4238,3 +4238,43 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, clearq(vd, 1, sizeof(uint64_t), tot); } } + +/* + *** Vector Mask Operations + */ +/* Vector Mask-Register Logical Instructions */ +#define GEN_VEXT_MASK_VV(NAME, OP) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ + void *vs2, CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vl = env->vl; \ + uint32_t i; \ + int a, b; \ + for (i = 0; i < vl; i++) { \ + a = vext_elem_mask(vs1, mlen, i); \ + b = vext_elem_mask(vs2, mlen, i); \ + vext_set_elem_mask(vd, mlen, i, OP(b, a)); \ + } \ + if (i == 0) { \ + return; \ + } \ + for (; i < vlmax; i++) { \ + vext_set_elem_mask(vd, mlen, i, 0); \ + } \ +} +#define DO_NAND(N, M) (!(N & M)) +#define DO_ANDNOT(N, M) (N & !M) +#define DO_NOR(N, M) (!(N | M)) +#define DO_ORNOT(N, M) (N | !M) +#define DO_XNOR(N, M) (!(N ^ M)) + +GEN_VEXT_MASK_VV(vmand_mm, DO_AND) +GEN_VEXT_MASK_VV(vmnand_mm, DO_NAND) +GEN_VEXT_MASK_VV(vmandnot_mm, DO_ANDNOT) +GEN_VEXT_MASK_VV(vmxor_mm, DO_XOR) +GEN_VEXT_MASK_VV(vmor_mm, DO_OR) +GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR) +GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT) +GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR) -- 2.23.0 ^ permalink raw reply related [flat|nested] 2+ messages in thread
end of thread, other threads:[~2020-03-15 6:59 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
[not found] <86d7d5d0-37c9-e1c3-49d5-984d40e9c4a9@linaro.org>
2020-03-15 6:57 ` [PATCH v5 48/60] target/riscv: vector mask-register logical instructions Richard Henderson
2020-03-12 14:58 [PATCH v5 00/60] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-03-12 14:58 ` [PATCH v5 48/60] target/riscv: vector mask-register logical instructions LIU Zhiwei
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).