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Tue, 17 Aug 2021 13:41:10 -0700 (PDT) Received: from [192.168.3.43] ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id 11sm4072922pgh.52.2021.08.17.13.41.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Aug 2021 13:41:10 -0700 (PDT) Subject: Re: [PATCH] target/arm: Do hflags rebuild in cpsr_write() To: Peter Maydell , qemu-arm , QEMU Developers References: <20210817201843.3829-1-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <4db339d0-8350-8099-0e28-eeb4b5a5a1a0@linaro.org> Date: Tue, 17 Aug 2021 10:41:07 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.961, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/17/21 10:26 AM, Peter Maydell wrote: > On Tue, 17 Aug 2021 at 21:18, Peter Maydell wrote: >> >> Currently we rely on all the callsites of cpsr_write() to rebuild the >> cached hflags if they change one of the CPSR bits which we use as a >> TB flag and cache in hflags. This is a bit awkward when we want to >> change the set of CPSR bits that we cache, because it means we need >> to re-audit all the cpsr_write() callsites to see which flags they >> are writing and whether they now need to rebuild the hflags. >> >> Switch instead to making cpsr_write() call arm_rebuild_hflags() >> itself if one of the bits being changed is a cached bit. >> >> We don't do the rebuild for the CPSRWriteRaw write type, > > Doh. I said this, but then... > >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index 201ecf8c67f..cdd6e0858fc 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -9215,6 +9215,7 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, >> CPSRWriteType write_type) >> { >> uint32_t changed_daif; >> + bool rebuild_hflags = mask & (CPSR_M | CPSR_E | CPSR_IL); > > ...forgot to actually check the write type. > > Should be: > > bool rebuild_hflags = (write_type != CPSRWriteRaw) && > (mask & (CPSR_M | CPSR_E | CPSR_IL)); with the fix, Reviewed-by: Richard Henderson r~