[Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[Tsuneo Saito]

Hi,

This patch series implements sparcv9 stfa/ldfa instructions with
non block-transfer ASIs that implementations seem to be left unfinished.
This patch also adds fp_disabled exception checks on stfa/ldfa
as they are FP instructions.

 target-sparc/op_helper.c |   31 ++++++++++++++++++++++---------
 target-sparc/translate.c |   14 ++++++++++++--
 2 files changed, 34 insertions(+), 11 deletions(-)

[Qemu-devel] [PATCH 1/4] SPARC64: Implement ldfa/lddfa/ldqfa instructions properly

[Tsuneo Saito]

This patch implements sparcv9 ldfa/lddfa/ldqfa instructions
with non block-load ASIs.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/op_helper.c |   16 +++++++++++-----
 1 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index fd0cfbd..a75ac4f 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -3331,7 +3331,7 @@ void helper_ldda_asi(target_ulong addr, int asi, int rd)
 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
 {
     unsigned int i;
-    target_ulong val;
+    CPU_DoubleU u;
 
     helper_check_align(addr, 3);
     addr = asi_address_mask(env, asi, addr);
@@ -3371,17 +3371,23 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
         break;
     }
 
-    val = helper_ld_asi(addr, asi, size, 0);
     switch(size) {
     default:
     case 4:
-        *((uint32_t *)&env->fpr[rd]) = val;
+        *((uint32_t *)&env->fpr[rd]) = helper_ld_asi(addr, asi, size, 0);
         break;
     case 8:
-        *((int64_t *)&DT0) = val;
+        u.ll = helper_ld_asi(addr, asi, size, 0);
+        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
+        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
         break;
     case 16:
-        // XXX
+        u.ll = helper_ld_asi(addr, asi, 8, 0);
+        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
+        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
+        u.ll = helper_ld_asi(addr + 8, asi, 8, 0);
+        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
+        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
         break;
     }
 }
-- 
1.7.5.4

Re: [Qemu-devel] [PATCH 1/4] SPARC64: Implement ldfa/lddfa/ldqfa instructions properly

[Blue Swirl]

On Wed, Jul 13, 2011 at 6:30 AM, Tsuneo Saito <tsnsaito@gmail.com> wrote:
> This patch implements sparcv9 ldfa/lddfa/ldqfa instructions
> with non block-load ASIs.
>
> Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
> ---
>  target-sparc/op_helper.c |   16 +++++++++++-----
>  1 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
> index fd0cfbd..a75ac4f 100644
> --- a/target-sparc/op_helper.c
> +++ b/target-sparc/op_helper.c
> @@ -3331,7 +3331,7 @@ void helper_ldda_asi(target_ulong addr, int asi, int rd)
>  void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
>  {
>     unsigned int i;
> -    target_ulong val;
> +    CPU_DoubleU u;
>
>     helper_check_align(addr, 3);
>     addr = asi_address_mask(env, asi, addr);
> @@ -3371,17 +3371,23 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
>         break;
>     }
>
> -    val = helper_ld_asi(addr, asi, size, 0);
>     switch(size) {
>     default:
>     case 4:
> -        *((uint32_t *)&env->fpr[rd]) = val;
> +        *((uint32_t *)&env->fpr[rd]) = helper_ld_asi(addr, asi, size, 0);
>         break;
>     case 8:
> -        *((int64_t *)&DT0) = val;
> +        u.ll = helper_ld_asi(addr, asi, size, 0);
> +        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
> +        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
>         break;
>     case 16:
> -        // XXX
> +        u.ll = helper_ld_asi(addr, asi, 8, 0);
> +        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
> +        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
> +        u.ll = helper_ld_asi(addr + 8, asi, 8, 0);

In general the patch is an improvement, however the ASIs are passed as
is to helper_ld_asi() and there the block ASIs would trigger
unassigned access faults. So you should perform some arithmetic with
the ASI numbers to make them match non-block ASIs, for example asi &
~0x6. This only works in the specific block ASIs, so I'd move this
inside the switch block for cases 0x16, 0x17, 0x1e, 0x1f etc. By the
way, aren't those the ASIs in question? The manual (UltraSPARC
Architecture 2007) is a bit confusing.

> +        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
> +        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
>         break;
>     }
>  }
> --
> 1.7.5.4
>
>
>

Re: [Qemu-devel] [PATCH 1/4] SPARC64: Implement ldfa/lddfa/ldqfa instructions properly

[Artyom Tarasenko]

On Wed, Jul 13, 2011 at 6:27 PM, Blue Swirl <blauwirbel@gmail.com> wrote:
> On Wed, Jul 13, 2011 at 6:30 AM, Tsuneo Saito <tsnsaito@gmail.com> wrote:
>> This patch implements sparcv9 ldfa/lddfa/ldqfa instructions
>> with non block-load ASIs.
>>
>> Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
>> ---
>>  target-sparc/op_helper.c |   16 +++++++++++-----
>>  1 files changed, 11 insertions(+), 5 deletions(-)
>>
>> diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
>> index fd0cfbd..a75ac4f 100644
>> --- a/target-sparc/op_helper.c
>> +++ b/target-sparc/op_helper.c
>> @@ -3331,7 +3331,7 @@ void helper_ldda_asi(target_ulong addr, int asi, int rd)
>>  void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
>>  {
>>     unsigned int i;
>> -    target_ulong val;
>> +    CPU_DoubleU u;
>>
>>     helper_check_align(addr, 3);
>>     addr = asi_address_mask(env, asi, addr);
>> @@ -3371,17 +3371,23 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
>>         break;
>>     }
>>
>> -    val = helper_ld_asi(addr, asi, size, 0);
>>     switch(size) {
>>     default:
>>     case 4:
>> -        *((uint32_t *)&env->fpr[rd]) = val;
>> +        *((uint32_t *)&env->fpr[rd]) = helper_ld_asi(addr, asi, size, 0);
>>         break;
>>     case 8:
>> -        *((int64_t *)&DT0) = val;
>> +        u.ll = helper_ld_asi(addr, asi, size, 0);
>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
>>         break;
>>     case 16:
>> -        // XXX
>> +        u.ll = helper_ld_asi(addr, asi, 8, 0);
>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
>> +        u.ll = helper_ld_asi(addr + 8, asi, 8, 0);
>
> In general the patch is an improvement, however the ASIs are passed as
> is to helper_ld_asi() and there the block ASIs would trigger
> unassigned access faults.

You mean the not [yet] implemented block ASIs? The implemented ones
return earlier
and for the not implemented ones unassigned access fault appears to be
a right thing to do.
Do you have an example where we would have an unassigned access fault
for an implemented ASI ?

>So you should perform some arithmetic with
> the ASI numbers to make them match non-block ASIs, for example asi &
> ~0x6. This only works in the specific block ASIs, so I'd move this
> inside the switch block for cases 0x16, 0x17, 0x1e, 0x1f etc. By the
> way, aren't those the ASIs in question? The manual (UltraSPARC
> Architecture 2007) is a bit confusing.
>
>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
>>         break;
>>     }
>>  }
>> --
>> 1.7.5.4
>>



-- 
Regards,
Artyom Tarasenko

solaris/sparc under qemu blog: http://tyom.blogspot.com/

Re: [Qemu-devel] [PATCH 1/4] SPARC64: Implement ldfa/lddfa/ldqfa instructions properly

[Blue Swirl]

On Wed, Jul 13, 2011 at 9:02 PM, Artyom Tarasenko <atar4qemu@gmail.com> wrote:
> On Wed, Jul 13, 2011 at 6:27 PM, Blue Swirl <blauwirbel@gmail.com> wrote:
>> On Wed, Jul 13, 2011 at 6:30 AM, Tsuneo Saito <tsnsaito@gmail.com> wrote:
>>> This patch implements sparcv9 ldfa/lddfa/ldqfa instructions
>>> with non block-load ASIs.
>>>
>>> Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
>>> ---
>>>  target-sparc/op_helper.c |   16 +++++++++++-----
>>>  1 files changed, 11 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
>>> index fd0cfbd..a75ac4f 100644
>>> --- a/target-sparc/op_helper.c
>>> +++ b/target-sparc/op_helper.c
>>> @@ -3331,7 +3331,7 @@ void helper_ldda_asi(target_ulong addr, int asi, int rd)
>>>  void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
>>>  {
>>>     unsigned int i;
>>> -    target_ulong val;
>>> +    CPU_DoubleU u;
>>>
>>>     helper_check_align(addr, 3);
>>>     addr = asi_address_mask(env, asi, addr);
>>> @@ -3371,17 +3371,23 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
>>>         break;
>>>     }
>>>
>>> -    val = helper_ld_asi(addr, asi, size, 0);
>>>     switch(size) {
>>>     default:
>>>     case 4:
>>> -        *((uint32_t *)&env->fpr[rd]) = val;
>>> +        *((uint32_t *)&env->fpr[rd]) = helper_ld_asi(addr, asi, size, 0);
>>>         break;
>>>     case 8:
>>> -        *((int64_t *)&DT0) = val;
>>> +        u.ll = helper_ld_asi(addr, asi, size, 0);
>>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
>>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
>>>         break;
>>>     case 16:
>>> -        // XXX
>>> +        u.ll = helper_ld_asi(addr, asi, 8, 0);
>>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
>>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
>>> +        u.ll = helper_ld_asi(addr + 8, asi, 8, 0);
>>
>> In general the patch is an improvement, however the ASIs are passed as
>> is to helper_ld_asi() and there the block ASIs would trigger
>> unassigned access faults.
>
> You mean the not [yet] implemented block ASIs? The implemented ones
> return earlier
> and for the not implemented ones unassigned access fault appears to be
> a right thing to do.
> Do you have an example where we would have an unassigned access fault
> for an implemented ASI ?

This patch would implement the unimplemented ones by calling
helper_ld_asi(), but the ASIs do not match. Instead of 0x1f (as if
user little endian secondary address space block ASI), 0x19
(corresponding non-block ASI) should be used. Also helper_ld_asi()
should not be changed to accept block ASIs, because then they would be
accepted also for non-block accesses.

>>So you should perform some arithmetic with
>> the ASI numbers to make them match non-block ASIs, for example asi &
>> ~0x6. This only works in the specific block ASIs, so I'd move this
>> inside the switch block for cases 0x16, 0x17, 0x1e, 0x1f etc. By the
>> way, aren't those the ASIs in question? The manual (UltraSPARC
>> Architecture 2007) is a bit confusing.
>>
>>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
>>> +        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
>>>         break;
>>>     }
>>>  }
>>> --
>>> 1.7.5.4
>>>
>
>
>
> --
> Regards,
> Artyom Tarasenko
>
> solaris/sparc under qemu blog: http://tyom.blogspot.com/
>

Re: [Qemu-devel] [PATCH 1/4] SPARC64: Implement ldfa/lddfa/ldqfa instructions properly

[tsnsaito]

Hi,

At Wed, 13 Jul 2011 21:19:16 +0300,
Blue Swirl wrote:
> On Wed, Jul 13, 2011 at 9:02 PM, Artyom Tarasenko <atar4qemu@gmail.com> wrote:
> > On Wed, Jul 13, 2011 at 6:27 PM, Blue Swirl <blauwirbel@gmail.com> wrote:
> >> On Wed, Jul 13, 2011 at 6:30 AM, Tsuneo Saito <tsnsaito@gmail.com> wrote:
> >>So you should perform some arithmetic with
> >> the ASI numbers to make them match non-block ASIs, for example asi &
> >> ~0x6. This only works in the specific block ASIs, so I'd move this
> >> inside the switch block for cases 0x16, 0x17, 0x1e, 0x1f etc. By the
> >> way, aren't those the ASIs in question? The manual (UltraSPARC
> >> Architecture 2007) is a bit confusing.

Thanks for the review!
I didn't know these ASIs (0x16, 0x17, 0x1e, 0x1f) as I was looking
at the JPS 1.0.4 specification.  I'll add codes for these ASIs.

---- 
Tsuneo Saito <tsnsaito@gmail.com>

[Qemu-devel] [PATCH 2/4] SPARC64: fp_disabled checks on ldfa/lddfa/ldqfa

[Tsuneo Saito]

ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/translate.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index f32a674..d07eb25 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -4484,10 +4484,14 @@ static void disas_sparc_insn(DisasContext * dc)
                 case 0x2d: /* V9 prefetch, no effect */
                     goto skip_move;
                 case 0x30: /* V9 ldfa */
+                    if (gen_trap_ifnofpu(dc, cpu_cond))
+                        goto jmp_insn;
                     save_state(dc, cpu_cond);
                     gen_ldf_asi(cpu_addr, insn, 4, rd);
                     goto skip_move;
                 case 0x33: /* V9 lddfa */
+                    if (gen_trap_ifnofpu(dc, cpu_cond))
+                        goto jmp_insn;
                     save_state(dc, cpu_cond);
                     gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
                     goto skip_move;
@@ -4495,6 +4499,8 @@ static void disas_sparc_insn(DisasContext * dc)
                     goto skip_move;
                 case 0x32: /* V9 ldqfa */
                     CHECK_FPU_FEATURE(dc, FLOAT128);
+                    if (gen_trap_ifnofpu(dc, cpu_cond))
+                        goto jmp_insn;
                     save_state(dc, cpu_cond);
                     gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
                     goto skip_move;
-- 
1.7.5.4

[Qemu-devel] [PATCH 3/4] SPARC64: Implement stfa/stdfa/stqfa instrcutions properly

[Tsuneo Saito]

This patch implements sparcv9 stfa/stdfa/stqfa instructions
with non block-store ASIs.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/op_helper.c |   15 +++++++++++----
 target-sparc/translate.c |    2 --
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index a75ac4f..fe71829 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -3396,6 +3396,7 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
 {
     unsigned int i;
     target_ulong val = 0;
+    CPU_DoubleU u;
 
     helper_check_align(addr, 3);
     addr = asi_address_mask(env, asi, addr);
@@ -3440,16 +3441,22 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
     switch(size) {
     default:
     case 4:
-        val = *((uint32_t *)&env->fpr[rd]);
+        helper_st_asi(addr, *(uint32_t *)&env->fpr[rd], asi, size);
         break;
     case 8:
-        val = *((int64_t *)&DT0);
+        u.l.upper = *(uint32_t *)&env->fpr[rd++];
+        u.l.lower = *(uint32_t *)&env->fpr[rd++];
+        helper_st_asi(addr, u.ll, asi, size);
         break;
     case 16:
-        // XXX
+        u.l.upper = *(uint32_t *)&env->fpr[rd++];
+        u.l.lower = *(uint32_t *)&env->fpr[rd++];
+        helper_st_asi(addr, u.ll, asi, 8);
+        u.l.upper = *(uint32_t *)&env->fpr[rd++];
+        u.l.lower = *(uint32_t *)&env->fpr[rd++];
+        helper_st_asi(addr + 8, u.ll, asi, 8);
         break;
     }
-    helper_st_asi(addr, val, asi, size);
 }
 
 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index d07eb25..95e78a3 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -4739,12 +4739,10 @@ static void disas_sparc_insn(DisasContext * dc)
                         r_const = tcg_const_i32(7);
                         gen_helper_check_align(cpu_addr, r_const);
                         tcg_temp_free_i32(r_const);
-                        gen_op_load_fpr_QT0(QFPREG(rd));
                         gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
                     }
                     break;
                 case 0x37: /* V9 stdfa */
-                    gen_op_load_fpr_DT0(DFPREG(rd));
                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
                     break;
                 case 0x3c: /* V9 casa */
-- 
1.7.5.4

[Qemu-devel] [PATCH 4/4] SPARC64: fp_disabled checks on stfa/stdfa/stqfa

[Tsuneo Saito]

stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/translate.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 95e78a3..94c1000 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -4729,6 +4729,8 @@ static void disas_sparc_insn(DisasContext * dc)
                 switch (xop) {
 #ifdef TARGET_SPARC64
                 case 0x34: /* V9 stfa */
+                    if (gen_trap_ifnofpu(dc, cpu_cond))
+                        goto jmp_insn;
                     gen_stf_asi(cpu_addr, insn, 4, rd);
                     break;
                 case 0x36: /* V9 stqfa */
@@ -4736,6 +4738,8 @@ static void disas_sparc_insn(DisasContext * dc)
                         TCGv_i32 r_const;
 
                         CHECK_FPU_FEATURE(dc, FLOAT128);
+                        if (gen_trap_ifnofpu(dc, cpu_cond))
+                            goto jmp_insn;
                         r_const = tcg_const_i32(7);
                         gen_helper_check_align(cpu_addr, r_const);
                         tcg_temp_free_i32(r_const);
@@ -4743,6 +4747,8 @@ static void disas_sparc_insn(DisasContext * dc)
                     }
                     break;
                 case 0x37: /* V9 stdfa */
+                    if (gen_trap_ifnofpu(dc, cpu_cond))
+                        goto jmp_insn;
                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
                     break;
                 case 0x3c: /* V9 casa */
-- 
1.7.5.4

Re: [Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[Artyom Tarasenko]

Hi,

On Wed, Jul 13, 2011 at 5:30 AM, Tsuneo Saito <tsnsaito@gmail.com> wrote:
> Hi,
>
> This patch series implements sparcv9 stfa/ldfa instructions with
> non block-transfer ASIs that implementations seem to be left unfinished.
> This patch also adds fp_disabled exception checks on stfa/ldfa
> as they are FP instructions.

Nice series!
May I ask what have you used as a test case to discover the problem?
Please use the scripts/checkpatch.pl script to check coding style,
there are some braces missing in 2/4 and 4/4 patches.
The contents
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>

>  target-sparc/op_helper.c |   31 ++++++++++++++++++++++---------
>  target-sparc/translate.c |   14 ++++++++++++--
>  2 files changed, 34 insertions(+), 11 deletions(-)
>
>


-- 
Regards,
Artyom Tarasenko

solaris/sparc under qemu blog: http://tyom.blogspot.com/

Re: [Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[tsnsaito]

Hi,

At Wed, 13 Jul 2011 10:57:19 +0200,
Artyom Tarasenko wrote:

> On Wed, Jul 13, 2011 at 5:30 AM, Tsuneo Saito <tsnsaito@gmail.com> wrote:
> > Hi,
> >
> > This patch series implements sparcv9 stfa/ldfa instructions with
> > non block-transfer ASIs that implementations seem to be left unfinished.
> > This patch also adds fp_disabled exception checks on stfa/ldfa
> > as they are FP instructions.
> 
> Nice series!
> May I ask what have you used as a test case to discover the problem?

I found the problem when I was trying to run the linux/sparc64 kernel.
It seemed that copy_to_user() did not work as expected.

> Please use the scripts/checkpatch.pl script to check coding style,
> there are some braces missing in 2/4 and 4/4 patches.
> The contents
> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>

Thanks for the review!
I'll fix the coding style problems and post the fixed version. 

----
Tsuneo Saito <tsnsaito@gmail.com>

Re: [Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[Mark Cave-Ayland]

On 13/07/11 12:06, tsnsaito@gmail.com wrote:

>> Nice series!
>> May I ask what have you used as a test case to discover the problem?
>
> I found the problem when I was trying to run the linux/sparc64 kernel.
> It seemed that copy_to_user() did not work as expected.

That's good to hear. How far have you managed to get a 64-bit Linux 
kernel to boot to date?


ATB,

Mark.

-- 
Mark Cave-Ayland - Senior Technical Architect
PostgreSQL - PostGIS
Sirius Corporation plc - control through freedom
http://www.siriusit.co.uk
t: +44 870 608 0063

Sirius Labs: http://www.siriusit.co.uk/labs

Re: [Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[tsnsaito]

Hi,

At Wed, 13 Jul 2011 13:09:28 +0100,
Mark Cave-Ayland wrote:
> >> Nice series!
> >> May I ask what have you used as a test case to discover the problem?
> >
> > I found the problem when I was trying to run the linux/sparc64 kernel.
> > It seemed that copy_to_user() did not work as expected.
> 
> That's good to hear. How far have you managed to get a 64-bit Linux 
> kernel to boot to date?

With dirty hacks other than the ldfa/stfa fixes, I have managed
to get the busybox shell prompt using a kernel with initramfs.
I'm planning to send other fixes after cleaning them up.

----
Tsuneo Saito <tsnsaito@gmail.com>

Re: [Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[Blue Swirl]

On Wed, Jul 13, 2011 at 3:48 PM,  <tsnsaito@gmail.com> wrote:
> Hi,
>
> At Wed, 13 Jul 2011 13:09:28 +0100,
> Mark Cave-Ayland wrote:
>> >> Nice series!
>> >> May I ask what have you used as a test case to discover the problem?
>> >
>> > I found the problem when I was trying to run the linux/sparc64 kernel.
>> > It seemed that copy_to_user() did not work as expected.
>>
>> That's good to hear. How far have you managed to get a 64-bit Linux
>> kernel to boot to date?
>
> With dirty hacks other than the ldfa/stfa fixes, I have managed
> to get the busybox shell prompt using a kernel with initramfs.
> I'm planning to send other fixes after cleaning them up.

Great! In which areas are the hacks needed?

Re: [Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[tsnsaito]

Hi,

At Wed, 13 Jul 2011 19:34:10 +0300,
Blue Swirl wrote:
> On Wed, Jul 13, 2011 at 3:48 PM,  <tsnsaito@gmail.com> wrote:
> > At Wed, 13 Jul 2011 13:09:28 +0100,
> > Mark Cave-Ayland wrote:
> >> >> Nice series!
> >> >> May I ask what have you used as a test case to discover the problem?
> >> >
> >> > I found the problem when I was trying to run the linux/sparc64 kernel.
> >> > It seemed that copy_to_user() did not work as expected.
> >>
> >> That's good to hear. How far have you managed to get a 64-bit Linux
> >> kernel to boot to date?
> >
> > With dirty hacks other than the ldfa/stfa fixes, I have managed
> > to get the busybox shell prompt using a kernel with initramfs.
> > I'm planning to send other fixes after cleaning them up.
> 
> Great! In which areas are the hacks needed?

Roughly speaking I've added/changed the following so far:
- %fprs register dirty bits support
- hardware interrupt handing (both interrupt controller and cpu side)
  also needed to modify the openbios.
- nonfaulting load ASI
  glibc memcpy seems to use nonfaulting loads

---- 
Tsuneo Saito <tsnsaito@gmail.com>

Re: [Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[Artyom Tarasenko]

On Thu, Jul 14, 2011 at 5:13 AM,  <tsnsaito@gmail.com> wrote:
> Hi,
>
> At Wed, 13 Jul 2011 19:34:10 +0300,
> Blue Swirl wrote:
>> On Wed, Jul 13, 2011 at 3:48 PM,  <tsnsaito@gmail.com> wrote:
>> > At Wed, 13 Jul 2011 13:09:28 +0100,
>> > Mark Cave-Ayland wrote:
>> >> >> Nice series!
>> >> >> May I ask what have you used as a test case to discover the problem?
>> >> >
>> >> > I found the problem when I was trying to run the linux/sparc64 kernel.
>> >> > It seemed that copy_to_user() did not work as expected.
>> >>
>> >> That's good to hear. How far have you managed to get a 64-bit Linux
>> >> kernel to boot to date?
>> >
>> > With dirty hacks other than the ldfa/stfa fixes, I have managed
>> > to get the busybox shell prompt using a kernel with initramfs.
>> > I'm planning to send other fixes after cleaning them up.
>>
>> Great! In which areas are the hacks needed?
>
> Roughly speaking I've added/changed the following so far:
> - %fprs register dirty bits support

O, that's interesting. Does glibc use it?

> - hardware interrupt handing (both interrupt controller and cpu side)
>  also needed to modify the openbios.

Nice. A lot of work indeed.

> - nonfaulting load ASI
>  glibc memcpy seems to use nonfaulting loads

You mean other than the implemented 0x82/83 and 0x8a/8b ones, or that
the current implementation is buggy?


-- 
Regards,
Artyom Tarasenko

solaris/sparc under qemu blog: http://tyom.blogspot.com/

Re: [Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[tsnsaito]

At Thu, 14 Jul 2011 09:38:18 +0200,
Artyom Tarasenko wrote:
> On Thu, Jul 14, 2011 at 5:13 AM,  <tsnsaito@gmail.com> wrote:
> > At Wed, 13 Jul 2011 19:34:10 +0300,
> > Blue Swirl wrote:
> >> On Wed, Jul 13, 2011 at 3:48 PM,  <tsnsaito@gmail.com> wrote:
> >> > At Wed, 13 Jul 2011 13:09:28 +0100,
> >> > Mark Cave-Ayland wrote:
> >> >> >> Nice series!
> >> >> >> May I ask what have you used as a test case to discover the problem?
> >> >> >
> >> >> > I found the problem when I was trying to run the linux/sparc64 kernel.
> >> >> > It seemed that copy_to_user() did not work as expected.
> >> >>
> >> >> That's good to hear. How far have you managed to get a 64-bit Linux
> >> >> kernel to boot to date?
> >> >
> >> > With dirty hacks other than the ldfa/stfa fixes, I have managed
> >> > to get the busybox shell prompt using a kernel with initramfs.
> >> > I'm planning to send other fixes after cleaning them up.
> >>
> >> Great! In which areas are the hacks needed?
> >
> > Roughly speaking I've added/changed the following so far:
> > - %fprs register dirty bits support
> 
> O, that's interesting. Does glibc use it?

The linux kernel saves FPU registers context based on %fprs dirty bits.
We need to implement these bits in order to make context switches
work properly.

> > - hardware interrupt handing (both interrupt controller and cpu side)
> >  also needed to modify the openbios.
> 
> Nice. A lot of work indeed.
> 
> > - nonfaulting load ASI
> >  glibc memcpy seems to use nonfaulting loads
> 
> You mean other than the implemented 0x82/83 and 0x8a/8b ones, or that
> the current implementation is buggy?

The softmmu version of current implementation is incorrect.
Nonfaulting loads should generate exceptions in the same way as
normal loads.  The CPU hardware should not return zero automatically
if no memory mapping exists.  The system software is responsible for
nonfaulting loads to read zero if no mapping is availale.

The differences between nonfaulting loads and normal loads are:
- that DSFSR.NF bit is set for nonfaulting loads on MMU faults.
- the result of loads on memory region mapped by TTEs with NFO bit set.

---- 
Tsuneo Saito <tsnsaito@gmail.com>

Re: [Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[Blue Swirl]

On Thu, Jul 14, 2011 at 12:13 PM,  <tsnsaito@gmail.com> wrote:
> At Thu, 14 Jul 2011 09:38:18 +0200,
> Artyom Tarasenko wrote:
>> On Thu, Jul 14, 2011 at 5:13 AM,  <tsnsaito@gmail.com> wrote:
>> > At Wed, 13 Jul 2011 19:34:10 +0300,
>> > Blue Swirl wrote:
>> >> On Wed, Jul 13, 2011 at 3:48 PM,  <tsnsaito@gmail.com> wrote:
>> >> > At Wed, 13 Jul 2011 13:09:28 +0100,
>> >> > Mark Cave-Ayland wrote:
>> >> >> >> Nice series!
>> >> >> >> May I ask what have you used as a test case to discover the problem?
>> >> >> >
>> >> >> > I found the problem when I was trying to run the linux/sparc64 kernel.
>> >> >> > It seemed that copy_to_user() did not work as expected.
>> >> >>
>> >> >> That's good to hear. How far have you managed to get a 64-bit Linux
>> >> >> kernel to boot to date?
>> >> >
>> >> > With dirty hacks other than the ldfa/stfa fixes, I have managed
>> >> > to get the busybox shell prompt using a kernel with initramfs.
>> >> > I'm planning to send other fixes after cleaning them up.
>> >>
>> >> Great! In which areas are the hacks needed?
>> >
>> > Roughly speaking I've added/changed the following so far:
>> > - %fprs register dirty bits support
>>
>> O, that's interesting. Does glibc use it?
>
> The linux kernel saves FPU registers context based on %fprs dirty bits.
> We need to implement these bits in order to make context switches
> work properly.

This could be implemented so that each instruction that writes to FPU
registers updates the dirty bits. A more advanced version could try to
do this more lazily (end of basic block or after any exception
generating instruction) but that may be tricky.

>> > - hardware interrupt handing (both interrupt controller and cpu side)
>> >  also needed to modify the openbios.
>>
>> Nice. A lot of work indeed.
>>
>> > - nonfaulting load ASI
>> >  glibc memcpy seems to use nonfaulting loads
>>
>> You mean other than the implemented 0x82/83 and 0x8a/8b ones, or that
>> the current implementation is buggy?
>
> The softmmu version of current implementation is incorrect.
> Nonfaulting loads should generate exceptions in the same way as
> normal loads.  The CPU hardware should not return zero automatically
> if no memory mapping exists.  The system software is responsible for
> nonfaulting loads to read zero if no mapping is availale.
>
> The differences between nonfaulting loads and normal loads are:
> - that DSFSR.NF bit is set for nonfaulting loads on MMU faults.
> - the result of loads on memory region mapped by TTEs with NFO bit set.

I hope this is documented somewhere.

Re: [Qemu-devel] [PATCH 0/4] SPARC64: Implement sparcv9 ldfa/stfa instructions

[tsnsaito]

At Thu, 14 Jul 2011 18:31:52 +0300,
Blue Swirl wrote:
> On Thu, Jul 14, 2011 at 12:13 PM,  <tsnsaito@gmail.com> wrote:
> > The softmmu version of current implementation is incorrect.
> > Nonfaulting loads should generate exceptions in the same way as
> > normal loads.  The CPU hardware should not return zero automatically
> > if no memory mapping exists.  The system software is responsible for
> > nonfaulting loads to read zero if no mapping is availale.
> >
> > The differences between nonfaulting loads and normal loads are:
> > - that DSFSR.NF bit is set for nonfaulting loads on MMU faults.
> > - the result of loads on memory region mapped by TTEs with NFO bit set.
> 
> I hope this is documented somewhere.

In the UA2007 spec it is partly documented in "9.6 Nonfaulting Load",
but I couldn't find out the description of the SFSR (Synchronous Fault
Status Register) in UA2007...
In the JPS1 spec, the SFSR register is described in F.10.9.

---- 
Tsuneo Saito <tsnsaito@gmail.com>