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([2a01:e0a:fa3:e4b0:95dc:ab11:92db:6f9e]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-6443f5aeac5sm778613d50.17.2025.12.04.08.28.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Dec 2025 08:28:29 -0800 (PST) Message-ID: <4e211bdd-b23a-4141-a341-3ee2429e0dee@redhat.com> Date: Thu, 4 Dec 2025 17:28:23 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 13/33] hw/arm/smmuv3: propagate smmuv3_cmdq_consume() errors to caller Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, yi.l.liu@intel.com, kjaju@nvidia.com References: <20251120132213.56581-1-skolothumtho@nvidia.com> <20251120132213.56581-14-skolothumtho@nvidia.com> From: Eric Auger In-Reply-To: <20251120132213.56581-14-skolothumtho@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/20/25 2:21 PM, Shameer Kolothum wrote: > smmuv3_cmdq_consume() is updated to return detailed errors via errp. > > Although this is currently a no-op, it prepares the ground for accel > SMMUv3 specific command handling where proper error reporting will be > useful. > > Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Eric > --- > hw/arm/smmuv3.c | 67 +++++++++++++++++++++++++++---------------------- > 1 file changed, 37 insertions(+), 30 deletions(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index ef991cb7d8..374ae08baa 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -1279,7 +1279,7 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage) > } > } > > -static int smmuv3_cmdq_consume(SMMUv3State *s) > +static int smmuv3_cmdq_consume(SMMUv3State *s, Error **errp) > { > SMMUState *bs = ARM_SMMU(s); > SMMUCmdError cmd_error = SMMU_CERROR_NONE; > @@ -1547,42 +1547,44 @@ static MemTxResult smmu_writell(SMMUv3State *s, hwaddr offset, > static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, > uint64_t data, MemTxAttrs attrs) > { > + Error *local_err = NULL; > + > switch (offset) { > case A_CR0: > s->cr[0] = data; > s->cr0ack = data & ~SMMU_CR0_RESERVED; > /* in case the command queue has been enabled */ > - smmuv3_cmdq_consume(s); > - return MEMTX_OK; > + smmuv3_cmdq_consume(s, &local_err); > + break; > case A_CR1: > s->cr[1] = data; > - return MEMTX_OK; > + break; > case A_CR2: > s->cr[2] = data; > - return MEMTX_OK; > + break; > case A_IRQ_CTRL: > s->irq_ctrl = data; > - return MEMTX_OK; > + break; > case A_GERRORN: > smmuv3_write_gerrorn(s, data); > /* > * By acknowledging the CMDQ_ERR, SW may notify cmds can > * be processed again > */ > - smmuv3_cmdq_consume(s); > - return MEMTX_OK; > + smmuv3_cmdq_consume(s, &local_err); > + break; > case A_GERROR_IRQ_CFG0: /* 64b */ > s->gerror_irq_cfg0 = deposit64(s->gerror_irq_cfg0, 0, 32, data); > - return MEMTX_OK; > + break; > case A_GERROR_IRQ_CFG0 + 4: > s->gerror_irq_cfg0 = deposit64(s->gerror_irq_cfg0, 32, 32, data); > - return MEMTX_OK; > + break; > case A_GERROR_IRQ_CFG1: > s->gerror_irq_cfg1 = data; > - return MEMTX_OK; > + break; > case A_GERROR_IRQ_CFG2: > s->gerror_irq_cfg2 = data; > - return MEMTX_OK; > + break; > case A_GBPA: > /* > * If UPDATE is not set, the write is ignored. This is the only > @@ -1592,71 +1594,76 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, > /* Ignore update bit as write is synchronous. */ > s->gbpa = data & ~R_GBPA_UPDATE_MASK; > } > - return MEMTX_OK; > + break; > case A_STRTAB_BASE: /* 64b */ > s->strtab_base = deposit64(s->strtab_base, 0, 32, data); > - return MEMTX_OK; > + break; > case A_STRTAB_BASE + 4: > s->strtab_base = deposit64(s->strtab_base, 32, 32, data); > - return MEMTX_OK; > + break; > case A_STRTAB_BASE_CFG: > s->strtab_base_cfg = data; > if (FIELD_EX32(data, STRTAB_BASE_CFG, FMT) == 1) { > s->sid_split = FIELD_EX32(data, STRTAB_BASE_CFG, SPLIT); > s->features |= SMMU_FEATURE_2LVL_STE; > } > - return MEMTX_OK; > + break; > case A_CMDQ_BASE: /* 64b */ > s->cmdq.base = deposit64(s->cmdq.base, 0, 32, data); > s->cmdq.log2size = extract64(s->cmdq.base, 0, 5); > if (s->cmdq.log2size > SMMU_CMDQS) { > s->cmdq.log2size = SMMU_CMDQS; > } > - return MEMTX_OK; > + break; > case A_CMDQ_BASE + 4: /* 64b */ > s->cmdq.base = deposit64(s->cmdq.base, 32, 32, data); > - return MEMTX_OK; > + break; > case A_CMDQ_PROD: > s->cmdq.prod = data; > - smmuv3_cmdq_consume(s); > - return MEMTX_OK; > + smmuv3_cmdq_consume(s, &local_err); > + break; > case A_CMDQ_CONS: > s->cmdq.cons = data; > - return MEMTX_OK; > + break; > case A_EVENTQ_BASE: /* 64b */ > s->eventq.base = deposit64(s->eventq.base, 0, 32, data); > s->eventq.log2size = extract64(s->eventq.base, 0, 5); > if (s->eventq.log2size > SMMU_EVENTQS) { > s->eventq.log2size = SMMU_EVENTQS; > } > - return MEMTX_OK; > + break; > case A_EVENTQ_BASE + 4: > s->eventq.base = deposit64(s->eventq.base, 32, 32, data); > - return MEMTX_OK; > + break; > case A_EVENTQ_PROD: > s->eventq.prod = data; > - return MEMTX_OK; > + break; > case A_EVENTQ_CONS: > s->eventq.cons = data; > - return MEMTX_OK; > + break; > case A_EVENTQ_IRQ_CFG0: /* 64b */ > s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data); > - return MEMTX_OK; > + break; > case A_EVENTQ_IRQ_CFG0 + 4: > s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data); > - return MEMTX_OK; > + break; > case A_EVENTQ_IRQ_CFG1: > s->eventq_irq_cfg1 = data; > - return MEMTX_OK; > + break; > case A_EVENTQ_IRQ_CFG2: > s->eventq_irq_cfg2 = data; > - return MEMTX_OK; > + break; > default: > qemu_log_mask(LOG_UNIMP, > "%s Unexpected 32-bit access to 0x%"PRIx64" (WI)\n", > __func__, offset); > - return MEMTX_OK; > + break; > } > + > + if (local_err) { > + error_report_err(local_err); > + } > + return MEMTX_OK; > } > > static MemTxResult smmu_write_mmio(void *opaque, hwaddr offset, uint64_t data,