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From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair23@gmail.com>, Michael Clark <mjc@sifive.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Peter Maydell <peter.maydell@linaro.org>,
	suhang16@mails.ucas.ac.cn, msuozzo@google.com,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	palmer@sifive.com, "Emilio G. Cota" <cota@braap.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	patches@groups.riscv.org
Subject: Re: [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates
Date: Thu, 26 Apr 2018 14:35:02 -1000	[thread overview]
Message-ID: <4e30b71b-7007-d879-d1c4-12eeb94ed6c5@linaro.org> (raw)
In-Reply-To: <CAKmqyKMtO5JQ7GnpKU9E_MGeDRGHsb=c0ra0CnGX8vxKtKsunQ@mail.gmail.com>

On 04/26/2018 08:22 AM, Alistair Francis wrote:
> On Wed, Apr 25, 2018 at 7:01 PM Michael Clark <mjc@sifive.com> wrote:
>> We can make a PR for the first 9 patches as they are already reviewed,
>> however, the with this series is to gather review for the new baseline we
>> have in the riscv repo.
> 
> I think it is worth sending a PR for the first 9 patches. The current
> master doesn't boot the sifive_u board and those patches will fix that.
> That also helps create a smaller patch series which is easier to review.

FYI, for patches that affect usability like this, you should also Cc:
qemu-stable@nongnu.org in your pull request.  That way they should be
cherry-picked from master into the 2.12.1 release.


r~

  parent reply	other threads:[~2018-04-27  0:35 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-25 23:45 [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 01/35] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-04-26 16:37   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 02/35] RISC-V: Make virt board description match spike Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 03/35] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 04/35] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 05/35] RISC-V: Remove unused class definitions Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 06/35] RISC-V: Include instruction hex in disassembly Michael Clark
2018-04-26 17:05   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 07/35] RISC-V: Make some header guards more specific Michael Clark
2018-04-26 16:43   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 08/35] RISC-V: Make virt header comment title consistent Michael Clark
2018-04-26 16:42   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 09/35] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-04-26 16:42   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 10/35] RISC-V: Remove erroneous comment from translate.c Michael Clark
2018-04-25 23:51   ` [Qemu-devel] [patches] " Palmer Dabbelt
2018-04-26 16:48   ` [Qemu-devel] " Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 11/35] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-04-26 16:48   ` Alistair Francis
2018-04-27  5:22     ` Michael Clark
2018-04-27  5:34       ` Michael Clark
2018-04-27 16:17         ` Alistair Francis
2018-05-04  1:45           ` Michael Clark
2018-05-04 23:44             ` Alistair Francis
2018-05-04 23:54               ` Alistair Francis
2018-05-05  2:02                 ` Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 12/35] RISC-V: Update address bits to support sv39 and sv48 Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 13/35] RISC-V: Improve page table walker spec compliance Michael Clark
2018-05-03 20:49   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 14/35] RISC-V: Update E order and I extension order Michael Clark
2018-04-26 17:11   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-04-26 17:21   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps Michael Clark
2018-04-26 17:27   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 17/35] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-04-26 17:36   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 Michael Clark
2018-04-26 20:02   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs " Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -icount auto Michael Clark
2018-04-26 20:05   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps Michael Clark
2018-04-27  0:14   ` Richard Henderson
2018-04-27  7:18     ` Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending Michael Clark
2018-04-27 22:33   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 24/35] RISC-V: Allow setting and clearing multiple irqs Michael Clark
2018-05-03 20:54   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu_helper Michael Clark
2018-04-26 17:42   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 26/35] RISC-V: Update CSR and interrupt definitions Michael Clark
2018-05-03 20:56   ` Alistair Francis
2018-05-04  4:21     ` Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 27/35] RISC-V: Implement modular CSR helper interface Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 28/35] RISC-V: Implement atomic mip/sip CSR updates Michael Clark
2018-05-03 21:11   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 29/35] RISC-V: Implement existential predicates for CSRs Michael Clark
2018-05-03 21:21   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 30/35] RISC-V: Split out mstatus_fs from tb_flags Michael Clark
2018-05-03 21:22   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 31/35] RISC-V: Mark mstatus.fs dirty Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 32/35] RISC-V: Implement mstatus.TSR/TW/TVM Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 33/35] RISC-V: Add public API for the CSR dispatch table Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 34/35] RISC-V: Add hartid and \n to interrupt logging Michael Clark
2018-05-03 21:25   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 35/35] RISC-V: Use riscv prefix consistently on cpu helpers Michael Clark
2018-04-26  1:42 ` [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates Michael Clark
2018-04-26  2:01   ` Michael Clark
2018-04-26 18:22     ` Alistair Francis
2018-04-27  0:34       ` Michael Clark
2018-04-27 10:19         ` Peter Maydell
2018-04-27  0:35       ` Richard Henderson [this message]
2018-04-27  5:00         ` Michael Clark

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