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Mon, 30 Sep 2024 12:10:54 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6137820040; Mon, 30 Sep 2024 12:10:54 +0000 (GMT) Received: from [127.0.0.1] (unknown [9.152.108.100]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 30 Sep 2024 12:10:54 +0000 (GMT) Message-ID: <4e3ab59f55937b846fc214f3c3ca3e15c4afb19c.camel@linux.ibm.com> Subject: Re: [PULL v2 00/47] riscv-to-apply queue From: Ilya Leoshkevich To: Daniel Henrique Barboza , Peter Maydell , Alistair Francis Cc: qemu-devel@nongnu.org, Alistair Francis Date: Mon, 30 Sep 2024 14:10:54 +0200 In-Reply-To: <13ee9889-b503-45ea-a074-ffafbd052c4e@ventanamicro.com> References: <20240924221751.2688389-1-alistair.francis@wdc.com> <13ee9889-b503-45ea-a074-ffafbd052c4e@ventanamicro.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.52.4 (3.52.4-1.fc40) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: lUl7SSnp0_Ux9t2Nzkk0Ro8I6SkKAs8c X-Proofpoint-ORIG-GUID: IIPjVXv6sSC3K4J7SF5u1y7yRVTlW4bE Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-09-30_10,2024-09-27_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 clxscore=1011 phishscore=0 spamscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409300087 Received-SPF: pass client-ip=148.163.158.5; envelope-from=iii@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URI_DOTEDU=1.999 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sat, 2024-09-28 at 17:40 -0300, Daniel Henrique Barboza wrote: >=20 >=20 > On 9/28/24 8:34 AM, Peter Maydell wrote: > > On Tue, 24 Sept 2024 at 23:18, Alistair Francis > > wrote: > > >=20 > > > The following changes since commit > > > 01dc65a3bc262ab1bec8fe89775e9bbfa627becb: > > >=20 > > > =C2=A0=C2=A0 Merge tag 'pull-target-arm-20240919' of > > > https://git.linaro.org/people/pmaydell/qemu-arm=C2=A0into staging > > > (2024-09-19 14:15:15 +0100) > > >=20 > > > are available in the Git repository at: > > >=20 > > > =C2=A0=C2=A0 https://github.com/alistair23/qemu.git=C2=A0tags/pull-ri= scv-to- > > > apply-20240925-1 > > >=20 > > > for you to fetch changes up to > > > 6bfa92c5757fe7a9580e1f6e065076777cae650f: > > >=20 > > > =C2=A0=C2=A0 bsd-user: Add RISC-V 64-bit Target Configuration and Deb= ug XML > > > Files (2024-09-24 12:53:16 +1000) > > >=20 > > > ---------------------------------------------------------------- > > > RISC-V PR for 9.2 > > >=20 > > > * Add a property to set vl to ceil(AVL/2) > > > * Enable numamem testing for RISC-V > > > * Consider MISA bit choice in implied rule > > > * Fix the za64rs priv spec requirements > > > * Enable Bit Manip for OpenTitan Ibex CPU > > > * Fix the group bit setting of AIA with KVM > > > * Stop timer with infinite timecmp > > > * Add 'fcsr' register to QEMU log as a part of F extension > > > * Fix riscv64 build on musl libc > > > * Add preliminary textra trigger CSR functions > > > * RISC-V IOMMU support > > > * RISC-V bsd-user support > > > * Respect firmware ELF entry point > > > * Add Svvptc extension support > > > * Fix masking of rv32 physical address > > > * Fix linking problem with semihosting disabled > > > * Fix IMSIC interrupt state updates > > >=20 > >=20 > > This fails the riscv qos-tests on s390x. My guess is that the new > > IOMMU support has endianness bugs and fails on bigendian hosts. > >=20 > > https://gitlab.com/qemu-project/qemu/-/jobs/7942189143 > >=20 > > full test log (4MB) at > > https://qemu-project.gitlab.io/-/qemu/-/jobs/7942189143/artifacts/build= /meson-logs/testlog.txt > >=20 > > The assertion failure is > > ERROR:../tests/qtest/riscv-iommu-test.c:72:test_reg_reset: > > assertion > > failed (cap & RISCV_IOMMU_CAP_VERSION =3D=3D 0x10): (0 =3D=3D 16) >=20 > The root cause is that the qtests I added aren't considering the > endianess of the > host. The RISC-V IOMMU is being implemented as LE only and all regs > are being > read/written in memory as LE. The qtest read/write helpers must take > the qtest > endianess into account. We make this type of handling in other qtest > archs like > ppc64. >=20 > I have a fix for the tests but I'm unable to run the ubuntu-22.04- > s390x-all-system > job to verify it, even after setting Cirrus like Thomas taught me a > week ago. In > fact I have no 'ubuntu-22-*' jobs available to run. >=20 > If there's a way to run these ubuntu s390x tests, let me know. > Otherwise I'm inclined > to remove the IOMMU qtests for now until I'm able to verify that > they'll work in a > BE host (I'll install a BE VM to verify). You can get a free s390x VM here: https://linuxone.cloud.marist.edu/#/register?flag=3DVM Best regards, Ilya [...]