From: Richard Henderson <richard.henderson@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>,
"Emilio G. Cota" <cota@braap.org>,
qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v3 4/4] cputlb: read CPUTLBEntry.addr_write atomically
Date: Tue, 16 Oct 2018 08:56:45 -0700 [thread overview]
Message-ID: <4e8d6cb0-2fb0-df55-afed-d71c76b1e526@linaro.org> (raw)
In-Reply-To: <6ae5b4c7-3300-2059-b648-855d7ea00488@redhat.com>
On 10/15/18 11:03 PM, Paolo Bonzini wrote:
> On 16/10/2018 04:52, Richard Henderson wrote:
>> On 10/5/18 2:14 PM, Emilio G. Cota wrote:
>>> - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
>>> + target_ulong tlb_addr =
>>> + atomic_read(&env->tlb_table[mmu_idx][index].addr_write);
>>
>> This fails for 32-bit hosts emulating 64-bit hosts.
>> I think you need a separate helper function. Perhaps
>>
>> static inline target_ulong tlb_addr_write(CPUTLBEntry *ent)
>> {
>> #if TCG_OVERSIZED_GUEST
>> return ent->addr_write;
>> #else
>> return atomic_read(&ent->addr_write);
>> #endif
>> }
>>
>
> Or just atomic_read__nocheck.
No, it won't be present, necessarily.
r~
prev parent reply other threads:[~2018-10-16 15:56 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-05 21:14 [Qemu-devel] [PATCH v3 0/4] per-TLB lock Emilio G. Cota
2018-10-05 21:14 ` [Qemu-devel] [PATCH v3 1/4] exec: introduce tlb_init Emilio G. Cota
2018-10-05 21:14 ` [Qemu-devel] [PATCH v3 2/4] cputlb: fix assert_cpu_is_self macro Emilio G. Cota
2018-10-05 21:14 ` [Qemu-devel] [PATCH v3 3/4] cputlb: serialize tlb updates with env->tlb_lock Emilio G. Cota
2018-10-08 13:57 ` Alex Bennée
2018-10-08 14:12 ` Emilio G. Cota
2018-10-08 14:30 ` Alex Bennée
2018-10-05 21:14 ` [Qemu-devel] [PATCH v3 4/4] cputlb: read CPUTLBEntry.addr_write atomically Emilio G. Cota
2018-10-16 2:52 ` Richard Henderson
2018-10-16 6:03 ` Paolo Bonzini
2018-10-16 15:12 ` Emilio G. Cota
2018-10-16 15:56 ` Richard Henderson [this message]
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