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From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <4e8d6cb0-2fb0-df55-afed-d71c76b1e526@linaro.org>
Date: Tue, 16 Oct 2018 08:56:45 -0700
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Subject: Re: [Qemu-devel] [PATCH v3 4/4] cputlb: read CPUTLBEntry.addr_write
 atomically
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To: Paolo Bonzini <pbonzini@redhat.com>, "Emilio G. Cota" <cota@braap.org>, qemu-devel@nongnu.org
Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= <alex.bennee@linaro.org>

On 10/15/18 11:03 PM, Paolo Bonzini wrote:
> On 16/10/2018 04:52, Richard Henderson wrote:
>> On 10/5/18 2:14 PM, Emilio G. Cota wrote:
>>> -    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
>>> +    target_ulong tlb_addr =
>>> +        atomic_read(&env->tlb_table[mmu_idx][index].addr_write);
>>
>> This fails for 32-bit hosts emulating 64-bit hosts.
>> I think you need a separate helper function.  Perhaps
>>
>> static inline target_ulong tlb_addr_write(CPUTLBEntry *ent)
>> {
>> #if TCG_OVERSIZED_GUEST
>>     return ent->addr_write;
>> #else
>>     return atomic_read(&ent->addr_write);
>> #endif
>> }
>>
> 
> Or just atomic_read__nocheck.

No, it won't be present, necessarily.


r~