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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a892e52c8esm10832082f8f.55.2025.06.30.08.35.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Jun 2025 08:35:43 -0700 (PDT) Message-ID: <4edfdda0-a627-48f3-a2fa-94d7545eff2c@linaro.org> Date: Mon, 30 Jun 2025 17:35:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/6] target/arm: Allow arm_cpu_tlb_fill_align optionally set CPUTLBEntryFull To: Richard Henderson , qemu-devel@nongnu.org References: <20250630130937.3487-1-philmd@linaro.org> <20250630130937.3487-7-philmd@linaro.org> <8141d048-42e5-4b79-a90d-0ef1857d5857@linaro.org> Content-Language: en-US Cc: qemu-arm From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <8141d048-42e5-4b79-a90d-0ef1857d5857@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 30/6/25 15:56, Richard Henderson wrote: > On 6/30/25 07:09, Philippe Mathieu-Daudé wrote: >> Signed-off-by: Philippe Mathieu-Daudé >> --- >>   target/arm/tcg/tlb_helper.c | 4 +++- >>   1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c >> index 23c72a99f5c..df04ef351d1 100644 >> --- a/target/arm/tcg/tlb_helper.c >> +++ b/target/arm/tcg/tlb_helper.c >> @@ -349,7 +349,9 @@ bool arm_cpu_tlb_fill_align(CPUState *cs, >> CPUTLBEntryFull *out, vaddr address, >>                                 &res, fi)) { >>           res.f.extra.arm.pte_attrs = res.cacheattrs.attrs; >>           res.f.extra.arm.shareability = res.cacheattrs.shareability; >> -        *out = res.f; >> +        if (out) { >> +            *out = res.f; >> +        } >>           return true; >>       } >>       if (probe) { > > Why?  There's no other way to get the phys addr result. > Are you only calling this for the raise-exception side effect? Yes: -- >8 -- @@ -2121,6 +2121,25 @@ int hvf_vcpu_exec(CPUState *cpu) hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized(), 1); } break; + case EC_INSNABORT: { + uint32_t set = (syndrome >> 12) & 3; + bool fnv = (syndrome >> 10) & 1; + bool ea = (syndrome >> 9) & 1; + bool s1ptw = (syndrome >> 7) & 1; + uint32_t ifsc = (syndrome >> 0) & 0x3f; + + trace_hvf_insn_abort(env->pc, set, fnv, ea, s1ptw, ifsc); + + cpu_synchronize_state(cpu); + if (tcg_enabled()) { + ret = EXCP_EMULATE; + arm_cpu_tlb_fill_align(cpu, NULL, env->pc, MMU_INST_FETCH, + arm_env_mmu_index(env), MO_32, 4, false, -1); + } + break; + } default: cpu_synchronize_state(cpu); trace_hvf_exit(syndrome, ec, env->pc); --- I see probe_access_full_mmu() uses discard_tlb, I can use a similar stack variable if you rather.