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[88.28.28.52]) by smtp.gmail.com with ESMTPSA id j40-20020a05600c1c2800b003dd1bd0b915sm19647059wms.22.2023.03.07.14.32.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Mar 2023 14:32:51 -0800 (PST) Message-ID: <4ef9dedc-ce1c-b0f1-281f-e0c49b4e04d7@linaro.org> Date: Tue, 7 Mar 2023 23:32:47 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v4 1/9] hw/pci-host/i440fx: Inline sysbus_add_io() Content-Language: en-US To: Bernhard Beschow , qemu-devel@nongnu.org Cc: Paolo Bonzini , Sunil Muthuswamy , "Michael S. Tsirkin" , Marcel Apfelbaum , "Dr . David Alan Gilbert" , qemu-trivial@nongnu.org, Richard Henderson , Juan Quintela , Eduardo Habkost , Thomas Huth , Igor Mammedov , BALATON Zoltan , Ani Sinha , Laurent Vivier References: <20230213162004.2797-1-shentey@gmail.com> <20230213162004.2797-2-shentey@gmail.com> <3ABCEE15-F73D-498F-8D95-F17B78795E14@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/3/23 07:57, Bernhard Beschow wrote: > > > Am 22. Februar 2023 18:05:51 UTC schrieb Bernhard Beschow : >> >> >> Am 22. Februar 2023 10:58:08 UTC schrieb "Philippe Mathieu-Daudé" : >>> On 13/2/23 17:19, Bernhard Beschow wrote: >>>> sysbus_add_io() just wraps memory_region_add_subregion() while also >>>> obscuring where the memory is attached. So use >>>> memory_region_add_subregion() directly and attach it to the existing >>>> memory region s->bus->address_space_io which is set as an alias to >>>> get_system_io() by the pc machine. >>>> >>>> Signed-off-by: Bernhard Beschow >>>> Reviewed-by: Thomas Huth >>>> --- >>>> hw/pci-host/i440fx.c | 5 +++-- >>>> 1 file changed, 3 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c >>>> index 262f82c303..9c6882d3fc 100644 >>>> --- a/hw/pci-host/i440fx.c >>>> +++ b/hw/pci-host/i440fx.c >>>> @@ -27,6 +27,7 @@ >>>> #include "qemu/range.h" >>>> #include "hw/i386/pc.h" >>>> #include "hw/pci/pci.h" >>>> +#include "hw/pci/pci_bus.h" >>>> #include "hw/pci/pci_host.h" >>>> #include "hw/pci-host/i440fx.h" >>>> #include "hw/qdev-properties.h" >>>> @@ -217,10 +218,10 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) >>>> PCIHostState *s = PCI_HOST_BRIDGE(dev); >>>> SysBusDevice *sbd = SYS_BUS_DEVICE(dev); >>>> - sysbus_add_io(sbd, 0xcf8, &s->conf_mem); >>>> + memory_region_add_subregion(s->bus->address_space_io, 0xcf8, &s->conf_mem); >>> >>> To avoid accessing internal fields we should stick to the PCI API: >>> >>> memory_region_add_subregion(pci_address_space_io(PCI_DEVICE(dev)), >>> 0xcf8, &s->conf_mem); >> >> dev is of type PCIHostState which derives from SysBusDevice, not PCIDevice. AFAICS there is no getter implemented on PCIBus. You are right, there is no getter for PCIBus::address_space_io, it is accessed directly: MemoryRegion *pci_address_space_io(PCIDevice *dev) { return pci_get_bus(dev)->address_space_io; } If it is considered a property, probably no need for getter. So: Reviewed-by: Philippe Mathieu-Daudé > >> >>> >>>> sysbus_init_ioports(sbd, 0xcf8, 4); >>>> - sysbus_add_io(sbd, 0xcfc, &s->data_mem); >>>> + memory_region_add_subregion(s->bus->address_space_io, 0xcfc, &s->data_mem); >>>> sysbus_init_ioports(sbd, 0xcfc, 4); >>> >>> Now all classes implementing PCI_HOST_BRIDGE register conf/data in I/O >>> space, so this could be a pattern justifying reworking a bit the >>> PCIHostBridgeClass or adding an helper in "hw/pci/pci_host.h" to do >>> that generically. (this comment is besides the scope of this patch) >> What do you mean exactly? There are PCI hosts spawning two PCI buses and therefore have two such spaces. I haven't checked but IIRC each PCI host exposing I/O registers to access buses via ISA I/O open-code it. Even if it exposes multiple buses, the same pattern is used (1 time per bus). Anyway, no need to worry about that now...