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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c10b14cadbsm14702574eec.3.2026.03.23.06.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 06:15:54 -0700 (PDT) From: Matheus Tavares Bernardino To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng, ltaylorsimpson@gmail.com, marco.liebel@oss.qualcomm.com, philmd@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com Subject: [PATCH 03/13] target/hexagon/cpu: add HVX IEEE FP extension Date: Mon, 23 Mar 2026 06:15:39 -0700 Message-Id: <4f6bd77ba6c6c07c8796e805ce6e50539bde260e.1774271525.git.matheus.bernardino@oss.qualcomm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=fq7RpV4f c=1 sm=1 tr=0 ts=69c13d0c cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=kpEvSfgP-Ez5Y9dk4oUA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-ORIG-GUID: TMAkN1c1-tMKCM9pgDApnbIdCAgB0ErP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDEwMyBTYWx0ZWRfX7ygD8+sT9Mv/ HAOnERkJvvHaeanRaHzbLIBWVYtVr0dabYJPGWfInapGpS7QX56P/BQxQ2yVhS6LAVRu4/xMvWn ygHJlneGCj/3rb03sQOezijTPTXtWULPq8ZnOyPH0SOesrZeEsga2XWV3wPrIBiqLmt1IflPAZd q1xAiwAcgbj/GYnUu1hCHk3xtbTkSbbS4/0uG2OCntVM/w0k0InVOQbAo7UbLWZS2Oh80U/VR+W 4oLQp3BWotBUnkUSxI+mLsSkG43l/ZTCWX0dVSzuDIhPHKC/yMIBXFO4hZ4Zm48YkznVJCr5p07 7WAkjy4Dx423qbe/qlVETHnsv3XSunkaqdnfUX91v3joQcSAZtx8p5HvGyvXZ+sNI7CvLInTFsy CrqyOM5KyQl+hZI9A6e8MZzv8i7cTPyTs3ALb77IVUN51ZCuuW2HOx0u5PmzOEkPX4b3+a6bOGK 7MqGFvLz3nvPC380Tgg== X-Proofpoint-GUID: TMAkN1c1-tMKCM9pgDApnbIdCAgB0ErP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_04,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230103 Received-SPF: pass client-ip=205.220.180.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This flag will be used to control the HVX IEEE float instructions, which are only available at some Hexagon cores. When unavailable, the instruction is essentially treated as a no-op. Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu.h | 1 + target/hexagon/translate.h | 1 + target/hexagon/attribs_def.h.inc | 3 +++ target/hexagon/cpu.c | 1 + target/hexagon/decode.c | 22 ++++++++++++++++++++++ target/hexagon/translate.c | 1 + 6 files changed, 29 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 85afd59277..77822a48b6 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -127,6 +127,7 @@ struct ArchCPU { bool lldb_compat; target_ulong lldb_stack_adjust; bool short_circuit; + bool ieee_fp_extension; }; #include "cpu_bits.h" diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index b37cb49238..516aab7038 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -70,6 +70,7 @@ typedef struct DisasContext { target_ulong branch_dest; bool is_tight_loop; bool short_circuit; + bool ieee_fp_extension; bool read_after_write; bool has_hvx_overlap; TCGv new_value[TOTAL_PER_THREAD_REGS]; diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc index 9e3a05f882..c85cd5d17c 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -173,5 +173,8 @@ DEF_ATTRIB(NOTE_SHIFT_RESOURCE, "Uses the HVX shift resource.", "", "") DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, "Packet must not have slot 1 store", "", "") DEF_ATTRIB(RESTRICT_LATEPRED, "Predicate can not be used as a .new.", "", "") +/* HVX IEEE FP extension attributes */ +DEF_ATTRIB(HVX_IEEE_FP, "HVX IEEE FP extension instruction", "", "") + /* Keep this as the last attribute: */ DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "") diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index ffd14bb467..8b72a5d3c8 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -54,6 +54,7 @@ static const Property hexagon_cpu_properties[] = { DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 0, qdev_prop_uint32, target_ulong), DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true), + DEFINE_PROP_BOOL("ieee-fp", HexagonCPU, ieee_fp_extension, true), }; const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = { diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index dbc9c630e8..d832a64a17 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -696,6 +696,18 @@ static bool pkt_has_write_conflict(Packet *pkt) return !bitmap_empty(conflict, 32); } +static void convert_to_nop(Insn *insn) +{ + bool is_endloop = insn->is_endloop; + memset(insn, 0, sizeof(*insn)); + insn->opcode = A2_nop; + insn->new_read_idx = -1; + insn->dest_idx = -1; + insn->generate = opcode_genptr[insn->opcode]; + insn->iclass = 0b111; + insn->is_endloop = is_endloop; +} + /* * decode_packet * Decodes packet with given words @@ -746,6 +758,16 @@ int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words, /* Ran out of words! */ return 0; } + + /* Disable HVX IEEE instruction if extension is disabled. */ + if (!ctx->ieee_fp_extension) { + for (i = 0; i < num_insns; i++) { + if (GET_ATTRIB(pkt->insn[i].opcode, A_HVX_IEEE_FP)) { + convert_to_nop(&pkt->insn[i]); + } + } + } + pkt->encod_pkt_size_in_bytes = words_read * 4; pkt->pkt_has_hvx = false; for (i = 0; i < num_insns; i++) { diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 8a223f6e13..9f8104f949 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -988,6 +988,7 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, ctx->branch_cond = TCG_COND_NEVER; ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP); ctx->short_circuit = hex_cpu->short_circuit; + ctx->ieee_fp_extension = hex_cpu->ieee_fp_extension; } static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) -- 2.37.2