* [PULL 0/4] loongarch queue
@ 2025-10-15 3:56 Bibo Mao
2025-10-15 3:56 ` [PULL 1/4] target/loongarch: Add missing TLB flush with different asid Bibo Mao
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Bibo Mao @ 2025-10-15 3:56 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 3bf5c57a11827d9fa706524d57ee3e5af68a429e:
Merge tag 'pull-tcg-20251014' of https://gitlab.com/rth7680/qemu into staging (2025-10-14 10:25:05 -0700)
are available in the Git repository at:
https://github.com/bibo-mao/qemu.git tags/pull-loongarch-20251015
for you to fetch changes up to a9c5e0ed9b63becde7a6188bf71f95e31a132b19:
hw/loongarch/virt: Sort order by hardware device base address (2025-10-15 11:07:37 +0800)
----------------------------------------------------------------
pull-loongarch-20251015 queue
----------------------------------------------------------------
Bibo Mao (4):
target/loongarch: Add missing TLB flush with different asid
target/loongarch: Skip global TLB when calculating replaced TLB
hw/loongarch/virt: Remove header file ls7a.h
hw/loongarch/virt: Sort order by hardware device base address
MAINTAINERS | 1 -
hw/intc/loongarch_pic_kvm.c | 1 -
hw/loongarch/virt-acpi-build.c | 1 -
hw/loongarch/virt-fdt-build.c | 1 -
hw/loongarch/virt.c | 3 +-
include/hw/intc/loongarch_pic_common.h | 2 +-
include/hw/loongarch/virt.h | 75 +++++++++++++++++++++++++---------
include/hw/pci-host/ls7a.h | 39 ------------------
target/loongarch/tcg/tlb_helper.c | 22 ++++++----
9 files changed, 70 insertions(+), 75 deletions(-)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PULL 1/4] target/loongarch: Add missing TLB flush with different asid
2025-10-15 3:56 [PULL 0/4] loongarch queue Bibo Mao
@ 2025-10-15 3:56 ` Bibo Mao
2025-10-15 3:56 ` [PULL 2/4] target/loongarch: Skip global TLB when calculating replaced TLB Bibo Mao
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Bibo Mao @ 2025-10-15 3:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Song Gao
If asid is changed in function helper_csrwr_asid(), qemu TLB is flushed,
however loongArch TLB is still valid. So loongArch TLB need be invalidated
in function invalidate_tlb() with different asid and bit effective need
be cleared.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/tcg/tlb_helper.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 8cfce48a29..f8fada5b9a 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -117,13 +117,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
- uint8_t tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
- if (!tlb_e) {
- return;
- }
-
- tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
pagesize = MAKE_64BIT_MASK(tlb_ps, 1);
mask = MAKE_64BIT_MASK(0, tlb_ps + 1);
@@ -145,11 +139,19 @@ static void invalidate_tlb(CPULoongArchState *env, int index)
{
LoongArchTLB *tlb;
uint16_t csr_asid, tlb_asid, tlb_g;
+ uint8_t tlb_e;
csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
tlb = &env->tlb[index];
+ tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
+ if (!tlb_e) {
+ return;
+ }
+
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+ /* QEMU TLB is flushed when asid is changed */
if (tlb_g == 0 && tlb_asid != csr_asid) {
return;
}
--
2.43.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PULL 2/4] target/loongarch: Skip global TLB when calculating replaced TLB
2025-10-15 3:56 [PULL 0/4] loongarch queue Bibo Mao
2025-10-15 3:56 ` [PULL 1/4] target/loongarch: Add missing TLB flush with different asid Bibo Mao
@ 2025-10-15 3:56 ` Bibo Mao
2025-10-15 3:56 ` [PULL 3/4] hw/loongarch/virt: Remove header file ls7a.h Bibo Mao
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Bibo Mao @ 2025-10-15 3:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Song Gao
When new TLB entry is added, TLB index is calculated from invalid
entry at first and then from different ASID, and randomly at last.
With different ASID, global TLB should be skipped since ASID is not
useful when global TLB is added.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/tcg/tlb_helper.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index f8fada5b9a..f1d183cb64 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -371,7 +371,7 @@ void helper_tlbfill(CPULoongArchState *env)
uint16_t pagesize, stlb_ps;
uint16_t asid, tlb_asid;
LoongArchTLB *tlb;
- uint8_t tlb_e;
+ uint8_t tlb_e, tlb_g;
if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
entryhi = env->CSR_TLBREHI;
@@ -400,7 +400,8 @@ void helper_tlbfill(CPULoongArchState *env)
}
tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
- if (asid != tlb_asid) {
+ tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+ if (tlb_g == 0 && asid != tlb_asid) {
set = i;
}
}
@@ -423,7 +424,8 @@ void helper_tlbfill(CPULoongArchState *env)
}
tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
- if (asid != tlb_asid) {
+ tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+ if (tlb_g == 0 && asid != tlb_asid) {
index = i;
}
}
--
2.43.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PULL 3/4] hw/loongarch/virt: Remove header file ls7a.h
2025-10-15 3:56 [PULL 0/4] loongarch queue Bibo Mao
2025-10-15 3:56 ` [PULL 1/4] target/loongarch: Add missing TLB flush with different asid Bibo Mao
2025-10-15 3:56 ` [PULL 2/4] target/loongarch: Skip global TLB when calculating replaced TLB Bibo Mao
@ 2025-10-15 3:56 ` Bibo Mao
2025-10-15 3:56 ` [PULL 4/4] hw/loongarch/virt: Sort order by hardware device base address Bibo Mao
2025-10-15 23:11 ` [PULL 0/4] loongarch queue Richard Henderson
4 siblings, 0 replies; 6+ messages in thread
From: Bibo Mao @ 2025-10-15 3:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Song Gao
LoongArch virt machine uses GPEX PCIE host bridge rather than 7A host
bridge. Remove header file ls7a.h and put hardware information to file
include/hw/loongarch/virt.h
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
MAINTAINERS | 1 -
hw/intc/loongarch_pic_kvm.c | 1 -
hw/loongarch/virt-acpi-build.c | 1 -
hw/loongarch/virt-fdt-build.c | 1 -
hw/loongarch/virt.c | 1 -
include/hw/intc/loongarch_pic_common.h | 2 +-
include/hw/loongarch/virt.h | 39 ++++++++++++++++++++++++++
include/hw/pci-host/ls7a.h | 39 --------------------------
8 files changed, 40 insertions(+), 45 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 84cfd85e1f..0c766961f3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1308,7 +1308,6 @@ F: include/hw/intc/loongarch_*.h
F: include/hw/intc/loongson_ipi_common.h
F: hw/intc/loongarch_*.c
F: hw/intc/loongson_ipi_common.c
-F: include/hw/pci-host/ls7a.h
F: hw/rtc/ls7a_rtc.c
F: gdb-xml/loongarch*.xml
diff --git a/hw/intc/loongarch_pic_kvm.c b/hw/intc/loongarch_pic_kvm.c
index dd504ec6a6..6cfddf4520 100644
--- a/hw/intc/loongarch_pic_kvm.c
+++ b/hw/intc/loongarch_pic_kvm.c
@@ -10,7 +10,6 @@
#include "hw/boards.h"
#include "hw/intc/loongarch_pch_pic.h"
#include "hw/loongarch/virt.h"
-#include "hw/pci-host/ls7a.h"
#include "system/kvm.h"
static void kvm_pch_pic_access_reg(int fd, uint64_t addr, void *val, bool write)
diff --git a/hw/loongarch/virt-acpi-build.c b/hw/loongarch/virt-acpi-build.c
index 8c2228a772..3694c9827f 100644
--- a/hw/loongarch/virt-acpi-build.c
+++ b/hw/loongarch/virt-acpi-build.c
@@ -21,7 +21,6 @@
#include "system/reset.h"
/* Supported chipsets: */
-#include "hw/pci-host/ls7a.h"
#include "hw/loongarch/virt.h"
#include "hw/acpi/utils.h"
diff --git a/hw/loongarch/virt-fdt-build.c b/hw/loongarch/virt-fdt-build.c
index 728ce46699..1f0ba01f71 100644
--- a/hw/loongarch/virt-fdt-build.c
+++ b/hw/loongarch/virt-fdt-build.c
@@ -12,7 +12,6 @@
#include "hw/loader.h"
#include "hw/loongarch/virt.h"
#include "hw/pci-host/gpex.h"
-#include "hw/pci-host/ls7a.h"
#include "system/device_tree.h"
#include "system/reset.h"
#include "target/loongarch/cpu.h"
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index c1760423ee..efd1f9ac49 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -29,7 +29,6 @@
#include "hw/intc/loongarch_pch_pic.h"
#include "hw/intc/loongarch_pch_msi.h"
#include "hw/intc/loongarch_dintc.h"
-#include "hw/pci-host/ls7a.h"
#include "hw/pci-host/gpex.h"
#include "hw/misc/unimp.h"
#include "hw/loongarch/fw_cfg.h"
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
index f774c975d4..675ba96e64 100644
--- a/include/hw/intc/loongarch_pic_common.h
+++ b/include/hw/intc/loongarch_pic_common.h
@@ -7,7 +7,7 @@
#ifndef HW_LOONGARCH_PIC_COMMON_H
#define HW_LOONGARCH_PIC_COMMON_H
-#include "hw/pci-host/ls7a.h"
+#include "hw/loongarch/virt.h"
#include "hw/sysbus.h"
#define PCH_PIC_INT_ID 0x00
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index 76fa57cd07..0cc1b499a7 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -25,6 +25,7 @@
#define IOCSRF_VM 11
#define IOCSRF_DMSI 15
+/* IOCSR region */
#define VERSION_REG 0x0
#define FEATURE_REG 0x8
#define VENDOR_REG 0x10
@@ -36,6 +37,18 @@
#define LOONGARCH_MAX_CPUS 256
+/* MMIO memory region */
+#define VIRT_PCH_REG_BASE 0x10000000UL
+#define VIRT_PCH_REG_SIZE 0x400
+#define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE)
+#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
+#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
+#define VIRT_RTC_LEN 0x100
+#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000UL
+#define VIRT_PLATFORM_BUS_SIZE 0x02000000
+#define VIRT_PCI_IO_BASE 0x18004000UL
+#define VIRT_PCI_IO_OFFSET 0x4000
+#define VIRT_PCI_IO_SIZE 0xC000
#define VIRT_FWCFG_BASE 0x1e020000UL
#define VIRT_BIOS_BASE 0x1c000000UL
#define VIRT_BIOS_SIZE (16 * MiB)
@@ -44,6 +57,16 @@
#define VIRT_FLASH0_SIZE VIRT_BIOS_SIZE
#define VIRT_FLASH1_BASE 0x1d000000UL
#define VIRT_FLASH1_SIZE (16 * MiB)
+#define VIRT_UART_BASE 0x1fe001e0UL
+#define VIRT_UART_SIZE 0x100
+#define VIRT_PCI_CFG_BASE 0x20000000UL
+#define VIRT_PCI_CFG_SIZE 0x08000000UL
+#define VIRT_DINTC_BASE 0x2FE00000UL
+#define VIRT_DINTC_SIZE 0x00100000UL
+#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
+#define VIRT_PCH_MSI_SIZE 0x8
+#define VIRT_PCI_MEM_BASE 0x40000000UL
+#define VIRT_PCI_MEM_SIZE 0x40000000UL
#define VIRT_LOWMEM_BASE 0
#define VIRT_LOWMEM_SIZE 0x10000000
@@ -53,6 +76,22 @@
#define VIRT_GED_REG_ADDR QEMU_ALIGN_UP(VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN, 4)
#define VIRT_GED_CPUHP_ADDR QEMU_ALIGN_UP(VIRT_GED_REG_ADDR + ACPI_GED_REG_COUNT, 4)
+/*
+ * GSI_BASE is hard-coded with 64 in linux kernel, else kernel fails to boot
+ * 0 - 15 GSI for ISA devices even if there is no ISA devices
+ * 16 - 63 GSI for CPU devices such as timers/perf monitor etc
+ * 64 - GSI for external devices
+ */
+#define VIRT_PCH_PIC_IRQ_NUM 32
+#define VIRT_GSI_BASE 64
+#define VIRT_DEVICE_IRQS 16
+#define VIRT_UART_IRQ (VIRT_GSI_BASE + 2)
+#define VIRT_UART_COUNT 4
+#define VIRT_RTC_IRQ (VIRT_GSI_BASE + 6)
+#define VIRT_SCI_IRQ (VIRT_GSI_BASE + 7)
+#define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 8)
+#define VIRT_PLATFORM_BUS_NUM_IRQS 2
+
#define COMMAND_LINE_SIZE 512
#define FDT_BASE 0x100000
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
index bfdbfe3614..33e7942de9 100644
--- a/include/hw/pci-host/ls7a.h
+++ b/include/hw/pci-host/ls7a.h
@@ -13,43 +13,4 @@
#include "qemu/range.h"
#include "qom/object.h"
-#define VIRT_PCI_MEM_BASE 0x40000000UL
-#define VIRT_PCI_MEM_SIZE 0x40000000UL
-#define VIRT_PCI_IO_OFFSET 0x4000
-#define VIRT_PCI_CFG_BASE 0x20000000
-#define VIRT_PCI_CFG_SIZE 0x08000000
-#define VIRT_PCI_IO_BASE 0x18004000UL
-#define VIRT_PCI_IO_SIZE 0xC000
-
-#define VIRT_PCH_REG_BASE 0x10000000UL
-#define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE)
-#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
-#define VIRT_DINTC_SIZE 0x100000UL
-#define VIRT_DINTC_BASE 0x2FE00000UL
-#define VIRT_PCH_REG_SIZE 0x400
-#define VIRT_PCH_MSI_SIZE 0x8
-
-/*
- * GSI_BASE is hard-coded with 64 in linux kernel, else kernel fails to boot
- * 0 - 15 GSI for ISA devices even if there is no ISA devices
- * 16 - 63 GSI for CPU devices such as timers/perf monitor etc
- * 64 - GSI for external devices
- */
-#define VIRT_PCH_PIC_IRQ_NUM 32
-#define VIRT_GSI_BASE 64
-#define VIRT_DEVICE_IRQS 16
-#define VIRT_UART_COUNT 4
-#define VIRT_UART_IRQ (VIRT_GSI_BASE + 2)
-#define VIRT_UART_BASE 0x1fe001e0
-#define VIRT_UART_SIZE 0x100
-#define VIRT_RTC_IRQ (VIRT_GSI_BASE + 6)
-#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
-#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
-#define VIRT_RTC_LEN 0x100
-#define VIRT_SCI_IRQ (VIRT_GSI_BASE + 7)
-
-#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000
-#define VIRT_PLATFORM_BUS_SIZE 0x2000000
-#define VIRT_PLATFORM_BUS_NUM_IRQS 2
-#define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 8)
#endif
--
2.43.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PULL 4/4] hw/loongarch/virt: Sort order by hardware device base address
2025-10-15 3:56 [PULL 0/4] loongarch queue Bibo Mao
` (2 preceding siblings ...)
2025-10-15 3:56 ` [PULL 3/4] hw/loongarch/virt: Remove header file ls7a.h Bibo Mao
@ 2025-10-15 3:56 ` Bibo Mao
2025-10-15 23:11 ` [PULL 0/4] loongarch queue Richard Henderson
4 siblings, 0 replies; 6+ messages in thread
From: Bibo Mao @ 2025-10-15 3:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Song Gao
With header file include/hw/loongarch/virt.h, hardware device definition
order is sorted by its base address. Add remove unused macro
VIRT_IOAPIC_REG_BASE and VIRT_MISC_REG_BASE.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/virt.c | 2 +-
include/hw/loongarch/virt.h | 42 +++++++++++++++++--------------------
2 files changed, 20 insertions(+), 24 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index efd1f9ac49..49434ad182 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -520,7 +520,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
}
/* PCH_PIC memory region */
- memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
+ memory_region_add_subregion(get_system_memory(), VIRT_PCH_REG_BASE,
sysbus_mmio_get_region(SYS_BUS_DEVICE(pch_pic), 0));
/* Connect pch_pic irqs to extioi */
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index 0cc1b499a7..27b1755802 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -13,50 +13,47 @@
#include "hw/block/flash.h"
#include "hw/loongarch/boot.h"
-#define IOCSRF_TEMP 0
-#define IOCSRF_NODECNT 1
-#define IOCSRF_MSI 2
-#define IOCSRF_EXTIOI 3
-#define IOCSRF_CSRIPI 4
-#define IOCSRF_FREQCSR 5
-#define IOCSRF_FREQSCALE 6
-#define IOCSRF_DVFSV1 7
-#define IOCSRF_GMOD 9
-#define IOCSRF_VM 11
-#define IOCSRF_DMSI 15
-
/* IOCSR region */
#define VERSION_REG 0x0
#define FEATURE_REG 0x8
+#define IOCSRF_TEMP 0
+#define IOCSRF_NODECNT 1
+#define IOCSRF_MSI 2
+#define IOCSRF_EXTIOI 3
+#define IOCSRF_CSRIPI 4
+#define IOCSRF_FREQCSR 5
+#define IOCSRF_FREQSCALE 6
+#define IOCSRF_DVFSV1 7
+#define IOCSRF_GMOD 9
+#define IOCSRF_VM 11
+#define IOCSRF_DMSI 15
#define VENDOR_REG 0x10
#define CPUNAME_REG 0x20
#define MISC_FUNC_REG 0x420
-#define IOCSRM_EXTIOI_EN 48
-#define IOCSRM_EXTIOI_INT_ENCODE 49
-#define IOCSRM_DMSI_EN 51
+#define IOCSRM_EXTIOI_EN 48
+#define IOCSRM_EXTIOI_INT_ENCODE 49
+#define IOCSRM_DMSI_EN 51
#define LOONGARCH_MAX_CPUS 256
/* MMIO memory region */
#define VIRT_PCH_REG_BASE 0x10000000UL
#define VIRT_PCH_REG_SIZE 0x400
-#define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE)
-#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
-#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
+#define VIRT_RTC_REG_BASE 0x100d0100UL
#define VIRT_RTC_LEN 0x100
#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000UL
#define VIRT_PLATFORM_BUS_SIZE 0x02000000
#define VIRT_PCI_IO_BASE 0x18004000UL
#define VIRT_PCI_IO_OFFSET 0x4000
#define VIRT_PCI_IO_SIZE 0xC000
-#define VIRT_FWCFG_BASE 0x1e020000UL
#define VIRT_BIOS_BASE 0x1c000000UL
-#define VIRT_BIOS_SIZE (16 * MiB)
+#define VIRT_BIOS_SIZE 0x01000000UL
#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
#define VIRT_FLASH0_BASE VIRT_BIOS_BASE
#define VIRT_FLASH0_SIZE VIRT_BIOS_SIZE
#define VIRT_FLASH1_BASE 0x1d000000UL
-#define VIRT_FLASH1_SIZE (16 * MiB)
+#define VIRT_FLASH1_SIZE 0x01000000UL
+#define VIRT_FWCFG_BASE 0x1e020000UL
#define VIRT_UART_BASE 0x1fe001e0UL
#define VIRT_UART_SIZE 0x100
#define VIRT_PCI_CFG_BASE 0x20000000UL
@@ -70,6 +67,7 @@
#define VIRT_LOWMEM_BASE 0
#define VIRT_LOWMEM_SIZE 0x10000000
+#define FDT_BASE 0x100000
#define VIRT_HIGHMEM_BASE 0x80000000
#define VIRT_GED_EVT_ADDR 0x100e0000
#define VIRT_GED_MEM_ADDR QEMU_ALIGN_UP(VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN, 4)
@@ -94,8 +92,6 @@
#define COMMAND_LINE_SIZE 512
-#define FDT_BASE 0x100000
-
struct LoongArchVirtMachineState {
/*< private >*/
MachineState parent_obj;
--
2.43.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PULL 0/4] loongarch queue
2025-10-15 3:56 [PULL 0/4] loongarch queue Bibo Mao
` (3 preceding siblings ...)
2025-10-15 3:56 ` [PULL 4/4] hw/loongarch/virt: Sort order by hardware device base address Bibo Mao
@ 2025-10-15 23:11 ` Richard Henderson
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2025-10-15 23:11 UTC (permalink / raw)
To: qemu-devel
On 10/14/25 20:56, Bibo Mao wrote:
> The following changes since commit 3bf5c57a11827d9fa706524d57ee3e5af68a429e:
>
> Merge tag 'pull-tcg-20251014' ofhttps://gitlab.com/rth7680/qemu into staging (2025-10-14 10:25:05 -0700)
>
> are available in the Git repository at:
>
> https://github.com/bibo-mao/qemu.git tags/pull-loongarch-20251015
>
> for you to fetch changes up to a9c5e0ed9b63becde7a6188bf71f95e31a132b19:
>
> hw/loongarch/virt: Sort order by hardware device base address (2025-10-15 11:07:37 +0800)
>
> ----------------------------------------------------------------
> pull-loongarch-20251015 queue
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-10-15 23:12 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-15 3:56 [PULL 0/4] loongarch queue Bibo Mao
2025-10-15 3:56 ` [PULL 1/4] target/loongarch: Add missing TLB flush with different asid Bibo Mao
2025-10-15 3:56 ` [PULL 2/4] target/loongarch: Skip global TLB when calculating replaced TLB Bibo Mao
2025-10-15 3:56 ` [PULL 3/4] hw/loongarch/virt: Remove header file ls7a.h Bibo Mao
2025-10-15 3:56 ` [PULL 4/4] hw/loongarch/virt: Sort order by hardware device base address Bibo Mao
2025-10-15 23:11 ` [PULL 0/4] loongarch queue Richard Henderson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).