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Thu, 21 Oct 2021 18:12:44 -0700 (PDT) Subject: Re: [RFC PATCH v5 3/3] riscv: Enable custom CSR support for Andes AX25 and A25 CPUs To: Ruinland Chuan-Tzu Tsai , alistair23@gmail.com, wangjunqiang@iscas.ac.cn, bmeng.cn@gmail.com References: <20211021150921.721630-1-ruinland@andestech.com> <20211021150921.721630-4-ruinland@andestech.com> From: Richard Henderson Message-ID: <4f7798d8-944a-b2d9-ff27-8a1fdf86b4e0@linaro.org> Date: Thu, 21 Oct 2021 18:12:42 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211021150921.721630-4-ruinland@andestech.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.867, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, dylan@andestech.com, ycliang@andestech.com, qemu-devel@nongnu.org, alankao@andestech.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/21/21 8:09 AM, Ruinland Chuan-Tzu Tsai wrote: > diff --git a/target/riscv/csr_andes.c b/target/riscv/csr_andes.c > new file mode 100644 > index 0000000000..8617f40483 > --- /dev/null > +++ b/target/riscv/csr_andes.c > @@ -0,0 +1,183 @@ > +/* > + * Copyright (c) 2021 Andes Technology Corp. > + * SPDX-License-Identifier: GPL-2.0+ > + * Andes custom CSR table and handling functions > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "cpu.h" > +#include "qemu/main-loop.h" > +#include "exec/exec-all.h" > +#include "andes_cpu_bits.h" > + > +struct andes_csr_val { > + target_long uitb; > +}; docs/devel/style.rst: Use a typedef and CamelCase. And of course per review of patch 2, this needs to go elsewhere. You need to add a subsection to machine.c to migrate this new state. With respect to the custom instructions, I suggested adding an ext_andes field. I would expect these CSRs, which go with those instructions, to use the same predicate. > +riscv_custom_csr_operations andes_custom_csr_table[MAX_CUSTOM_CSR_NUM] = { ... > + {CSR_TXEVT, { "csr_txevt", any, read_zero, write_stub} }, > + {0, { "", NULL, NULL, NULL } }, > + }; Indentation here. I think you should not export the array itself, but instead void andes_setup_custom_csrs(RISCVCPUClass *cc) { setup_custom_csrs(cc, andes_custom_csr_table, ARRAY_SIZE(andes_custom_csr_table)); } r~