From: Richard Henderson <richard.henderson@linaro.org>
To: "Emilio G. Cota" <cota@braap.org>, qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v3 4/4] cputlb: read CPUTLBEntry.addr_write atomically
Date: Mon, 15 Oct 2018 19:52:34 -0700 [thread overview]
Message-ID: <4f8df676-f854-e7fe-afed-51099a8abffe@linaro.org> (raw)
In-Reply-To: <20181005211450.847-5-cota@braap.org>
On 10/5/18 2:14 PM, Emilio G. Cota wrote:
> - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
> + target_ulong tlb_addr =
> + atomic_read(&env->tlb_table[mmu_idx][index].addr_write);
This fails for 32-bit hosts emulating 64-bit hosts.
I think you need a separate helper function. Perhaps
static inline target_ulong tlb_addr_write(CPUTLBEntry *ent)
{
#if TCG_OVERSIZED_GUEST
return ent->addr_write;
#else
return atomic_read(&ent->addr_write);
#endif
}
I'm going to drop this patch from my queue for now.
We can fix it up this week some time.
r~
next prev parent reply other threads:[~2018-10-16 2:52 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-05 21:14 [Qemu-devel] [PATCH v3 0/4] per-TLB lock Emilio G. Cota
2018-10-05 21:14 ` [Qemu-devel] [PATCH v3 1/4] exec: introduce tlb_init Emilio G. Cota
2018-10-05 21:14 ` [Qemu-devel] [PATCH v3 2/4] cputlb: fix assert_cpu_is_self macro Emilio G. Cota
2018-10-05 21:14 ` [Qemu-devel] [PATCH v3 3/4] cputlb: serialize tlb updates with env->tlb_lock Emilio G. Cota
2018-10-08 13:57 ` Alex Bennée
2018-10-08 14:12 ` Emilio G. Cota
2018-10-08 14:30 ` Alex Bennée
2018-10-05 21:14 ` [Qemu-devel] [PATCH v3 4/4] cputlb: read CPUTLBEntry.addr_write atomically Emilio G. Cota
2018-10-16 2:52 ` Richard Henderson [this message]
2018-10-16 6:03 ` Paolo Bonzini
2018-10-16 15:12 ` Emilio G. Cota
2018-10-16 15:56 ` Richard Henderson
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