From: Richard Henderson <richard.henderson@linaro.org>
To: Keith Packard <keithp@keithp.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Laurent Vivier <laurent@vivier.eu>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH] riscv: Add semihosting support [v8]
Date: Mon, 26 Oct 2020 12:22:54 -0700 [thread overview]
Message-ID: <4faf9e1f-45bd-9f47-8a5f-be7b6fcdf540@linaro.org> (raw)
In-Reply-To: <20201023214940.917885-1-keithp@keithp.com>
On 10/23/20 2:49 PM, Keith Packard via wrote:
> static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
> {
> - generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
> + uint32_t pre = opcode_at(&ctx->base, ctx->base.pc_next - 4);
> + uint32_t ebreak = opcode_at(&ctx->base, ctx->base.pc_next);
> + uint32_t post = opcode_at(&ctx->base, ctx->base.pc_next + 4);
Alistair asked if this approach is ok. I think it is. There are other places
in which we scan forward (usually only forward, not backward, but this is a
special nop, so it doesn't matter).
However:
(1) No need to re-read the current ebreak insn. That is how we arrived here,
after all.
(2) You need to check for page boundaries before reading pre and post.
Otherwise you could wind up with SIGSEGV (or the equivalent internal qemu
exception) when you shouldn't.
r~
next prev parent reply other threads:[~2020-10-26 19:24 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 21:49 [PATCH] riscv: Add semihosting support [v8] Keith Packard via
2020-10-24 0:22 ` Alistair Francis
2020-10-24 5:56 ` Keith Packard via
2020-10-24 15:00 ` Alistair Francis
2020-10-26 19:26 ` Richard Henderson
2020-10-26 21:06 ` Keith Packard via
2020-10-26 19:22 ` Richard Henderson [this message]
2020-10-26 21:20 ` Keith Packard via
-- strict thread matches above, loose matches on Subject: below --
2020-09-17 21:02 [PATCH] riscv: Add semihosting support [v7] Keith Packard via
2020-09-17 21:13 ` [PATCH] riscv: Add semihosting support [v8] Keith Packard via
2020-09-17 21:18 ` no-reply
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