From: Richard Henderson <richard.henderson@linaro.org>
To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: philmd@redhat.com, bin.meng@windriver.com,
alistair.francis@wdc.com, palmer@dabbelt.com,
fabien.portas@grenoble-inp.org
Subject: Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target
Date: Mon, 29 Nov 2021 13:13:21 +0100 [thread overview]
Message-ID: <4fceecbf-7424-3a0d-d350-fb677f6b1104@linaro.org> (raw)
In-Reply-To: <20211128135719.50444-1-frederic.petrot@univ-grenoble-alpes.fr>
On 11/28/21 2:57 PM, Frédéric Pétrot wrote:
> This series of patches provides partial 128-bit support for the riscv
> target architecture, namely RVI and RVM, with minimal csr support.
>
> Thanks again for the reviews and suggestions.
>
> v6:
> - support for '-cpu rv128' in qemu-system-riscv64 to handle 128-bit
> executables (no more qemu-system-riscv128)
> - remove useless (and buggy) big-endian support in lq/sq
This also fails make check. With
../qemu/configure --enable-debug
--target-list=riscv64-linux-user,riscv64-softmmu,riscv32-softmmu,riscv32-linux-user
watch qemu-iotest 040 fail.
r~
next prev parent reply other threads:[~2021-11-29 12:14 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-28 13:57 [PATCH v6 00/18] Adding partial support for 128-bit riscv target Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 01/18] exec/memop: Adding signedness to quad definitions Frédéric Pétrot
2021-12-09 1:15 ` Alistair Francis
2021-11-28 13:57 ` [PATCH v6 02/18] exec/memop: Adding signed quad and octo defines Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 03/18] qemu/int128: addition of div/rem 128-bit operations Frédéric Pétrot
2021-11-29 10:07 ` Richard Henderson
2021-11-29 14:27 ` Frédéric Pétrot
2021-11-29 14:32 ` Richard Henderson
2021-11-28 13:57 ` [PATCH v6 04/18] target/riscv: additional macros to check instruction support Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 05/18] target/riscv: separation of bitwise logic and arithmetic helpers Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 06/18] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 07/18] target/riscv: setup everything for rv64 to support rv128 execution Frédéric Pétrot
2021-12-09 1:18 ` Alistair Francis
2021-11-28 13:57 ` [PATCH v6 08/18] target/riscv: moving some insns close to similar insns Frédéric Pétrot
2021-12-01 12:33 ` Alistair Francis
2021-11-28 13:57 ` [PATCH v6 09/18] target/riscv: accessors to registers upper part and 128-bit load/store Frédéric Pétrot
2021-12-10 2:03 ` Alistair Francis
2021-11-28 13:57 ` [PATCH v6 10/18] target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 11/18] target/riscv: support for 128-bit U-type instructions Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 12/18] target/riscv: support for 128-bit shift instructions Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 13/18] target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 14/18] target/riscv: support for 128-bit M extension Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 15/18] target/riscv: adding high part of some csrs Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 17/18] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot
2021-11-28 13:57 ` [PATCH v6 18/18] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot
2021-11-29 10:47 ` [PATCH v6 00/18] Adding partial support for 128-bit riscv target Richard Henderson
2021-11-29 12:13 ` Richard Henderson [this message]
2021-11-29 13:24 ` Frédéric Pétrot
2021-12-06 15:00 ` Frédéric Pétrot
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