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Thu, 15 May 2025 15:44:31 +0000 (GMT) Message-ID: <4fd5d6f8-beee-4e5d-adf7-baa6288a9e83@linux.ibm.com> Date: Thu, 15 May 2025 10:44:30 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 45/50] ppc/xive2: redistribute group interrupts on context push To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?UTF-8?B?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Glenn Miles , Caleb Schlossin References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-46-npiggin@gmail.com> Content-Language: en-US From: Mike Kowal In-Reply-To: <20250512031100.439842-46-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: N2nt5qAv8b0oSmWfcey5hLm0TKE3r-MJ X-Authority-Analysis: v=2.4 cv=XK4wSRhE c=1 sm=1 tr=0 ts=68260be2 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=89eXdJJYgY74zT-coKsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: VQBXvFZLX93NgHoRFVch7GwCPbhjkA8x X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE1NSBTYWx0ZWRfX3WqftHDbhRnV yKthhlj6o0IrI5afmXBijhOWH1FqbQs9kBHy9Ja/2z6UgOare2l0wGRrAaPJT6iS0WDJgGw3vSR lr8yrY8EzQ6XJIH7zNZQ8SjLtB7rG91CRl3KcE6ckP66qVJfgXF90iUMwPMJmkBMIZoSP30X+MF rJJb6cBuJvX75M1pOYqw3sh2AqS6Laper0rZiy4ieiG2IzRopMIe6EBUoQ0DM7cFNkZaIHfPbNe lbN5bt4reaBRsIGOpFZPqq4n099NiKJMXKeSZvb7gu+VUYFkMMZjqPQ2IF2oNNuFdfZJC8rBHe5 3eE7hnjk8nxNKMTAU8j4hqyD9qPhpw7aDa0G6fHDRm9PW4XzR2eeyk+5N9g14Sdpnm2fp9kJ4Jy by0DyAce3sfosvYATo9jDfqtGlhyb4C6Jb9E0ihX1vJlX9MdOUNlRaqS/qKg3aJOvQ/m2Q0p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_06,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 mlxscore=0 bulkscore=0 mlxlogscore=910 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 adultscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150155 Received-SPF: pass client-ip=148.163.156.1; envelope-from=kowal@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/11/2025 10:10 PM, Nicholas Piggin wrote: > When pushing a context, any presented group interrupt should be > redistributed before processing pending interrupts to present > highest priority. > > This can occur when pushing the POOL ring when the valid PHYS > ring has a group interrupt presented, because they share signal > registers. Reviewed-by: Michael Kowal Thanks,  MAK > > Signed-off-by: Nicholas Piggin > --- > hw/intc/xive2.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index 21cd07df68..392ac6077e 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -945,8 +945,9 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, > uint8_t nvp_blk, uint32_t nvp_idx, > bool do_restore) > { > + uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); > uint8_t *regs = &tctx->regs[ring]; > - uint8_t ipb; > + uint8_t ipb, nsr = sig_regs[TM_NSR]; > Xive2Nvp nvp; > > /* > @@ -978,6 +979,11 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, > /* IPB bits in the backlog are merged with the TIMA IPB bits */ > regs[TM_IPB] |= ipb; > > + if (xive_nsr_indicates_group_exception(ring, nsr)) { > + /* redistribute precluded active grp interrupt */ > + g_assert(ring == TM_QW2_HV_POOL); /* PHYS ring has the grp interrupt */ > + xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr)); > + } > xive2_tctx_process_pending(tctx, ring == TM_QW2_HV_POOL ? > TM_QW3_HV_PHYS : ring); > }