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[213.30.8.110]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f3368fbasm103084755e9.2.2025.05.16.04.50.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 May 2025 04:50:05 -0700 (PDT) Message-ID: <4feacbca-76fe-42cd-a8f6-9daf70f2b437@linaro.org> Date: Fri, 16 May 2025 12:50:04 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PULL 34/46] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin References: <20250309135130.545764-1-clg@redhat.com> <20250309135130.545764-35-clg@redhat.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250309135130.545764-35-clg@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/3/25 14:51, Cédric Le Goater wrote: > From: Jamin Lin > > Introduce a new ast2700 INTCIO class to support AST2700 INTCIO. > Added new register definitions for INTCIO, including enable and status > registers for IRQs GICINT192 through GICINT197. > Created a dedicated IRQ array for INTCIO, supporting six input pins and six > output pins, aligning with the newly defined registers. > Implemented "aspeed_intcio_read" and "aspeed_intcio_write" to handle > INTCIO-specific register access. > Signed-off-by: Jamin Lin > Reviewed-by: Cédric Le Goater > Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-18-jamin_lin@aspeedtech.com > Signed-off-by: Cédric Le Goater > --- > include/hw/intc/aspeed_intc.h | 1 + > hw/intc/aspeed_intc.c | 112 ++++++++++++++++++++++++++++++++++ > 2 files changed, 113 insertions(+) > +static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset, > + unsigned int size) > +{ > + AspeedINTCState *s = ASPEED_INTC(opaque); > + const char *name = object_get_typename(OBJECT(s)); > + uint32_t reg = offset >> 2; > + uint32_t value = 0; > + > + value = s->regs[reg]; > + trace_aspeed_intc_read(name, offset, size, value); > + > + return value; > +} > +static const MemoryRegionOps aspeed_intcio_ops = { > + .read = aspeed_intcio_read, > + .write = aspeed_intcio_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, > + } Could be safer to also add .impl.min_access_size = 4. > +};