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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c48de68sm40362941f8f.67.2025.08.11.03.34.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Aug 2025 03:34:27 -0700 (PDT) Message-ID: <4ff26d30-3b0d-4392-8bac-698ecb0fbdde@linaro.org> Date: Mon, 11 Aug 2025 12:34:26 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC 04/11] hw/arm/smmuv3: Enable command processing for the Secure state To: Tao Tang , Pierrick Bouvier , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Eric Auger , Peter Maydell , Chen Baozi , smostafa@google.com, jean-philippe@linaro.org References: <20250806151134.365755-1-tangtao1634@phytium.com.cn> <20250806151134.365755-5-tangtao1634@phytium.com.cn> <0b38d386-9d8b-46bd-a981-718cc7281eb6@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, On 10/8/25 18:59, Tao Tang wrote: > On 2025/8/7 05:55, Pierrick Bouvier wrote: >> On 8/6/25 8:11 AM, Tao Tang wrote: >>> This patch enables the secure command queue, providing a dedicated >>> interface for secure software to issue commands to the SMMU. Based on >>> the SMMU_S_CMDQ_BASE configuration, the SMMU now fetches command >>> entries directly from the Secure PA space so that we need to pass the >>> memory transaction attributes when reading the command queue. >>> >>> This provides a parallel command mechanism to the non-secure world. >>> >>> Signed-off-by: Tao Tang >>> --- >>>   hw/arm/smmuv3-internal.h |  8 ++++-- >>>   hw/arm/smmuv3.c          | 55 +++++++++++++++++++++++++--------------- >>>   hw/arm/trace-events      |  2 +- >>>   3 files changed, 41 insertions(+), 24 deletions(-) >>> >>> diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h >>> index 1a8b1cb204..5b2ca00832 100644 >>> --- a/hw/arm/smmuv3-internal.h >>> +++ b/hw/arm/smmuv3-internal.h >>> @@ -319,9 +319,13 @@ static inline void queue_cons_incr(SMMUQueue *q) >>>       q->cons = deposit32(q->cons, 0, q->log2size + 1, q->cons + 1); >>>   } >>>   -static inline bool smmuv3_cmdq_enabled(SMMUv3State *s) >>> +static inline bool smmuv3_cmdq_enabled(SMMUv3State *s, bool is_secure) >>>   { >>> -    return FIELD_EX32(s->cr[0], CR0, CMDQEN); >>> +    if (is_secure) { >>> +        return FIELD_EX32(s->secure_cr[0], S_CR0, CMDQEN); >>> +    } else { >>> +        return FIELD_EX32(s->cr[0], CR0, CMDQEN); >>> +    } >>>   } >> This looks like a reasonable and readable approach to support secure >> and non secure accesses. > > Hi Pierrick, > > Thank you so much for taking the time to review and for the very > positive feedback. > > I'm very relieved to hear you find the approach "reasonable and > readable". I was hoping that explicitly passing the parameter was the > right way to avoid issues with global state or code duplication, and > your confirmation is the best encouragement I could ask for. An alternative (also suggested in patch #1) is to use index for banked registers. For example we use M_REG_NS with Cortex-M cores (target/arm/cpu-qom.h): /* For M profile, some registers are banked secure vs non-secure; * these are represented as a 2-element array where the first * element is the non-secure copy and the second is the secure copy. * When the CPU does not have implement the security extension then * only the first element is used. * This means that the copy for the current security state can be * accessed via env->registerfield[env->v7m.secure] (whether the * security extension is implemented or not). */ enum { M_REG_NS = 0, M_REG_S = 1, M_REG_NUM_BANKS = 2, }; And generally for address spaces (target/arm/cpu.h): typedef enum ARMASIdx { ARMASIdx_NS = 0, ARMASIdx_S = 1, ARMASIdx_TagNS = 2, ARMASIdx_TagS = 3, } ARMASIdx; (not sure this one is appropriate here).