Re: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order

["Cédric Le Goater" <clg@redhat.com>]

Hello Jamin,

On 9/23/25 10:31, Jamin Lin wrote:
> Hi Cédric
> 
>> Subject: Re: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP
>> and ensure correct device realization order
>>
>> On 7/17/25 05:40, Jamin Lin wrote:
>>> AST2700 has a single SCU hardware block, memory-mapped at
>>> 0x12C02000–0x12C03FFF from the perspective of the main CA35 processor
>>> (PSP). The SSP coprocessor accesses this same SCU block at a different
>> address: 0x72C02000–0x72C03FFF.
>>>
>>> To support this shared SCU model, this commit introduces
>>> "ssp.scu_mr_alias", a "MemoryRegion" alias of the original SCU region
>>> ("s->scu.iomem"). The alias is realized during SSP SoC setup and mapped into
>> the SSP's SoC memory map.
>>>
>>> Additionally, because the SCU must be realized before the SSP can
>>> create an alias to it, the device realization order is explicitly managed:
>>> "aspeed_soc_ast2700_ssp_realize()" is invoked after the SCU is initialized.
>>>
>>> This ensures that PSP and SSP access a consistent SCU state, as expected by
>> hardware.
>>
>> The SCU model of the main SoC could be passed as a link to the coprocessor
>> models, like done for the timer model. But the problem is elsewhere.
>> I think we need to rework the coprocessor models.
>>
>> Currently, Aspeed27x0TSPSoCState and Aspeed27x0SSPSoCState inherit from
>> AspeedSoCState and looking at the aspeed_soc_ast27x0{t,s}sp_init handlers, it
>> seems clear that AspeedSoCState has too much state. We need a simplified
>> version of AspeedSoCState for the coprocessors.
>>
>> Please rethink the proposal with that in mind.
>>
> This rework is quite large. To make review easier and avoid an oversized series, I plan to split it into 3 separate patch series:
> 
> Series A
> 1. Move the boot ROM helper from aspeed.c to aspeed_soc_common.c and declare it in aspeed_soc.h, so all ASPEED boards can reuse it.
> 2. Support vbootrom with coprocessor.

This should be quickly merged.

> 
> Series B
> 3. Migrate all ASPEED coprocessors (e.g. SSP/TSP) to a common AspeedCoprocessorState.

Is 'AspeedCoprocessorState' a new model structure minimizing the number
of sub controllers ? if so, looks good. Could be merged fairly quickly.

> Series C
> 4. Introduce an FC SoC class.
> 5. Refactor SSP/TSP to share common controllers (e.g. SRAM/SCU) with PSP.
> 6. Gate SSP/TSP CPU power via the SCU

OK That's the long term goal. Let's plan it for QEMU 10.2.

Thanks,

C.