From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37326) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SrrmN-0001RM-PQ for qemu-devel@nongnu.org; Thu, 19 Jul 2012 10:32:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SrrmD-0007jc-Ub for qemu-devel@nongnu.org; Thu, 19 Jul 2012 10:32:35 -0400 Received: from cantor2.suse.de ([195.135.220.15]:40239 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SrrmD-0007iz-L6 for qemu-devel@nongnu.org; Thu, 19 Jul 2012 10:32:25 -0400 Message-ID: <50081A74.2050102@suse.de> Date: Thu, 19 Jul 2012 16:32:20 +0200 From: =?ISO-8859-1?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <20120717154609.GA16640@avionic-0098.mockup.avionic-design.de> In-Reply-To: <20120717154609.GA16640@avionic-0098.mockup.avionic-design.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] Keeping a secondary CPU in reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Thierry Reding Cc: Vincent Palatin , qemu-devel@nongnu.org -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi Thierry, Am 17.07.2012 17:46, schrieb Thierry Reding: > I've been toying around with adding NVIDIA Tegra support to QEMU. > While adding SMP support I came across a problem: on Tegra, the > secondary CPU is kept in reset by the clock-and-reset controller > (CRC). When bringing up the secondary CPU, the OS writes a given > register in the CRC to release the CPU, after which it starts > running. Other hardware blocks can also be reset by writing other > registers in the CRC. [snip] Please take a look at the Tegra feature page on the Wiki, which has a link to my repository where I've been rebasing an older series by Vincent Palatin. http://wiki.qemu.org/Features/Tegra2 It does not use the generic arm_boot iirc but its own implementation. There's a tegra_clocks device that probably corresponds to the CRC. What's still missing on my branch is the actual machine that instantiates the devices I've been working on. A big TODO where I could use some help is refactoring EHCI so that we can have the current PCIDevice plus a new SysBus device (or DeviceState?) for Tegra. Regards, Andreas - --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.18 (GNU/Linux) iQIcBAEBAgAGBQJQCBp0AAoJEPou0S0+fgE/xkUP/RK5/0Ye7Bsd7yx0Q9cTATUz wgdN2amH52Fbq2UG8kqokyp3u+ohkz4hyAdMCXPimQzkCdIjPUx9Smi+q++1auD1 CCMkDwpgrFgECglkixa5FVS9mokpJDVhLMt5QPlduHEa9/I1e59wbh2eDPpnSOoz Ddh+0ZwcR9cHe+h9Xsgf7qmWKyUetKqQw5MLxukfSf7tnzUWrMn7cbZud7W3HlQR XVSr8iGWf4zkD9nX43IbrQOR4W8n+Wk1w95yiIq59uq2Zei96YJhL9ZUvqVIQ3m2 GF4S0K3Y8Qjd6JVpRUv53mTTjEz5+FTqVz8Q538QJ+zhJ+z3lAqGx6XObk8bqoX7 Ojl2GjUL8W4Gddtu8OrKoECkkixuLhgmQ/ScCLSoSVSY+8hhQ88fcx3aWxK+nSpQ RVsUqR9bds995W+yb4rI8NfbcSD/x4ucrsDhBKKoIUnT663VuGGxXJVu9K8ATC8Z 46ZFDh2zrPPoucGzHBC6Nm/SygTX7cmDUf7pHTI4Uzc9uTnPLVzHg7+JfH0nyNvJ Zm/DcfWiToauIf5CQq4X5chAFtRBzeP0FntwhD1hWYaOzgUe5DwIKGZljchO7lH3 2SJDiUBz9wSy7hqurFKF7lFCIlenR5BADRMGvAKdQ0IX1P/vUNC+bI30jyz8P777 hGbTENc9RYXFtjwNV6b0 =3DBojw -----END PGP SIGNATURE-----