From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59574) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Styag-0003py-QJ for qemu-devel@nongnu.org; Wed, 25 Jul 2012 06:13:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1StyaZ-0005qo-Jt for qemu-devel@nongnu.org; Wed, 25 Jul 2012 06:13:14 -0400 Received: from mail-gg0-f173.google.com ([209.85.161.173]:42344) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1StyaZ-0005qd-Fr for qemu-devel@nongnu.org; Wed, 25 Jul 2012 06:13:07 -0400 Received: by ggnp1 with SMTP id p1so491030ggn.4 for ; Wed, 25 Jul 2012 03:13:07 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <500FC6A7.9090809@redhat.com> Date: Wed, 25 Jul 2012 12:12:55 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <20120724165835.GB21023@onelab2.iet.unipi.it> <500FB409.7010207@redhat.com> <20120725095655.GC29334@onelab2.iet.unipi.it> In-Reply-To: <20120725095655.GC29334@onelab2.iet.unipi.it> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] interrupt mitigation for e1000 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Luigi Rizzo Cc: Avi Kivity , qemu-devel@nongnu.org Il 25/07/2012 11:56, Luigi Rizzo ha scritto: > On Wed, Jul 25, 2012 at 11:53:29AM +0300, Avi Kivity wrote: >> On 07/24/2012 07:58 PM, Luigi Rizzo wrote: >>> I noticed that the various NIC modules in qemu/kvm do not implement >>> interrupt mitigation, which is very beneficial as it dramatically >>> reduces exits from the hypervisor. >>> >>> As a proof of concept i tried to implement it for the e1000 driver >>> (patch below), and it brings tx performance from 9 to 56Kpps on >>> qemu-softmmu, and from ~20 to 140Kpps on qemu-kvm. >>> >>> I am going to measure the rx interrupt mitigation in the next couple >>> of days. >>> >>> Is there any interest in having this code in ? >> >> Indeed. But please drop the #ifdef MITIGATIONs. > > Thanks for the comments. The #ifdef block MITIGATION was only temporary to > point out the differences and run the performance comparisons. > Similarly, the magic thresholds below will be replaced with > appropriately commented #defines. > > Note: > On the real hardware interrupt mitigation is controlled by a total of four > registers (TIDV, TADV, RIDV, RADV) which control it with a granularity > of 1024ns , see > > http://www.intel.com/content/dam/doc/manual/pci-pci-x-family-gbe-controllers-software-dev-manual.pdf > > An exact emulation of the feature is hard, because the timer resolution we > have is much coarser (in the ms range). So i am inclined to use a different > approach, similar to the one i have implemented, namely: > - the first few packets (whether 1 or 4 or 5 will be decided on the host) > report an interrupt immediately; > - subsequent interrupts are delayed through qemu_bh_schedule_idle() qemu_bh_schedule_idle() is really a 10ms timer. Paolo