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From: Richard Henderson <rth@twiddle.net>
To: Yeongkyoon Lee <yeongkyoon.lee@samsung.com>
Cc: blauwirbel@gmail.com, sw@weilnetz.de,
	laurent.desnogues@gmail.com, qemu-devel@nongnu.org,
	peter.maydell@linaro.org
Subject: Re: [Qemu-devel] [RFC][PATCH v4 3/3] tcg: Optimize qemu_ld/st by generating slow paths at the end of a block
Date: Wed, 25 Jul 2012 07:00:00 -0700	[thread overview]
Message-ID: <500FFBE0.70700@twiddle.net> (raw)
In-Reply-To: <1343201734-12062-4-git-send-email-yeongkyoon.lee@samsung.com>

On 07/25/2012 12:35 AM, Yeongkyoon Lee wrote:
> +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
> +/* Macros/structures for qemu_ld/st IR code optimization:
> +   TCG_MAX_HELPER_LABELS is defined as same as OPC_BUF_SIZE in exec-all.h. */
> +#define TCG_MAX_QEMU_LDST       640

Why statically size this ...

> +    /* labels info for qemu_ld/st IRs
> +       The labels help to generate TLB miss case codes at the end of TB */
> +    TCGLabelQemuLdst *qemu_ldst_labels;

... and then allocate the array dynamically?

> +    /* jne slow_path */
> +    /* XXX: How to avoid using OPC_JCC_long for peephole optimization? */
> +    tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);

You can't, not and maintain the code-generate-until-address-reached
exception invariant.

> +#ifndef CONFIG_QEMU_LDST_OPTIMIZATION
>  uint8_t __ldb_mmu(target_ulong addr, int mmu_idx);
>  void __stb_mmu(target_ulong addr, uint8_t val, int mmu_idx);
>  uint16_t __ldw_mmu(target_ulong addr, int mmu_idx);
> @@ -28,6 +30,30 @@ void __stl_cmmu(target_ulong addr, uint32_t val, int mmu_idx);
>  uint64_t __ldq_cmmu(target_ulong addr, int mmu_idx);
>  void __stq_cmmu(target_ulong addr, uint64_t val, int mmu_idx);
>  #else
> +/* Extended versions of MMU helpers for qemu_ld/st optimization.
> +   The additional argument is a host code address accessing guest memory */
> +uint8_t ext_ldb_mmu(target_ulong addr, int mmu_idx, uintptr_t ra);

Don't tie LDST_OPTIMIZATION directly to the extended function calls.

For a host supporting predication, like ARM, the best code sequence
may look like

	(1) TLB check
	(2) If hit, load value from memory
	(3) If miss, call miss case (5)
	(4) ... next code
	...
	(5) Load call parameters
	(6) Tail call (aka jump) to MMU helper

so that (a) we need not explicitly load the address of (3) by hand
for your RA parameter and (b) the mmu helper returns directly to (4).


r~

  reply	other threads:[~2012-07-25 14:00 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-25  7:35 [Qemu-devel] [RFC][PATCH v4 0/3] tcg: enhance code generation quality for qemu_ld/st IRs Yeongkyoon Lee
2012-07-25  7:35 ` [Qemu-devel] [RFC][PATCH v4 1/3] configure: Add CONFIG_QEMU_LDST_OPTIMIZATION for TCG qemu_ld/st optimization Yeongkyoon Lee
2012-07-25  7:35 ` [Qemu-devel] [RFC][PATCH v4 2/3] tcg: Add declarations and templates of extended MMU helpers Yeongkyoon Lee
2012-07-25  7:35 ` [Qemu-devel] [RFC][PATCH v4 3/3] tcg: Optimize qemu_ld/st by generating slow paths at the end of a block Yeongkyoon Lee
2012-07-25 14:00   ` Richard Henderson [this message]
2012-07-28 15:39     ` Yeongkyoon Lee
2012-08-27  7:23       ` Yeongkyoon Lee
2012-08-27 18:24         ` Blue Swirl
2012-08-28  6:52           ` Yeongkyoon Lee
2012-08-28 16:58             ` Blue Swirl
2012-08-27 18:31         ` Peter Maydell
2012-08-28  6:38           ` Yeongkyoon Lee
2012-08-28 17:18           ` Andreas Färber

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