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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id c8sm4255701pjv.18.2021.02.23.10.24.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Feb 2021 10:24:56 -0800 (PST) Subject: Re: [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20210223081951.20226-1-frank.chang@sifive.com> From: Richard Henderson Message-ID: <500b1f4a-1fe8-9e4f-cdee-2c2b35a53edb@linaro.org> Date: Tue, 23 Feb 2021 10:24:54 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210223081951.20226-1-frank.chang@sifive.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/23/21 12:19 AM, frank.chang@sifive.com wrote: > From: Frank Chang > > TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in > commit: c445593, but other TB_FLAGS bits for rvv and rvh were > not shift as well so these bits may overlap with each other when > rvv is enabled. > > Signed-off-by: Frank Chang Reviewed-by: Richard Henderson > -#define TB_FLAGS_MMU_MASK 7 > #define TB_FLAGS_PRIV_MMU_MASK 3 > #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) > #define TB_FLAGS_MSTATUS_FS MSTATUS_FS ... > +FIELD(TB_FLAGS, MEM_IDX, 0, 3) > +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1) > +FIELD(TB_FLAGS, LMUL, 4, 2) > +FIELD(TB_FLAGS, SEW, 6, 3) > +FIELD(TB_FLAGS, VILL, 9, 1) > /* Is a Hypervisor instruction load/store allowed? */ > -FIELD(TB_FLAGS, HLSX, 9, 1) > +FIELD(TB_FLAGS, HLSX, 10, 1) The only other thing that I'd add at this point is a comment about MSTATUS_FS -- a 2-bit field at bit 13 -- for the benefit of the next person that adds something to TB_FLAGS. r~