From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59182) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SyjQL-0002rm-7a for qemu-devel@nongnu.org; Tue, 07 Aug 2012 09:02:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SyjQB-0001XR-1L for qemu-devel@nongnu.org; Tue, 07 Aug 2012 09:02:13 -0400 Received: from mx1.redhat.com ([209.132.183.28]:25509) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SyjQA-0001Wq-QX for qemu-devel@nongnu.org; Tue, 07 Aug 2012 09:02:02 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q77D21c8013965 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Tue, 7 Aug 2012 09:02:01 -0400 Message-ID: <50211212.5020909@redhat.com> Date: Tue, 07 Aug 2012 15:03:14 +0200 From: Laszlo Ersek MIME-Version: 1.0 References: <20120807125203.GC3341@redhat.com> In-Reply-To: <20120807125203.GC3341@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] reset PMBA and PMREGMISC PIIX4 registers. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gleb Natapov Cc: qemu-devel@nongnu.org On 08/07/12 14:52, Gleb Natapov wrote: > The bug causes Windows + OVMF hang after reboot since OVMF > checks PMREGMISC to see if IO space is enabled and skip > configuration if it is. > > Signed-off-by: Gleb Natapov > diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c > index 0aace60..90b46b5 100644 > --- a/hw/acpi_piix4.c > +++ b/hw/acpi_piix4.c > @@ -353,6 +353,9 @@ static void piix4_reset(void *opaque) > pci_conf[0x5a] = 0; > pci_conf[0x5b] = 0; > > + pci_conf[0x40] = 0x01; /* PM io base read only bit */ > + pci_conf[0x80] = 0; > + > if (s->kvm_enabled) { > /* Mark SMM as already inited (until KVM supports SMM). */ > pci_conf[0x5B] = 0x02; > @@ -392,8 +395,6 @@ static int piix4_pm_initfn(PCIDevice *dev) > pci_conf[0x09] = 0x00; > pci_conf[0x3d] = 0x01; // interrupt pin 1 > > - pci_conf[0x40] = 0x01; /* PM io base read only bit */ > - > /* APM */ > apm_init(&s->apm, apm_ctrl_changed, s); > > -- > Gleb. Unless I'm missing something, the patch keeps the "PM io base read only bit" set-up correctly the first time around too, since piix4_pm_initfn() qemu_register_reset(piix4_reset, ...); main() qemu_system_reset() FWIW, Reviewed-by: Laszlo Ersek Thanks! Laszlo