From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:44342) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3lTZ-0002YL-RD for qemu-devel@nongnu.org; Tue, 21 Aug 2012 06:14:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T3lTX-0007Es-TO for qemu-devel@nongnu.org; Tue, 21 Aug 2012 06:14:21 -0400 Received: from cantor2.suse.de ([195.135.220.15]:35879 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3lTX-0007Eh-Mp for qemu-devel@nongnu.org; Tue, 21 Aug 2012 06:14:19 -0400 Message-ID: <50335F77.4020900@suse.de> Date: Tue, 21 Aug 2012 12:14:15 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1345506102-8444-1-git-send-email-meadori@codesourcery.com> In-Reply-To: <1345506102-8444-1-git-send-email-meadori@codesourcery.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] target-mips: Enable access to required RDHWR hardware registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Meador Inge Cc: qemu-devel@nongnu.org, aurelien@aurel32.net Am 21.08.2012 01:41, schrieb Meador Inge: > While running in the usermode emulator all of the MIPS32r2 *required* > RDHWR hardware registers should be accessible (the Linux kernel enables > access to these same registers). >=20 > Signed-off-by: Meador Inge > --- > target-mips/translate.c | 7 +++++-- > 1 files changed, 5 insertions(+), 2 deletions(-) >=20 > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 47daf85..849e75d 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -12768,8 +12768,11 @@ void cpu_state_reset(CPUMIPSState *env) > =20 > #if defined(CONFIG_USER_ONLY) > env->hflags =3D MIPS_HFLAG_UM; > - /* Enable access to the SYNCI_Step register. */ > - env->CP0_HWREna |=3D (1 << 1); > + if (env->insn_flags & ISA_MIPS32R2) { > + /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHW= R > + hardware registers. */ > + env->CP0_HWREna |=3D 0x0000000F; > + } So what about the non-MIPS32r2 case? IIUC then the SYNCI_Step register would no longer be accessible, which your commit message does not mention. Intentional? If this is a bugfix for v1.2.0 don't forget to mark "for-1.2". Andreas > if (env->CP0_Config1 & (1 << CP0C1_FP)) { > env->hflags |=3D MIPS_HFLAG_FPU; > } >=20 --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg