From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39952) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3qaa-0006RU-IM for qemu-devel@nongnu.org; Tue, 21 Aug 2012 11:42:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T3qaX-0005sF-Qg for qemu-devel@nongnu.org; Tue, 21 Aug 2012 11:41:56 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:64825) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3qaX-0005sB-LE for qemu-devel@nongnu.org; Tue, 21 Aug 2012 11:41:53 -0400 Message-ID: <5033AC3D.2020302@codesourcery.com> Date: Tue, 21 Aug 2012 10:41:49 -0500 From: Meador Inge MIME-Version: 1.0 References: <1345506102-8444-1-git-send-email-meadori@codesourcery.com> <50335F77.4020900@suse.de> In-Reply-To: <50335F77.4020900@suse.de> Content-Type: text/plain; charset="ISO-8859-15" Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH] target-mips: Enable access to required RDHWR hardware registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-15?Q?Andreas_F=E4rber?= Cc: qemu-devel@nongnu.org, aurelien@aurel32.net On 08/21/2012 05:14 AM, Andreas Färber wrote: > Am 21.08.2012 01:41, schrieb Meador Inge: >> While running in the usermode emulator all of the MIPS32r2 *required* >> RDHWR hardware registers should be accessible (the Linux kernel enables >> access to these same registers). >> >> Signed-off-by: Meador Inge >> --- >> target-mips/translate.c | 7 +++++-- >> 1 files changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/target-mips/translate.c b/target-mips/translate.c >> index 47daf85..849e75d 100644 >> --- a/target-mips/translate.c >> +++ b/target-mips/translate.c >> @@ -12768,8 +12768,11 @@ void cpu_state_reset(CPUMIPSState *env) >> >> #if defined(CONFIG_USER_ONLY) >> env->hflags = MIPS_HFLAG_UM; >> - /* Enable access to the SYNCI_Step register. */ >> - env->CP0_HWREna |= (1 << 1); >> + if (env->insn_flags & ISA_MIPS32R2) { >> + /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR >> + hardware registers. */ >> + env->CP0_HWREna |= 0x0000000F; >> + } > > So what about the non-MIPS32r2 case? IIUC then the SYNCI_Step register > would no longer be accessible, which your commit message does not > mention. Intentional? Yes, that is intentional. In Section 9.13 of [1] it is stated that these registers are only required starting at release 2 of the architecture. The Linux kernel follows the same approach. I guess I should just split this into two minor patches: (1) for enabling all the registers and (2) for making them conditional on R2. [1] MIPS® Architecture For Programmers, Volume III: The MIPS32 (R) and microMIPS32TM Privileged Resource Architecture Revision 3.12 > If this is a bugfix for v1.2.0 don't forget to mark "for-1.2". Will do. Thanks for the review. -- Meador Inge CodeSourcery / Mentor Embedded http://www.mentor.com/embedded-software