From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38272) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3qlM-0004Lt-Gy for qemu-devel@nongnu.org; Tue, 21 Aug 2012 11:53:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T3qlF-0000kE-Uh for qemu-devel@nongnu.org; Tue, 21 Aug 2012 11:53:04 -0400 Received: from hall.aurel32.net ([88.191.126.93]:51358) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T3qlF-0000iU-O7 for qemu-devel@nongnu.org; Tue, 21 Aug 2012 11:52:57 -0400 Message-ID: <5033AEC8.6050006@aurel32.net> Date: Tue, 21 Aug 2012 17:52:40 +0200 From: Aurelien Jarno MIME-Version: 1.0 References: <1345506102-8444-1-git-send-email-meadori@codesourcery.com> <50335F77.4020900@suse.de> <5033AC3D.2020302@codesourcery.com> In-Reply-To: <5033AC3D.2020302@codesourcery.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH] target-mips: Enable access to required RDHWR hardware registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Meador Inge Cc: =?ISO-8859-15?Q?Andreas_F=E4rber?= , qemu-devel@nongnu.org Le 21/08/2012 17:41, Meador Inge a écrit : > On 08/21/2012 05:14 AM, Andreas Färber wrote: > >> Am 21.08.2012 01:41, schrieb Meador Inge: >>> While running in the usermode emulator all of the MIPS32r2 *required* >>> RDHWR hardware registers should be accessible (the Linux kernel enables >>> access to these same registers). >>> >>> Signed-off-by: Meador Inge >>> --- >>> target-mips/translate.c | 7 +++++-- >>> 1 files changed, 5 insertions(+), 2 deletions(-) >>> >>> diff --git a/target-mips/translate.c b/target-mips/translate.c >>> index 47daf85..849e75d 100644 >>> --- a/target-mips/translate.c >>> +++ b/target-mips/translate.c >>> @@ -12768,8 +12768,11 @@ void cpu_state_reset(CPUMIPSState *env) >>> >>> #if defined(CONFIG_USER_ONLY) >>> env->hflags = MIPS_HFLAG_UM; >>> - /* Enable access to the SYNCI_Step register. */ >>> - env->CP0_HWREna |= (1 << 1); >>> + if (env->insn_flags & ISA_MIPS32R2) { >>> + /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR >>> + hardware registers. */ >>> + env->CP0_HWREna |= 0x0000000F; >>> + } >> >> So what about the non-MIPS32r2 case? IIUC then the SYNCI_Step register >> would no longer be accessible, which your commit message does not >> mention. Intentional? > > Yes, that is intentional. In Section 9.13 of [1] it is stated that these > registers are only required starting at release 2 of the architecture. The > Linux kernel follows the same approach. Remember this is linux user mode, as such you should not look at the MIPS architecture, but rather at the behavour of MIPS architecture + Linux kernel. SYNCI_Step is emulated by the Linux kernel for non R2 CPUs, as such it should be available even for non R2 CPUs *in user mode only*. At a first glance, it seems to be the same for CPUNum, CC and CCRes, but someone has to check that more in details. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net