From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:32921) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T5ZH2-0004zY-R9 for qemu-devel@nongnu.org; Sun, 26 Aug 2012 05:36:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T5ZGz-0001Sr-De for qemu-devel@nongnu.org; Sun, 26 Aug 2012 05:36:52 -0400 Received: from mout.web.de ([212.227.15.3]:51720) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T5ZGz-0001Sk-0A for qemu-devel@nongnu.org; Sun, 26 Aug 2012 05:36:49 -0400 Message-ID: <5039EE2A.2040603@web.de> Date: Sun, 26 Aug 2012 11:36:42 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <1fa099f2f1c404e8b562a2ad32a39a784c68be1c.1345549695.git.julien.grall@citrix.com> <5039E7F3.1040106@web.de> In-Reply-To: <5039E7F3.1040106@web.de> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enigBF64D400440666AF05272B49" Subject: Re: [Qemu-devel] [PATCH V5 2/8] hw/acpi_piix4.c: replace register_ioport* List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Julien Grall Cc: avi@redhat.com, qemu-devel@nongnu.org, Stefano.Stabellini@eu.citrix.com This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enigBF64D400440666AF05272B49 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable On 2012-08-26 11:10, Jan Kiszka wrote: > On 2012-08-22 14:27, Julien Grall wrote: >> This patch replaces all register_ioport* with the new memory API. It p= ermits >> to use the new Memory stuff like listener. >> >> Signed-off-by: Julien Grall >> --- >> hw/acpi_piix4.c | 160 ++++++++++++++++++++++++++++++++++++++++++----= -------- >> 1 files changed, 124 insertions(+), 36 deletions(-) >> >> diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c >> index 0aace60..26d5559 100644 >> --- a/hw/acpi_piix4.c >> +++ b/hw/acpi_piix4.c >> @@ -28,6 +28,7 @@ >> #include "range.h" >> #include "ioport.h" >> #include "fw_cfg.h" >> +#include "exec-memory.h" >> =20 >> //#define DEBUG >> =20 >> @@ -41,8 +42,7 @@ >> =20 >> #define GPE_BASE 0xafe0 >> #define GPE_LEN 4 >> -#define PCI_UP_BASE 0xae00 >> -#define PCI_DOWN_BASE 0xae04 >> +#define PCI_BASE 0xaa00 >> #define PCI_EJ_BASE 0xae08 >> #define PCI_RMV_BASE 0xae0c >> =20 >> @@ -55,7 +55,7 @@ struct pci_status { >> =20 >> typedef struct PIIX4PMState { >> PCIDevice dev; >> - IORange ioport; >> + MemoryRegion pm_io; >> ACPIREGS ar; >> =20 >> APMState apm; >> @@ -63,6 +63,13 @@ typedef struct PIIX4PMState { >> PMSMBus smb; >> uint32_t smb_io_base; >> =20 >> + MemoryRegion smb_io; >> + MemoryRegion acpi_io; >> + MemoryRegion acpi_hot_io; >> + PortioList pci_hot_port_list; >> + MemoryRegion pciej_hot_io; >> + MemoryRegion pcirmv_hot_io; >> + >> qemu_irq irq; >> qemu_irq smi_irq; >> int kvm_enabled; >> @@ -108,12 +115,12 @@ static void pm_tmr_timer(ACPIREGS *ar) >> pm_update_sci(s); >> } >> =20 >> -static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned = width, >> - uint64_t val) >> +static void pm_ioport_write(void *opaque, target_phys_addr_t addr, >> + uint64_t val, unsigned size) >> { >> - PIIX4PMState *s =3D container_of(ioport, PIIX4PMState, ioport); >> + PIIX4PMState *s =3D opaque; >> =20 >> - if (width !=3D 2) { >> + if (size !=3D 2) { >> PIIX4_DPRINTF("PM write port=3D0x%04x width=3D%d val=3D0x%08x= \n", >> (unsigned)addr, width, (unsigned)val); >> } >> @@ -137,11 +144,11 @@ static void pm_ioport_write(IORange *ioport, uin= t64_t addr, unsigned width, >> (unsigned int)val); >> } >> =20 >> -static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned w= idth, >> - uint64_t *data) >> +static uint64_t pm_ioport_read(void *opaque, target_phys_addr_t addr,= >> + unsigned size) >> { >> - PIIX4PMState *s =3D container_of(ioport, PIIX4PMState, ioport); >> - uint32_t val; >> + PIIX4PMState *s =3D opaque; >> + uint64_t val; >> =20 >> switch(addr) { >> case 0x00: >> @@ -161,12 +168,18 @@ static void pm_ioport_read(IORange *ioport, uint= 64_t addr, unsigned width, >> break; >> } >> PIIX4_DPRINTF("PM readw port=3D0x%04x val=3D0x%04x\n", (unsigned = int)addr, val); >> - *data =3D val; >> + >> + return val; >> } >> =20 >> -static const IORangeOps pm_iorange_ops =3D { >> +static const MemoryRegionOps pm_io_ops =3D { >> .read =3D pm_ioport_read, >> .write =3D pm_ioport_write, >> + .endianness =3D DEVICE_NATIVE_ENDIAN, >> + .impl =3D { >> + .min_access_size =3D 2, >> + .max_access_size =3D 2, >> + }, >> }; >> =20 >> static void apm_ctrl_changed(uint32_t val, void *arg) >> @@ -183,7 +196,8 @@ static void apm_ctrl_changed(uint32_t val, void *a= rg) >> } >> } >> =20 >> -static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val= ) >> +static void acpi_dbg_writel(void *opaque, target_phys_addr_t addr, >> + uint64_t val, unsigned size) >> { >> PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val); >> } >> @@ -198,8 +212,10 @@ static void pm_io_space_update(PIIX4PMState *s) >> =20 >> /* XXX: need to improve memory and ioport allocation */ >> PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base); >> - iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64); >> - ioport_register(&s->ioport); >> + >> + memory_region_init_io(&s->pm_io, &pm_io_ops, s, "piix4-pm", 6= 4); >> + memory_region_add_subregion(pci_address_space_io(&s->dev), >> + pm_io_base, &s->pm_io); >> } >> } >> =20 >> @@ -381,6 +397,25 @@ static void piix4_pm_machine_ready(Notifier *n, v= oid *opaque) >> =20 >> } >> =20 >> +static const MemoryRegionOps smb_io_ops =3D { >> + .read =3D smb_ioport_readb, >> + .write =3D smb_ioport_writeb, >> + .endianness =3D DEVICE_NATIVE_ENDIAN, >> + .impl =3D { >> + .min_access_size =3D 1, >> + .max_access_size =3D 1, >> + }, >> +}; >> + >> +static const MemoryRegionOps acpi_io_ops =3D { >> + .write =3D acpi_dbg_writel, >> + .endianness =3D DEVICE_NATIVE_ENDIAN, >> + .impl =3D { >> + .min_access_size =3D 4, >> + .max_access_size =3D 4, >> + }, >> +}; >> + >> static int piix4_pm_initfn(PCIDevice *dev) >> { >> PIIX4PMState *s =3D DO_UPCAST(PIIX4PMState, dev, dev); >> @@ -395,9 +430,11 @@ static int piix4_pm_initfn(PCIDevice *dev) >> pci_conf[0x40] =3D 0x01; /* PM io base read only bit */ >> =20 >> /* APM */ >> - apm_init(&s->apm, apm_ctrl_changed, s); >> + apm_init(dev, &s->apm, apm_ctrl_changed, s); >> =20 >> - register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s)= ; >> + memory_region_init_io(&s->acpi_io, &acpi_io_ops, s, "piix4-acpi",= 4); >> + memory_region_add_subregion(pci_address_space_io(dev), ACPI_DBG_I= O_ADDR, >> + &s->acpi_io); >> =20 >> if (s->kvm_enabled) { >> /* Mark SMM as already inited to prevent SMM from running. K= VM does not >> @@ -410,8 +447,10 @@ static int piix4_pm_initfn(PCIDevice *dev) >> pci_conf[0x90] =3D s->smb_io_base | 1; >> pci_conf[0x91] =3D s->smb_io_base >> 8; >> pci_conf[0xd2] =3D 0x09; >> - register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &= s->smb); >> - register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s-= >smb); >> + >> + memory_region_init_io(&s->smb_io, &smb_io_ops, &s->smb, "piix4-sm= b", 64); >> + memory_region_add_subregion(pci_address_space_io(dev), s->smb_io_= base, >> + &s->smb_io); >> =20 >> acpi_pm_tmr_init(&s->ar, pm_tmr_timer); >> acpi_gpe_init(&s->ar, GPE_LEN); >> @@ -496,16 +535,17 @@ static void piix4_pm_register_types(void) >> =20 >> type_init(piix4_pm_register_types) >> =20 >> -static uint32_t gpe_readb(void *opaque, uint32_t addr) >> +static uint64_t gpe_readb(void *opaque, target_phys_addr_t addr, unsi= gned size) >> { >> PIIX4PMState *s =3D opaque; >> - uint32_t val =3D acpi_gpe_ioport_readb(&s->ar, addr); >> + uint64_t val =3D acpi_gpe_ioport_readb(&s->ar, addr); >> =20 >> PIIX4_DPRINTF("gpe read %x =3D=3D %x\n", addr, val); >> return val; >> } >> =20 >> -static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) >> +static void gpe_writeb(void *opaque, target_phys_addr_t addr, uint64_= t val, >> + unsigned size) >> { >> PIIX4PMState *s =3D opaque; >> =20 >> @@ -537,21 +577,24 @@ static uint32_t pci_down_read(void *opaque, uint= 32_t addr) >> return val; >> } >> =20 >> -static uint32_t pci_features_read(void *opaque, uint32_t addr) >> +static uint64_t pci_features_read(void *opaque, target_phys_addr_t ad= dr, >> + unsigned size) >> { >> /* No feature defined yet */ >> PIIX4_DPRINTF("pci_features_read %x\n", 0); >> return 0; >> } >> =20 >> -static void pciej_write(void *opaque, uint32_t addr, uint32_t val) >> +static void pciej_write(void *opaque, target_phys_addr_t addr, uint64= _t val, >> + unsigned size) >> { >> acpi_piix_eject_slot(opaque, val); >> =20 >> PIIX4_DPRINTF("pciej write %x <=3D=3D %d\n", addr, val); >> } >> =20 >> -static uint32_t pcirmv_read(void *opaque, uint32_t addr) >> +static uint64_t pcirmv_read(void *opaque, target_phys_addr_t addr, >> + unsigned size) >> { >> PIIX4PMState *s =3D opaque; >> =20 >> @@ -561,20 +604,65 @@ static uint32_t pcirmv_read(void *opaque, uint32= _t addr) >> static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, >> PCIHotplugState state); >> =20 >> -static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState = *s) >> -{ >> +static const MemoryRegionOps acpi_hot_io_ops =3D { >> + .read =3D gpe_readb, >> + .write =3D gpe_writeb, >> + .endianness =3D DEVICE_NATIVE_ENDIAN, >> + .impl =3D { >> + .min_access_size =3D 1, >> + .max_access_size =3D 1, >> + }, >> +}; >> + >> +/* PCI hot plug registers */ >> +static const MemoryRegionPortio pci_hot_portio_list[] =3D { >> + { 0x00, 4, 4, .read =3D pci_up_read, }, /* 0xae00 */ >> + { 0x04, 4, 4, .read =3D pci_down_read, }, /* 0xae04 */ >> + PORTIO_END_OF_LIST(), >> +}; >> =20 >> - register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s); >> - register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s); >> - acpi_gpe_blk(&s->ar, GPE_BASE); >> +static const MemoryRegionOps pciej_hot_io_ops =3D { >> + .read =3D pci_features_read, >> + .write =3D pciej_write, >> + .endianness =3D DEVICE_NATIVE_ENDIAN, >> + .impl =3D { >> + .min_access_size =3D 4, >> + .max_access_size =3D 4, >> + }, >> +}; >> =20 >> - register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s); >> - register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s); >> +static const MemoryRegionOps pcirmv_hot_io_ops =3D { >> + .read =3D pcirmv_read, >> + .endianness =3D DEVICE_NATIVE_ENDIAN, >> + .impl =3D { >> + .min_access_size =3D 4, >> + .max_access_size =3D 4, >> + }, >> +}; >> =20 >> - register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s); >> - register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s); >> +static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState = *s) >> +{ >> =20 >> - register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); >> + memory_region_init_io(&s->acpi_hot_io, &acpi_hot_io_ops, s, >> + "piix4-acpi-hot", GPE_LEN); >> + memory_region_add_subregion(pci_address_space_io(&s->dev), GPE_BA= SE, >> + &s->acpi_hot_io); >> + acpi_gpe_blk(&s->ar, 0); >> + >> + portio_list_init(&s->pci_hot_port_list, pci_hot_portio_list, s, >> + "piix4-pci-hot"); >> + portio_list_add(&s->pci_hot_port_list, pci_address_space_io(&s->d= ev), >> + PCI_BASE); >> + >> + memory_region_init_io(&s->pciej_hot_io, &pciej_hot_io_ops, s, >> + "piix4-pciej-hot", 4); >> + memory_region_add_subregion(pci_address_space_io(&s->dev), PCI_EJ= _BASE, >> + &s->pciej_hot_io); >> + >> + memory_region_init_io(&s->pcirmv_hot_io, &pcirmv_hot_io_ops, s, >> + "piix4-pcirmv-hot", 4); >> + memory_region_add_subregion(pci_address_space_io(&s->dev), PCI_RM= V_BASE, >> + &s->pcirmv_hot_io); >> =20 >> pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); >> } >> >=20 > This patch doesn't build without patch 8 and then still generates warni= ngs. Sorry, it depends on patches 7 & 8. Then the warnings are gone as well. Anyway, every patch has to build and work on its own. Jan --------------enigBF64D400440666AF05272B49 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.16 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://www.enigmail.net/ iEYEARECAAYFAlA57ioACgkQitSsb3rl5xRAbACgnbpbY/u9QsmNATPjeJ95GFuH BUkAn0MYdTxv/Rklv/eO3t8JYy8m7Uj3 =aGfg -----END PGP SIGNATURE----- --------------enigBF64D400440666AF05272B49--