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Date: Mon, 03 Sep 2012 11:34:49 +0200
From: Paolo Bonzini <pbonzini@redhat.com>
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Subject: Re: [Qemu-devel] [PATCH v4 5/5] i8259: fix dynamically masking
 slave IRQs with IMR register
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To: Jan Kiszka <jan.kiszka@web.de>
Cc: Richard Henderson <rth@twiddle.net>, Matthew Ogilvie <mmogilvi_qemu@miniinfo.net>, qemu-devel@nongnu.org

Il 03/09/2012 10:51, Jan Kiszka ha scritto:
> The only thing that worries me is that we just consider the PC so far
> while the i8259 is also used on different architectures (PPC, MIPS, Alpha?).

Why is this a problem?  All of them use IRQ2 for a cascade, and initialize
icw3 to 0x4/0x2 (I checked OpenBIOS, rth's palcode for Alpha, and Linux).

BTW, from the palcode it looks like Alpha wants LTIM=1, so it would be nice
to implement that one as well:

  /* ??? MILO initializes the PIC as edge triggered; I do not know how SRM
     initializes them.  However, Linux seems to expect that these are level
     triggered.  That may be a kernel bug, but level triggers are more
     reliable anyway so lets go with that.  */

  /* Initialize level triggers.  The CY82C693UB that's on real alpha
     hardware doesn't have this; this is a PIIX extension.  However,
     QEMU doesn't implement regular level triggers.  */
  outb(0xff, PORT_PIC2_ELCR);
  outb(0xff, PORT_PIC1_ELCR);

Paolo