From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39243) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T8nVB-0001vH-Rk for qemu-devel@nongnu.org; Tue, 04 Sep 2012 03:24:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T8nVA-0000I7-Cg for qemu-devel@nongnu.org; Tue, 04 Sep 2012 03:24:49 -0400 Received: from mout.web.de ([212.227.15.4]:50796) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T8nVA-0000I1-2i for qemu-devel@nongnu.org; Tue, 04 Sep 2012 03:24:48 -0400 Message-ID: <5045ACB5.40106@web.de> Date: Tue, 04 Sep 2012 09:24:37 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <7f5a672e348b8f917dcc92c67e2ae5f7ce75ea60.1346665074.git.julien.grall@citrix.com> In-Reply-To: <7f5a672e348b8f917dcc92c67e2ae5f7ce75ea60.1346665074.git.julien.grall@citrix.com> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig41ADA93D8F6AAE7212C0841B" Subject: Re: [Qemu-devel] [PATCH V7 4/8] hw/acpi_piix4.c: replace register_ioport* List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Julien Grall Cc: qemu-devel@nongnu.org, Stefano Stabellini , avi@redhat.com, afaerber@suse.de, kraxel@redhat.com This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig41ADA93D8F6AAE7212C0841B Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable On 2012-09-03 12:03, Julien Grall wrote: > This patch replaces all register_ioport* with the new memory API. It pe= rmits > to use the new Memory stuff like listener. >=20 > Signed-off-by: Julien Grall > --- > hw/acpi_piix4.c | 151 +++++++++++++++++++++++++++++++++++++++++++----= -------- > 1 files changed, 119 insertions(+), 32 deletions(-) >=20 > diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c > index 1ad45ce..527dfc1 100644 > --- a/hw/acpi_piix4.c > +++ b/hw/acpi_piix4.c > @@ -41,8 +41,7 @@ > =20 > #define GPE_BASE 0xafe0 > #define GPE_LEN 4 > -#define PCI_UP_BASE 0xae00 > -#define PCI_DOWN_BASE 0xae04 > +#define PCI_BASE 0xae00 > #define PCI_EJ_BASE 0xae08 > #define PCI_RMV_BASE 0xae0c > =20 > @@ -55,7 +54,8 @@ struct pci_status { > =20 > typedef struct PIIX4PMState { > PCIDevice dev; > - IORange ioport; > + MemoryRegion pm_io; > + uint32_t pm_io_base; > ACPIREGS ar; > =20 > APMState apm; > @@ -64,6 +64,11 @@ typedef struct PIIX4PMState { > uint32_t smb_io_base; > =20 > MemoryRegion smb_io; > + MemoryRegion acpi_io; > + MemoryRegion acpi_hot_io; > + PortioList pci_hot_port_list; > + MemoryRegion pciej_hot_io; > + MemoryRegion pcirmv_hot_io; > =20 > qemu_irq irq; > qemu_irq smi_irq; > @@ -110,10 +115,10 @@ static void pm_tmr_timer(ACPIREGS *ar) > pm_update_sci(s); > } > =20 > -static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned w= idth, > - uint64_t val) > +static void pm_ioport_write(void *opaque, target_phys_addr_t addr, > + uint64_t val, unsigned width) > { > - PIIX4PMState *s =3D container_of(ioport, PIIX4PMState, ioport); > + PIIX4PMState *s =3D opaque; > =20 > if (width !=3D 2) { > PIIX4_DPRINTF("PM write port=3D0x%04x width=3D%d val=3D0x%08x\= n", > @@ -139,11 +144,11 @@ static void pm_ioport_write(IORange *ioport, uint= 64_t addr, unsigned width, > (unsigned int)val); > } > =20 > -static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned wi= dth, > - uint64_t *data) > +static uint64_t pm_ioport_read(void *opaque, target_phys_addr_t addr, > + unsigned width) > { > - PIIX4PMState *s =3D container_of(ioport, PIIX4PMState, ioport); > - uint32_t val; > + PIIX4PMState *s =3D opaque; > + uint64_t val; > =20 > switch(addr) { > case 0x00: > @@ -163,12 +168,18 @@ static void pm_ioport_read(IORange *ioport, uint6= 4_t addr, unsigned width, > break; > } > PIIX4_DPRINTF("PM readw port=3D0x%04x val=3D0x%04x\n", (unsigned i= nt)addr, val); > - *data =3D val; > + > + return val; > } > =20 > -static const IORangeOps pm_iorange_ops =3D { > +static const MemoryRegionOps pm_io_ops =3D { > .read =3D pm_ioport_read, > .write =3D pm_ioport_write, > + .endianness =3D DEVICE_LITTLE_ENDIAN, > + .impl =3D { > + .min_access_size =3D 2, > + .max_access_size =3D 2, > + }, > }; > =20 > static void apm_ctrl_changed(uint32_t val, void *arg) > @@ -185,7 +196,8 @@ static void apm_ctrl_changed(uint32_t val, void *ar= g) > } > } > =20 > -static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)= > +static void acpi_dbg_writel(void *opaque, target_phys_addr_t addr, > + uint64_t val, unsigned size) > { > PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val); > } > @@ -200,8 +212,18 @@ static void pm_io_space_update(PIIX4PMState *s) > =20 > /* XXX: need to improve memory and ioport allocation */ > PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base); > - iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64); > - ioport_register(&s->ioport); > + > + if (!s->pm_io_base) { > + memory_region_add_subregion(pci_address_space_io(&s->dev),= > + pm_io_base, &s->pm_io); This doesn't work reliably. Add the region in a disabled state (ie. the default) during init, only toggle enable and update the base here. Jan PS: Series now builds cleanly here. --------------enig41ADA93D8F6AAE7212C0841B Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.16 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://www.enigmail.net/ iEYEARECAAYFAlBFrLkACgkQitSsb3rl5xTD7QCgwaDuqA+9cIwWXOemMMIDp5lB D1wAn34RBLVzRj38jx4tCdxklqhqZOcc =i/kp -----END PGP SIGNATURE----- --------------enig41ADA93D8F6AAE7212C0841B--