* [Qemu-devel] [PATCH 01/21] target-s390x: fix style
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-03 4:31 ` Alexander Graf
2012-09-06 18:33 ` Alexander Graf
2012-09-02 17:33 ` [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops Blue Swirl
` (20 subsequent siblings)
21 siblings, 2 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Before splitting op_helper.c and helper.c in the next patches,
fix style issues. No functional changes.
Replace also GCC specific __FUNCTION__ with
standard __func__.
Don't init static variable (cpu_s390x_init:inited) with 0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
target-s390x/helper.c | 96 +++++-----
target-s390x/op_helper.c | 438 ++++++++++++++++++++++++++--------------------
2 files changed, 297 insertions(+), 237 deletions(-)
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index d0a1180..d98e6d9 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -74,7 +74,7 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
{
S390CPU *cpu;
CPUS390XState *env;
- static int inited = 0;
+ static int inited;
cpu = S390_CPU(object_new(TYPE_S390_CPU));
env = &cpu->env;
@@ -91,25 +91,27 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUS390XState *env)
+void do_interrupt(CPUS390XState *env)
{
env->exception_index = -1;
}
-int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
- int mmu_idx)
+int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
+ int rw, int mmu_idx)
{
- /* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d\n",
- __FUNCTION__, address, rw, mmu_idx); */
+ /* fprintf(stderr, "%s: address 0x%lx rw %d mmu_idx %d\n",
+ __func__, address, rw, mmu_idx); */
env->exception_index = EXCP_ADDR;
- env->__excp_addr = address; /* FIXME: find out how this works on a real machine */
+ /* FIXME: find out how this works on a real machine */
+ env->__excp_addr = address;
return 1;
}
#else /* !CONFIG_USER_ONLY */
/* Ensure to exit the TB after this call! */
-static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilc)
+static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
+ uint32_t ilc)
{
env->exception_index = EXCP_PGM;
env->int_pgm_code = code;
@@ -138,19 +140,20 @@ static int trans_bits(CPUS390XState *env, uint64_t mode)
return bits;
}
-static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, uint64_t mode)
+static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
+ uint64_t mode)
{
int ilc = ILC_LATER_INC_2;
int bits = trans_bits(env, mode) | 4;
- DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
+ DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
trigger_pgm_exception(env, PGM_PROTECTION, ilc);
}
-static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type,
- uint64_t asc, int rw)
+static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
+ uint32_t type, uint64_t asc, int rw)
{
int ilc = ILC_LATER;
int bits = trans_bits(env, asc);
@@ -160,26 +163,26 @@ static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t
ilc = 2;
}
- DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
+ DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
trigger_pgm_exception(env, type, ilc);
}
-static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
- uint64_t asce, int level, target_ulong *raddr,
- int *flags, int rw)
+static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
+ uint64_t asc, uint64_t asce, int level,
+ target_ulong *raddr, int *flags, int rw)
{
uint64_t offs = 0;
uint64_t origin;
uint64_t new_asce;
- PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __FUNCTION__, asce);
+ PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);
if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
/* XXX different regions have different faults */
- DPRINTF("%s: invalid region\n", __FUNCTION__);
+ DPRINTF("%s: invalid region\n", __func__);
trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
return -1;
}
@@ -222,7 +225,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t a
new_asce = ldq_phys(origin + offs);
PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
- __FUNCTION__, origin, offs, new_asce);
+ __func__, origin, offs, new_asce);
if (level != _ASCE_TYPE_SEGMENT) {
/* yet another region */
@@ -232,7 +235,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t a
/* PTE */
if (new_asce & _PAGE_INVALID) {
- DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __FUNCTION__, new_asce);
+ DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce);
trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
return -1;
}
@@ -243,13 +246,14 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t a
*raddr = new_asce & _ASCE_ORIGIN;
- PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __FUNCTION__, new_asce);
+ PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce);
return 0;
}
-static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
- target_ulong *raddr, int *flags, int rw)
+static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
+ uint64_t asc, target_ulong *raddr, int *flags,
+ int rw)
{
uint64_t asce = 0;
int level, new_level;
@@ -257,15 +261,15 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
switch (asc) {
case PSW_ASC_PRIMARY:
- PTE_DPRINTF("%s: asc=primary\n", __FUNCTION__);
+ PTE_DPRINTF("%s: asc=primary\n", __func__);
asce = env->cregs[1];
break;
case PSW_ASC_SECONDARY:
- PTE_DPRINTF("%s: asc=secondary\n", __FUNCTION__);
+ PTE_DPRINTF("%s: asc=secondary\n", __func__);
asce = env->cregs[7];
break;
case PSW_ASC_HOME:
- PTE_DPRINTF("%s: asc=home\n", __FUNCTION__);
+ PTE_DPRINTF("%s: asc=home\n", __func__);
asce = env->cregs[13];
break;
}
@@ -276,8 +280,7 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
case _ASCE_TYPE_REGION2:
if (vaddr & 0xffe0000000000000ULL) {
DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
- " 0xffe0000000000000ULL\n", __FUNCTION__,
- vaddr);
+ " 0xffe0000000000000ULL\n", __func__, vaddr);
trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
return -1;
}
@@ -285,8 +288,7 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
case _ASCE_TYPE_REGION3:
if (vaddr & 0xfffffc0000000000ULL) {
DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
- " 0xfffffc0000000000ULL\n", __FUNCTION__,
- vaddr);
+ " 0xfffffc0000000000ULL\n", __func__, vaddr);
trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
return -1;
}
@@ -294,8 +296,7 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
case _ASCE_TYPE_SEGMENT:
if (vaddr & 0xffffffff80000000ULL) {
DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
- " 0xffffffff80000000ULL\n", __FUNCTION__,
- vaddr);
+ " 0xffffffff80000000ULL\n", __func__, vaddr);
trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
return -1;
}
@@ -358,7 +359,7 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
break;
}
-out:
+ out:
/* Convert real address -> absolute address */
if (*raddr < 0x2000) {
*raddr = *raddr + env->psa;
@@ -378,18 +379,18 @@ out:
return r;
}
-int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong _vaddr, int rw,
- int mmu_idx)
+int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
+ int rw, int mmu_idx)
{
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
target_ulong vaddr, raddr;
int prot;
DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
- __FUNCTION__, _vaddr, rw, mmu_idx);
+ __func__, _vaddr, rw, mmu_idx);
- _vaddr &= TARGET_PAGE_MASK;
- vaddr = _vaddr;
+ orig_vaddr &= TARGET_PAGE_MASK;
+ vaddr = orig_vaddr;
/* 31-Bit mode */
if (!(env->psw.mask & PSW_MASK_64)) {
@@ -403,22 +404,23 @@ int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong _vaddr, int rw,
/* check out of RAM access */
if (raddr > (ram_size + virtio_size)) {
- DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __FUNCTION__,
+ DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
(uint64_t)aaddr, (uint64_t)ram_size);
trigger_pgm_exception(env, PGM_ADDRESSING, ILC_LATER);
return 1;
}
- DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __FUNCTION__,
+ DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
(uint64_t)vaddr, (uint64_t)raddr, prot);
- tlb_set_page(env, _vaddr, raddr, prot,
+ tlb_set_page(env, orig_vaddr, raddr, prot,
mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env, target_ulong vaddr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env,
+ target_ulong vaddr)
{
target_ulong raddr;
int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -509,7 +511,7 @@ static void do_program_interrupt(CPUS390XState *env)
break;
}
- qemu_log("%s: code=0x%x ilc=%d\n", __FUNCTION__, env->int_pgm_code, ilc);
+ qemu_log("%s: code=0x%x ilc=%d\n", __func__, env->int_pgm_code, ilc);
lowcore = cpu_physical_memory_map(env->psa, &len, 1);
@@ -522,7 +524,7 @@ static void do_program_interrupt(CPUS390XState *env)
cpu_physical_memory_unmap(lowcore, len, 1, len);
- DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
+ DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
env->int_pgm_code, ilc, env->psw.mask,
env->psw.addr);
@@ -565,15 +567,15 @@ static void do_ext_interrupt(CPUS390XState *env)
env->pending_int &= ~INTERRUPT_EXT;
}
- DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
+ DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
env->psw.mask, env->psw.addr);
load_psw(env, mask, addr);
}
-void do_interrupt (CPUS390XState *env)
+void do_interrupt(CPUS390XState *env)
{
- qemu_log("%s: %d at pc=%" PRIx64 "\n", __FUNCTION__, env->exception_index,
+ qemu_log("%s: %d at pc=%" PRIx64 "\n", __func__, env->exception_index,
env->psw.addr);
s390_add_running_cpu(env);
diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
index abc35dd..195e93e 100644
--- a/target-s390x/op_helper.c
+++ b/target-s390x/op_helper.c
@@ -31,13 +31,13 @@
#include <linux/kvm.h>
#endif
-#if !defined (CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
#include "sysemu.h"
#endif
/*****************************************************************************/
/* Softmmu support */
-#if !defined (CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#define MMUSUFFIX _mmu
@@ -95,7 +95,7 @@ void tlb_fill(CPUS390XState *env1, target_ulong addr, int is_write, int mmu_idx,
/* raise an exception */
void HELPER(exception)(uint32_t excp)
{
- HELPER_LOG("%s: exception %d\n", __FUNCTION__, excp);
+ HELPER_LOG("%s: exception %d\n", __func__, excp);
env->exception_index = excp;
cpu_loop_exit(env);
}
@@ -164,7 +164,7 @@ uint32_t HELPER(nc)(uint32_t l, uint64_t dest, uint64_t src)
uint32_t cc = 0;
HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
- __FUNCTION__, l, dest, src);
+ __func__, l, dest, src);
for (i = 0; i <= l; i++) {
x = ldub(dest + i) & ldub(src + i);
if (x) {
@@ -183,7 +183,7 @@ uint32_t HELPER(xc)(uint32_t l, uint64_t dest, uint64_t src)
uint32_t cc = 0;
HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
- __FUNCTION__, l, dest, src);
+ __func__, l, dest, src);
#ifndef CONFIG_USER_ONLY
/* xor with itself is the same as memset(0) */
@@ -217,7 +217,7 @@ uint32_t HELPER(oc)(uint32_t l, uint64_t dest, uint64_t src)
uint32_t cc = 0;
HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
- __FUNCTION__, l, dest, src);
+ __func__, l, dest, src);
for (i = 0; i <= l; i++) {
x = ldub(dest + i) | ldub(src + i);
if (x) {
@@ -236,7 +236,7 @@ void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
uint32_t l_64 = (l + 1) / 8;
HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
- __FUNCTION__, l, dest, src);
+ __func__, l, dest, src);
#ifndef CONFIG_USER_ONLY
if ((l > 32) &&
@@ -278,10 +278,11 @@ void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
{
int i;
- unsigned char x,y;
+ unsigned char x, y;
uint32_t cc;
+
HELPER_LOG("%s l %d s1 %" PRIx64 " s2 %" PRIx64 "\n",
- __FUNCTION__, l, s1, s2);
+ __func__, l, s1, s2);
for (i = 0; i <= l; i++) {
x = ldub(s1 + i);
y = ldub(s2 + i);
@@ -295,7 +296,7 @@ uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
}
}
cc = 0;
-done:
+ done:
HELPER_LOG("\n");
return cc;
}
@@ -303,9 +304,10 @@ done:
/* compare logical under mask */
uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
{
- uint8_t r,d;
+ uint8_t r, d;
uint32_t cc;
- HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%" PRIx64 "\n", __FUNCTION__, r1,
+
+ HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%" PRIx64 "\n", __func__, r1,
mask, addr);
cc = 0;
while (mask) {
@@ -313,7 +315,7 @@ uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
d = ldub(addr);
r = (r1 & 0xff000000UL) >> 24;
HELPER_LOG("mask 0x%x %02x/%02x (0x%" PRIx64 ") ", mask, r, d,
- addr);
+ addr);
if (r < d) {
cc = 1;
break;
@@ -334,7 +336,8 @@ uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
void HELPER(stcm)(uint32_t r1, uint32_t mask, uint64_t addr)
{
uint8_t r;
- HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%lx\n", __FUNCTION__, r1, mask,
+
+ HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%lx\n", __func__, r1, mask,
addr);
while (mask) {
if (mask & 8) {
@@ -355,6 +358,7 @@ void HELPER(mlg)(uint32_t r1, uint64_t v2)
#if HOST_LONG_BITS == 64 && defined(__GNUC__)
/* assuming 64-bit hosts have __uint128_t */
__uint128_t res = (__uint128_t)env->regs[r1 + 1];
+
res *= (__uint128_t)v2;
env->regs[r1] = (uint64_t)(res >> 64);
env->regs[r1 + 1] = (uint64_t)res;
@@ -370,18 +374,18 @@ void HELPER(dlg)(uint32_t r1, uint64_t v2)
if (!env->regs[r1]) {
/* 64 -> 64/64 case */
- env->regs[r1] = env->regs[r1+1] % divisor;
- env->regs[r1+1] = env->regs[r1+1] / divisor;
+ env->regs[r1] = env->regs[r1 + 1] % divisor;
+ env->regs[r1 + 1] = env->regs[r1 + 1] / divisor;
return;
} else {
-
#if HOST_LONG_BITS == 64 && defined(__GNUC__)
/* assuming 64-bit hosts have __uint128_t */
__uint128_t dividend = (((__uint128_t)env->regs[r1]) << 64) |
- (env->regs[r1+1]);
+ (env->regs[r1 + 1]);
__uint128_t quotient = dividend / divisor;
- env->regs[r1+1] = quotient;
__uint128_t remainder = dividend % divisor;
+
+ env->regs[r1 + 1] = quotient;
env->regs[r1] = remainder;
#else
/* 32-bit hosts would need special wrapper functionality - just abort if
@@ -431,7 +435,7 @@ uint32_t HELPER(srst)(uint32_t c, uint32_t r1, uint32_t r2)
uint64_t str = get_address_31fix(r2);
uint64_t end = get_address_31fix(r1);
- HELPER_LOG("%s: c %d *r1 0x%" PRIx64 " *r2 0x%" PRIx64 "\n", __FUNCTION__,
+ HELPER_LOG("%s: c %d *r1 0x%" PRIx64 " *r2 0x%" PRIx64 "\n", __func__,
c, env->regs[r1], env->regs[r2]);
for (i = str; i != end; i++) {
@@ -452,11 +456,12 @@ uint32_t HELPER(clst)(uint32_t c, uint32_t r1, uint32_t r2)
uint64_t s2 = get_address_31fix(r2);
uint8_t v1, v2;
uint32_t cc;
+
c = c & 0xff;
#ifdef CONFIG_USER_ONLY
if (!c) {
HELPER_LOG("%s: comparing '%s' and '%s'\n",
- __FUNCTION__, (char*)g2h(s1), (char*)g2h(s2));
+ __func__, (char *)g2h(s1), (char *)g2h(s2));
}
#endif
for (;;) {
@@ -501,10 +506,11 @@ void HELPER(mvst)(uint32_t c, uint32_t r1, uint32_t r2)
uint64_t dest = get_address_31fix(r1);
uint64_t src = get_address_31fix(r2);
uint8_t v;
+
c = c & 0xff;
#ifdef CONFIG_USER_ONLY
if (!c) {
- HELPER_LOG("%s: copy '%s' to 0x%lx\n", __FUNCTION__, (char*)g2h(src),
+ HELPER_LOG("%s: copy '%s' to 0x%lx\n", __func__, (char *)g2h(src),
dest);
}
#endif
@@ -526,6 +532,7 @@ uint32_t HELPER(csg)(uint32_t r1, uint64_t a2, uint32_t r3)
/* FIXME: locking? */
uint32_t cc;
uint64_t v2 = ldq(a2);
+
if (env->regs[r1] == v2) {
cc = 0;
stq(a2, env->regs[r3]);
@@ -564,8 +571,9 @@ uint32_t HELPER(cs)(uint32_t r1, uint64_t a2, uint32_t r3)
{
/* FIXME: locking? */
uint32_t cc;
- HELPER_LOG("%s: r1 %d a2 0x%lx r3 %d\n", __FUNCTION__, r1, a2, r3);
uint32_t v2 = ldl(a2);
+
+ HELPER_LOG("%s: r1 %d a2 0x%lx r3 %d\n", __func__, r1, a2, r3);
if (((uint32_t)env->regs[r1]) == v2) {
cc = 0;
stl(a2, (uint32_t)env->regs[r3]);
@@ -612,14 +620,16 @@ static uint32_t helper_icm(uint32_t r1, uint64_t address, uint32_t mask)
it does not change the program counter
in other words: tricky...
currently implemented by interpreting the cases it is most commonly used in
- */
+*/
uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
{
uint16_t insn = lduw_code(addr);
- HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __FUNCTION__, v1, addr,
- insn);
+
+ HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr,
+ insn);
if ((insn & 0xf0ff) == 0xd000) {
uint32_t l, insn2, b1, b2, d1, d2;
+
l = v1 & 0xff;
insn2 = ldl_code(addr + 2);
b1 = (insn2 >> 28) & 0xf;
@@ -645,13 +655,14 @@ uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
}
} else if ((insn & 0xff00) == 0x0a00) {
/* supervisor call */
- HELPER_LOG("%s: svc %ld via execute\n", __FUNCTION__, (insn|v1) & 0xff);
+ HELPER_LOG("%s: svc %ld via execute\n", __func__, (insn | v1) & 0xff);
env->psw.addr = ret - 4;
- env->int_svc_code = (insn|v1) & 0xff;
+ env->int_svc_code = (insn | v1) & 0xff;
env->int_svc_ilc = 4;
helper_exception(EXCP_SVC);
} else if ((insn & 0xff00) == 0xbf00) {
uint32_t insn2, r1, r3, b2, d2;
+
insn2 = ldl_code(addr + 2);
r1 = (insn2 >> 20) & 0xf;
r3 = (insn2 >> 16) & 0xf;
@@ -659,7 +670,7 @@ uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
d2 = insn2 & 0xfff;
cc = helper_icm(r1, get_address(0, b2, d2), r3);
} else {
-abort:
+ abort:
cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n",
insn);
}
@@ -689,7 +700,7 @@ int32_t HELPER(nabs_i32)(int32_t val)
/* absolute value 64-bit */
uint64_t HELPER(abs_i64)(int64_t val)
{
- HELPER_LOG("%s: val 0x%" PRIx64 "\n", __FUNCTION__, val);
+ HELPER_LOG("%s: val 0x%" PRIx64 "\n", __func__, val);
if (val < 0) {
return -val;
@@ -774,9 +785,9 @@ void HELPER(ipm)(uint32_t cc, uint32_t r1)
uint64_t r = env->regs[r1];
r &= 0xffffffff00ffffffULL;
- r |= (cc << 28) | ( (env->psw.mask >> 40) & 0xf );
+ r |= (cc << 28) | ((env->psw.mask >> 40) & 0xf);
env->regs[r1] = r;
- HELPER_LOG("%s: cc %d psw.mask 0x%lx r1 0x%lx\n", __FUNCTION__,
+ HELPER_LOG("%s: cc %d psw.mask 0x%lx r1 0x%lx\n", __func__,
cc, env->psw.mask, r);
}
@@ -908,7 +919,7 @@ uint32_t HELPER(clcle)(uint32_t r1, uint64_t a2, uint32_t r3)
uint64_t srclen = env->regs[r3 + 1];
uint64_t src = get_address_31fix(r3);
uint8_t pad = a2 & 0xff;
- uint8_t v1 = 0,v2 = 0;
+ uint8_t v1 = 0, v2 = 0;
uint32_t cc = 0;
if (!(destlen || srclen)) {
@@ -1036,7 +1047,7 @@ static uint32_t set_cc_nz_f128(float128 v)
/* convert 32-bit int to 64-bit float */
void HELPER(cdfbr)(uint32_t f1, int32_t v2)
{
- HELPER_LOG("%s: converting %d to f%d\n", __FUNCTION__, v2, f1);
+ HELPER_LOG("%s: converting %d to f%d\n", __func__, v2, f1);
env->fregs[f1].d = int32_to_float64(v2, &env->fpu_status);
}
@@ -1044,6 +1055,7 @@ void HELPER(cdfbr)(uint32_t f1, int32_t v2)
void HELPER(cxfbr)(uint32_t f1, int32_t v2)
{
CPU_QuadU v1;
+
v1.q = int32_to_float128(v2, &env->fpu_status);
env->fregs[f1].ll = v1.ll.upper;
env->fregs[f1 + 2].ll = v1.ll.lower;
@@ -1052,14 +1064,14 @@ void HELPER(cxfbr)(uint32_t f1, int32_t v2)
/* convert 64-bit int to 32-bit float */
void HELPER(cegbr)(uint32_t f1, int64_t v2)
{
- HELPER_LOG("%s: converting %ld to f%d\n", __FUNCTION__, v2, f1);
+ HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
env->fregs[f1].l.upper = int64_to_float32(v2, &env->fpu_status);
}
/* convert 64-bit int to 64-bit float */
void HELPER(cdgbr)(uint32_t f1, int64_t v2)
{
- HELPER_LOG("%s: converting %ld to f%d\n", __FUNCTION__, v2, f1);
+ HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
env->fregs[f1].d = int64_to_float64(v2, &env->fpu_status);
}
@@ -1067,8 +1079,9 @@ void HELPER(cdgbr)(uint32_t f1, int64_t v2)
void HELPER(cxgbr)(uint32_t f1, int64_t v2)
{
CPU_QuadU x1;
+
x1.q = int64_to_float128(v2, &env->fpu_status);
- HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __FUNCTION__, v2,
+ HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __func__, v2,
x1.ll.upper, x1.ll.lower);
env->fregs[f1].ll = x1.ll.upper;
env->fregs[f1 + 2].ll = x1.ll.lower;
@@ -1078,7 +1091,7 @@ void HELPER(cxgbr)(uint32_t f1, int64_t v2)
void HELPER(cefbr)(uint32_t f1, int32_t v2)
{
env->fregs[f1].l.upper = int32_to_float32(v2, &env->fpu_status);
- HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __FUNCTION__, v2,
+ HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __func__, v2,
env->fregs[f1].l.upper, f1);
}
@@ -1088,7 +1101,7 @@ uint32_t HELPER(aebr)(uint32_t f1, uint32_t f2)
env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
env->fregs[f2].l.upper,
&env->fpu_status);
- HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __FUNCTION__,
+ HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
return set_cc_nz_f32(env->fregs[f1].l.upper);
@@ -1099,7 +1112,7 @@ uint32_t HELPER(adbr)(uint32_t f1, uint32_t f2)
{
env->fregs[f1].d = float64_add(env->fregs[f1].d, env->fregs[f2].d,
&env->fpu_status);
- HELPER_LOG("%s: adding 0x%ld resulting in 0x%ld in f%d\n", __FUNCTION__,
+ HELPER_LOG("%s: adding 0x%ld resulting in 0x%ld in f%d\n", __func__,
env->fregs[f2].d, env->fregs[f1].d, f1);
return set_cc_nz_f64(env->fregs[f1].d);
@@ -1111,7 +1124,7 @@ uint32_t HELPER(sebr)(uint32_t f1, uint32_t f2)
env->fregs[f1].l.upper = float32_sub(env->fregs[f1].l.upper,
env->fregs[f2].l.upper,
&env->fpu_status);
- HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __FUNCTION__,
+ HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
return set_cc_nz_f32(env->fregs[f1].l.upper);
@@ -1123,7 +1136,7 @@ uint32_t HELPER(sdbr)(uint32_t f1, uint32_t f2)
env->fregs[f1].d = float64_sub(env->fregs[f1].d, env->fregs[f2].d,
&env->fpu_status);
HELPER_LOG("%s: subtracting 0x%ld resulting in 0x%ld in f%d\n",
- __FUNCTION__, env->fregs[f2].d, env->fregs[f1].d, f1);
+ __func__, env->fregs[f2].d, env->fregs[f1].d, f1);
return set_cc_nz_f64(env->fregs[f1].d);
}
@@ -1140,12 +1153,13 @@ void HELPER(debr)(uint32_t f1, uint32_t f2)
void HELPER(dxbr)(uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
+ CPU_QuadU v2;
+ CPU_QuadU res;
+
v1.ll.upper = env->fregs[f1].ll;
v1.ll.lower = env->fregs[f1 + 2].ll;
- CPU_QuadU v2;
v2.ll.upper = env->fregs[f2].ll;
v2.ll.lower = env->fregs[f2 + 2].ll;
- CPU_QuadU res;
res.q = float128_div(v1.q, v2.q, &env->fpu_status);
env->fregs[f1].ll = res.ll.upper;
env->fregs[f1 + 2].ll = res.ll.lower;
@@ -1162,12 +1176,13 @@ void HELPER(mdbr)(uint32_t f1, uint32_t f2)
void HELPER(mxbr)(uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
+ CPU_QuadU v2;
+ CPU_QuadU res;
+
v1.ll.upper = env->fregs[f1].ll;
v1.ll.lower = env->fregs[f1 + 2].ll;
- CPU_QuadU v2;
v2.ll.upper = env->fregs[f2].ll;
v2.ll.lower = env->fregs[f2 + 2].ll;
- CPU_QuadU res;
res.q = float128_mul(v1.q, v2.q, &env->fpu_status);
env->fregs[f1].ll = res.ll.upper;
env->fregs[f1 + 2].ll = res.ll.lower;
@@ -1184,16 +1199,18 @@ void HELPER(ldebr)(uint32_t r1, uint32_t r2)
void HELPER(ldxbr)(uint32_t f1, uint32_t f2)
{
CPU_QuadU x2;
+
x2.ll.upper = env->fregs[f2].ll;
x2.ll.lower = env->fregs[f2 + 2].ll;
env->fregs[f1].d = float128_to_float64(x2.q, &env->fpu_status);
- HELPER_LOG("%s: to 0x%ld\n", __FUNCTION__, env->fregs[f1].d);
+ HELPER_LOG("%s: to 0x%ld\n", __func__, env->fregs[f1].d);
}
/* convert 64-bit float to 128-bit float */
void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
{
CPU_QuadU res;
+
res.q = float64_to_float128(env->fregs[f2].d, &env->fpu_status);
env->fregs[f1].ll = res.ll.upper;
env->fregs[f1 + 2].ll = res.ll.lower;
@@ -1203,6 +1220,7 @@ void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
void HELPER(ledbr)(uint32_t f1, uint32_t f2)
{
float64 d2 = env->fregs[f2].d;
+
env->fregs[f1].l.upper = float64_to_float32(d2, &env->fpu_status);
}
@@ -1210,10 +1228,11 @@ void HELPER(ledbr)(uint32_t f1, uint32_t f2)
void HELPER(lexbr)(uint32_t f1, uint32_t f2)
{
CPU_QuadU x2;
+
x2.ll.upper = env->fregs[f2].ll;
x2.ll.lower = env->fregs[f2 + 2].ll;
env->fregs[f1].l.upper = float128_to_float32(x2.q, &env->fpu_status);
- HELPER_LOG("%s: to 0x%d\n", __FUNCTION__, env->fregs[f1].l.upper);
+ HELPER_LOG("%s: to 0x%d\n", __func__, env->fregs[f1].l.upper);
}
/* absolute value of 32-bit float */
@@ -1221,6 +1240,7 @@ uint32_t HELPER(lpebr)(uint32_t f1, uint32_t f2)
{
float32 v1;
float32 v2 = env->fregs[f2].d;
+
v1 = float32_abs(v2);
env->fregs[f1].d = v1;
return set_cc_nz_f32(v1);
@@ -1231,6 +1251,7 @@ uint32_t HELPER(lpdbr)(uint32_t f1, uint32_t f2)
{
float64 v1;
float64 v2 = env->fregs[f2].d;
+
v1 = float64_abs(v2);
env->fregs[f1].d = v1;
return set_cc_nz_f64(v1);
@@ -1241,6 +1262,7 @@ uint32_t HELPER(lpxbr)(uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
CPU_QuadU v2;
+
v2.ll.upper = env->fregs[f2].ll;
v2.ll.lower = env->fregs[f2 + 2].ll;
v1.q = float128_abs(v2.q);
@@ -1267,6 +1289,7 @@ uint32_t HELPER(ltebr)(uint32_t f1, uint32_t f2)
uint32_t HELPER(ltxbr)(uint32_t f1, uint32_t f2)
{
CPU_QuadU x;
+
x.ll.upper = env->fregs[f2].ll;
x.ll.lower = env->fregs[f2 + 2].ll;
env->fregs[f1].ll = x.ll.upper;
@@ -1294,6 +1317,7 @@ uint32_t HELPER(lcdbr)(uint32_t f1, uint32_t f2)
uint32_t HELPER(lcxbr)(uint32_t f1, uint32_t f2)
{
CPU_QuadU x1, x2;
+
x2.ll.upper = env->fregs[f2].ll;
x2.ll.lower = env->fregs[f2 + 2].ll;
x1.q = float128_chs(x2.q);
@@ -1307,8 +1331,9 @@ void HELPER(aeb)(uint32_t f1, uint32_t val)
{
float32 v1 = env->fregs[f1].l.upper;
CPU_FloatU v2;
+
v2.l = val;
- HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __FUNCTION__,
+ HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __func__,
v1, f1, v2.f);
env->fregs[f1].l.upper = float32_add(v1, v2.f, &env->fpu_status);
}
@@ -1318,8 +1343,9 @@ void HELPER(deb)(uint32_t f1, uint32_t val)
{
float32 v1 = env->fregs[f1].l.upper;
CPU_FloatU v2;
+
v2.l = val;
- HELPER_LOG("%s: dividing 0x%d from f%d by 0x%d\n", __FUNCTION__,
+ HELPER_LOG("%s: dividing 0x%d from f%d by 0x%d\n", __func__,
v1, f1, v2.f);
env->fregs[f1].l.upper = float32_div(v1, v2.f, &env->fpu_status);
}
@@ -1329,8 +1355,9 @@ void HELPER(meeb)(uint32_t f1, uint32_t val)
{
float32 v1 = env->fregs[f1].l.upper;
CPU_FloatU v2;
+
v2.l = val;
- HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __FUNCTION__,
+ HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __func__,
v1, f1, v2.f);
env->fregs[f1].l.upper = float32_mul(v1, v2.f, &env->fpu_status);
}
@@ -1340,7 +1367,8 @@ uint32_t HELPER(cebr)(uint32_t f1, uint32_t f2)
{
float32 v1 = env->fregs[f1].l.upper;
float32 v2 = env->fregs[f2].l.upper;
- HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __FUNCTION__,
+
+ HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __func__,
v1, f1, v2);
return set_cc_f32(v1, v2);
}
@@ -1350,7 +1378,8 @@ uint32_t HELPER(cdbr)(uint32_t f1, uint32_t f2)
{
float64 v1 = env->fregs[f1].d;
float64 v2 = env->fregs[f2].d;
- HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __FUNCTION__,
+
+ HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __func__,
v1, f1, v2);
return set_cc_f64(v1, v2);
}
@@ -1359,14 +1388,15 @@ uint32_t HELPER(cdbr)(uint32_t f1, uint32_t f2)
uint32_t HELPER(cxbr)(uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
+ CPU_QuadU v2;
+
v1.ll.upper = env->fregs[f1].ll;
v1.ll.lower = env->fregs[f1 + 2].ll;
- CPU_QuadU v2;
v2.ll.upper = env->fregs[f2].ll;
v2.ll.lower = env->fregs[f2 + 2].ll;
return float_comp_to_cc(float128_compare_quiet(v1.q, v2.q,
- &env->fpu_status));
+ &env->fpu_status));
}
/* 64-bit FP compare RM */
@@ -1374,8 +1404,9 @@ uint32_t HELPER(cdb)(uint32_t f1, uint64_t a2)
{
float64 v1 = env->fregs[f1].d;
CPU_DoubleU v2;
+
v2.ll = ldq(a2);
- HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __FUNCTION__, v1,
+ HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __func__, v1,
f1, v2.d);
return set_cc_f64(v1, v2.d);
}
@@ -1385,8 +1416,9 @@ uint32_t HELPER(adb)(uint32_t f1, uint64_t a2)
{
float64 v1 = env->fregs[f1].d;
CPU_DoubleU v2;
+
v2.ll = ldq(a2);
- HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __FUNCTION__,
+ HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __func__,
v1, f1, v2.d);
env->fregs[f1].d = v1 = float64_add(v1, v2.d, &env->fpu_status);
return set_cc_nz_f64(v1);
@@ -1397,6 +1429,7 @@ void HELPER(seb)(uint32_t f1, uint32_t val)
{
float32 v1 = env->fregs[f1].l.upper;
CPU_FloatU v2;
+
v2.l = val;
env->fregs[f1].l.upper = float32_sub(v1, v2.f, &env->fpu_status);
}
@@ -1406,6 +1439,7 @@ uint32_t HELPER(sdb)(uint32_t f1, uint64_t a2)
{
float64 v1 = env->fregs[f1].d;
CPU_DoubleU v2;
+
v2.ll = ldq(a2);
env->fregs[f1].d = v1 = float64_sub(v1, v2.d, &env->fpu_status);
return set_cc_nz_f64(v1);
@@ -1416,8 +1450,9 @@ void HELPER(mdb)(uint32_t f1, uint64_t a2)
{
float64 v1 = env->fregs[f1].d;
CPU_DoubleU v2;
+
v2.ll = ldq(a2);
- HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __FUNCTION__,
+ HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __func__,
v1, f1, v2.d);
env->fregs[f1].d = float64_mul(v1, v2.d, &env->fpu_status);
}
@@ -1427,8 +1462,9 @@ void HELPER(ddb)(uint32_t f1, uint64_t a2)
{
float64 v1 = env->fregs[f1].d;
CPU_DoubleU v2;
+
v2.ll = ldq(a2);
- HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __FUNCTION__,
+ HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __func__,
v1, f1, v2.d);
env->fregs[f1].d = float64_div(v1, v2.d, &env->fpu_status);
}
@@ -1464,6 +1500,7 @@ static void set_round_mode(int m3)
uint32_t HELPER(cgebr)(uint32_t r1, uint32_t f2, uint32_t m3)
{
float32 v2 = env->fregs[f2].l.upper;
+
set_round_mode(m3);
env->regs[r1] = float32_to_int64(v2, &env->fpu_status);
return set_cc_nz_f32(v2);
@@ -1473,6 +1510,7 @@ uint32_t HELPER(cgebr)(uint32_t r1, uint32_t f2, uint32_t m3)
uint32_t HELPER(cgdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
{
float64 v2 = env->fregs[f2].d;
+
set_round_mode(m3);
env->regs[r1] = float64_to_int64(v2, &env->fpu_status);
return set_cc_nz_f64(v2);
@@ -1482,6 +1520,7 @@ uint32_t HELPER(cgdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
{
CPU_QuadU v2;
+
v2.ll.upper = env->fregs[f2].ll;
v2.ll.lower = env->fregs[f2 + 2].ll;
set_round_mode(m3);
@@ -1501,9 +1540,10 @@ uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
uint32_t HELPER(cfebr)(uint32_t r1, uint32_t f2, uint32_t m3)
{
float32 v2 = env->fregs[f2].l.upper;
+
set_round_mode(m3);
env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
- float32_to_int32(v2, &env->fpu_status);
+ float32_to_int32(v2, &env->fpu_status);
return set_cc_nz_f32(v2);
}
@@ -1511,9 +1551,10 @@ uint32_t HELPER(cfebr)(uint32_t r1, uint32_t f2, uint32_t m3)
uint32_t HELPER(cfdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
{
float64 v2 = env->fregs[f2].d;
+
set_round_mode(m3);
env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
- float64_to_int32(v2, &env->fpu_status);
+ float64_to_int32(v2, &env->fpu_status);
return set_cc_nz_f64(v2);
}
@@ -1521,10 +1562,11 @@ uint32_t HELPER(cfdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
uint32_t HELPER(cfxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
{
CPU_QuadU v2;
+
v2.ll.upper = env->fregs[f2].ll;
v2.ll.lower = env->fregs[f2 + 2].ll;
env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
- float128_to_int32(v2.q, &env->fpu_status);
+ float128_to_int32(v2.q, &env->fpu_status);
return set_cc_nz_f128(v2.q);
}
@@ -1544,6 +1586,7 @@ void HELPER(lzdr)(uint32_t f1)
void HELPER(lzxr)(uint32_t f1)
{
CPU_QuadU x;
+
x.q = float64_to_float128(float64_zero, &env->fpu_status);
env->fregs[f1].ll = x.ll.upper;
env->fregs[f1 + 1].ll = x.ll.lower;
@@ -1553,12 +1596,13 @@ void HELPER(lzxr)(uint32_t f1)
uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
+ CPU_QuadU v2;
+ CPU_QuadU res;
+
v1.ll.upper = env->fregs[f1].ll;
v1.ll.lower = env->fregs[f1 + 2].ll;
- CPU_QuadU v2;
v2.ll.upper = env->fregs[f2].ll;
v2.ll.lower = env->fregs[f2 + 2].ll;
- CPU_QuadU res;
res.q = float128_sub(v1.q, v2.q, &env->fpu_status);
env->fregs[f1].ll = res.ll.upper;
env->fregs[f1 + 2].ll = res.ll.lower;
@@ -1569,12 +1613,13 @@ uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
uint32_t HELPER(axbr)(uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
+ CPU_QuadU v2;
+ CPU_QuadU res;
+
v1.ll.upper = env->fregs[f1].ll;
v1.ll.lower = env->fregs[f1 + 2].ll;
- CPU_QuadU v2;
v2.ll.upper = env->fregs[f2].ll;
v2.ll.lower = env->fregs[f2 + 2].ll;
- CPU_QuadU res;
res.q = float128_add(v1.q, v2.q, &env->fpu_status);
env->fregs[f1].ll = res.ll.upper;
env->fregs[f1 + 2].ll = res.ll.lower;
@@ -1599,8 +1644,9 @@ void HELPER(ddbr)(uint32_t f1, uint32_t f2)
/* 64-bit FP multiply and add RM */
void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
{
- HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __FUNCTION__, f1, a2, f3);
CPU_DoubleU v2;
+
+ HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __func__, f1, a2, f3);
v2.ll = ldq(a2);
env->fregs[f1].d = float64_add(env->fregs[f1].d,
float64_mul(v2.d, env->fregs[f3].d,
@@ -1611,7 +1657,7 @@ void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
/* 64-bit FP multiply and add RR */
void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
{
- HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __FUNCTION__, f1, f2, f3);
+ HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
env->fregs[f1].d = float64_add(float64_mul(env->fregs[f2].d,
env->fregs[f3].d,
&env->fpu_status),
@@ -1621,7 +1667,7 @@ void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
/* 64-bit FP multiply and subtract RR */
void HELPER(msdbr)(uint32_t f1, uint32_t f3, uint32_t f2)
{
- HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __FUNCTION__, f1, f2, f3);
+ HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
env->fregs[f1].d = float64_sub(float64_mul(env->fregs[f2].d,
env->fregs[f3].d,
&env->fpu_status),
@@ -1642,6 +1688,7 @@ void HELPER(maebr)(uint32_t f1, uint32_t f3, uint32_t f2)
void HELPER(ldeb)(uint32_t f1, uint64_t a2)
{
uint32_t v2;
+
v2 = ldl(a2);
env->fregs[f1].d = float32_to_float64(v2,
&env->fpu_status);
@@ -1651,8 +1698,9 @@ void HELPER(ldeb)(uint32_t f1, uint64_t a2)
void HELPER(lxdb)(uint32_t f1, uint64_t a2)
{
CPU_DoubleU v2;
- v2.ll = ldq(a2);
CPU_QuadU v1;
+
+ v2.ll = ldq(a2);
v1.q = float64_to_float128(v2.d, &env->fpu_status);
env->fregs[f1].ll = v1.ll.upper;
env->fregs[f1 + 2].ll = v1.ll.lower;
@@ -1665,7 +1713,7 @@ uint32_t HELPER(tceb)(uint32_t f1, uint64_t m2)
int neg = float32_is_neg(v1);
uint32_t cc = 0;
- HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __FUNCTION__, (long)v1, m2, neg);
+ HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, (long)v1, m2, neg);
if ((float32_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
(float32_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
(float32_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
@@ -1687,7 +1735,7 @@ uint32_t HELPER(tcdb)(uint32_t f1, uint64_t m2)
int neg = float64_is_neg(v1);
uint32_t cc = 0;
- HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __FUNCTION__, v1, m2, neg);
+ HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, v1, m2, neg);
if ((float64_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
(float64_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
(float64_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
@@ -1706,10 +1754,12 @@ uint32_t HELPER(tcxb)(uint32_t f1, uint64_t m2)
{
CPU_QuadU v1;
uint32_t cc = 0;
+ int neg;
+
v1.ll.upper = env->fregs[f1].ll;
v1.ll.lower = env->fregs[f1 + 2].ll;
- int neg = float128_is_neg(v1.q);
+ neg = float128_is_neg(v1.q);
if ((float128_is_zero(v1.q) && (m2 & (1 << (11-neg)))) ||
(float128_is_infinity(v1.q) && (m2 & (1 << (5-neg)))) ||
(float128_is_any_nan(v1.q) && (m2 & (1 << (3-neg)))) ||
@@ -1787,7 +1837,7 @@ void HELPER(cksm)(uint32_t r1, uint32_t r2)
/* store result */
env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
- ((uint32_t)cksm + (cksm >> 32));
+ ((uint32_t)cksm + (cksm >> 32));
}
static inline uint32_t cc_calc_ltgt_32(CPUS390XState *env, int32_t src,
@@ -1848,10 +1898,12 @@ static inline uint32_t cc_calc_ltugtu_64(CPUS390XState *env, uint64_t src,
}
}
-static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val, uint32_t mask)
+static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val,
+ uint32_t mask)
{
- HELPER_LOG("%s: val 0x%x mask 0x%x\n", __FUNCTION__, val, mask);
uint16_t r = val & mask;
+
+ HELPER_LOG("%s: val 0x%x mask 0x%x\n", __func__, val, mask);
if (r == 0 || mask == 0) {
return 0;
} else if (r == mask) {
@@ -1862,10 +1914,12 @@ static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val, uint32_t
}
/* set condition code for test under mask */
-static inline uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val, uint32_t mask)
+static inline uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val,
+ uint32_t mask)
{
uint16_t r = val & mask;
- HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __FUNCTION__, val, mask, r);
+
+ HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __func__, val, mask, r);
if (r == 0 || mask == 0) {
return 0;
} else if (r == mask) {
@@ -1888,8 +1942,8 @@ static inline uint32_t cc_calc_nz(CPUS390XState *env, uint64_t dst)
return !!dst;
}
-static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1, int64_t a2,
- int64_t ar)
+static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1,
+ int64_t a2, int64_t ar)
{
if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
return 3; /* overflow */
@@ -1904,8 +1958,8 @@ static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1, int64_t a2
}
}
-static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1, uint64_t a2,
- uint64_t ar)
+static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1,
+ uint64_t a2, uint64_t ar)
{
if (ar == 0) {
if (a1) {
@@ -1915,15 +1969,15 @@ static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1, uint64_t
}
} else {
if (ar < a1 || ar < a2) {
- return 3;
+ return 3;
} else {
- return 1;
+ return 1;
}
}
}
-static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1, int64_t a2,
- int64_t ar)
+static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1,
+ int64_t a2, int64_t ar)
{
if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
return 3; /* overflow */
@@ -1938,8 +1992,8 @@ static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1, int64_t a2
}
}
-static inline uint32_t cc_calc_subu_64(CPUS390XState *env, uint64_t a1, uint64_t a2,
- uint64_t ar)
+static inline uint32_t cc_calc_subu_64(CPUS390XState *env, uint64_t a1,
+ uint64_t a2, uint64_t ar)
{
if (ar == 0) {
return 2;
@@ -1982,8 +2036,8 @@ static inline uint32_t cc_calc_comp_64(CPUS390XState *env, int64_t dst)
}
-static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1, int32_t a2,
- int32_t ar)
+static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1,
+ int32_t a2, int32_t ar)
{
if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
return 3; /* overflow */
@@ -1998,26 +2052,26 @@ static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1, int32_t a2
}
}
-static inline uint32_t cc_calc_addu_32(CPUS390XState *env, uint32_t a1, uint32_t a2,
- uint32_t ar)
+static inline uint32_t cc_calc_addu_32(CPUS390XState *env, uint32_t a1,
+ uint32_t a2, uint32_t ar)
{
if (ar == 0) {
if (a1) {
- return 2;
+ return 2;
} else {
- return 0;
+ return 0;
}
} else {
if (ar < a1 || ar < a2) {
- return 3;
+ return 3;
} else {
- return 1;
+ return 1;
}
}
}
-static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1, int32_t a2,
- int32_t ar)
+static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1,
+ int32_t a2, int32_t ar)
{
if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
return 3; /* overflow */
@@ -2032,8 +2086,8 @@ static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1, int32_t a2
}
}
-static inline uint32_t cc_calc_subu_32(CPUS390XState *env, uint32_t a1, uint32_t a2,
- uint32_t ar)
+static inline uint32_t cc_calc_subu_32(CPUS390XState *env, uint32_t a1,
+ uint32_t a2, uint32_t ar)
{
if (ar == 0) {
return 2;
@@ -2076,11 +2130,12 @@ static inline uint32_t cc_calc_comp_32(CPUS390XState *env, int32_t dst)
}
/* calculate condition code for insert character under mask insn */
-static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask, uint32_t val)
+static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask,
+ uint32_t val)
{
- HELPER_LOG("%s: mask 0x%x val %d\n", __FUNCTION__, mask, val);
uint32_t cc;
+ HELPER_LOG("%s: mask 0x%x val %d\n", __func__, mask, val);
if (mask == 0xf) {
if (!val) {
return 0;
@@ -2107,7 +2162,8 @@ static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask, uint32_
return cc;
}
-static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src, uint64_t shift)
+static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src,
+ uint64_t shift)
{
uint64_t mask = ((1ULL << shift) - 1ULL) << (64 - shift);
uint64_t match, r;
@@ -2136,8 +2192,8 @@ static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src, uint64_t s
}
-static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src,
- uint64_t dst, uint64_t vr)
+static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
+ uint64_t src, uint64_t dst, uint64_t vr)
{
uint32_t r = 0;
@@ -2244,7 +2300,7 @@ static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t s
cpu_abort(env, "Unknown CC operation: %s\n", cc_name(cc_op));
}
- HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __FUNCTION__,
+ HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__,
cc_name(cc_op), src, dst, vr, r);
return r;
}
@@ -2334,6 +2390,7 @@ void HELPER(tr)(uint32_t len, uint64_t array, uint64_t trans)
for (i = 0; i <= len; i++) {
uint8_t byte = ldub(array + i);
uint8_t new_byte = ldub(trans + byte);
+
stb(array + i, new_byte);
}
}
@@ -2363,7 +2420,7 @@ static void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
}
/*
- * ret < 0 indicates program check, ret = 0,1,2,3 -> cc
+ * ret < 0 indicates program check, ret = 0, 1, 2, 3 -> cc
*/
int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
{
@@ -2382,24 +2439,24 @@ int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
return -PGM_SPECIFICATION;
}
- switch(code) {
- case SCLP_CMDW_READ_SCP_INFO:
- case SCLP_CMDW_READ_SCP_INFO_FORCED:
- while ((ram_size >> (20 + shift)) > 65535) {
- shift++;
- }
- stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
- stb_phys(sccb + SCP_INCREMENT, 1 << shift);
- stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
+ switch (code) {
+ case SCLP_CMDW_READ_SCP_INFO:
+ case SCLP_CMDW_READ_SCP_INFO_FORCED:
+ while ((ram_size >> (20 + shift)) > 65535) {
+ shift++;
+ }
+ stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
+ stb_phys(sccb + SCP_INCREMENT, 1 << shift);
+ stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
- s390_sclp_extint(sccb & ~3);
- break;
- default:
+ s390_sclp_extint(sccb & ~3);
+ break;
+ default:
#ifdef DEBUG_HELPER
- printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
+ printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
#endif
- r = 3;
- break;
+ r = 3;
+ break;
}
return r;
@@ -2479,7 +2536,7 @@ static inline uint64_t clock_value(CPUS390XState *env)
uint64_t time;
time = env->tod_offset +
- time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
+ time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
return time;
}
@@ -2503,7 +2560,6 @@ uint32_t HELPER(stcke)(uint64_t a1)
/* XXX programmable fields */
stw(a1 + 17, 0);
-
return 0;
}
@@ -2584,7 +2640,7 @@ uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
ebcdic_put(sysib.model, "QEMU ", 16);
ebcdic_put(sysib.sequence, "QEMU ", 16);
ebcdic_put(sysib.plant, "QEMU", 4);
- cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
} else if ((sel1 == 2) && (sel2 == 1)) {
/* Basic Machine CPU */
struct sysib_121 sysib;
@@ -2594,7 +2650,7 @@ uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
ebcdic_put(sysib.plant, "QEMU", 4);
stw_p(&sysib.cpu_addr, env->cpu_num);
- cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
} else if ((sel1 == 2) && (sel2 == 2)) {
/* Basic Machine CPUs */
struct sysib_122 sysib;
@@ -2606,68 +2662,68 @@ uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
stw_p(&sysib.active_cpus, 1);
stw_p(&sysib.standby_cpus, 0);
stw_p(&sysib.reserved_cpus, 0);
- cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
} else {
cc = 3;
}
break;
case STSI_LEVEL_2:
- {
- if ((sel1 == 2) && (sel2 == 1)) {
- /* LPAR CPU */
- struct sysib_221 sysib;
-
- memset(&sysib, 0, sizeof(sysib));
- /* XXX make different for different CPUs? */
- ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
- ebcdic_put(sysib.plant, "QEMU", 4);
- stw_p(&sysib.cpu_addr, env->cpu_num);
- stw_p(&sysib.cpu_id, 0);
- cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
- } else if ((sel1 == 2) && (sel2 == 2)) {
- /* LPAR CPUs */
- struct sysib_222 sysib;
-
- memset(&sysib, 0, sizeof(sysib));
- stw_p(&sysib.lpar_num, 0);
- sysib.lcpuc = 0;
- /* XXX change when SMP comes */
- stw_p(&sysib.total_cpus, 1);
- stw_p(&sysib.conf_cpus, 1);
- stw_p(&sysib.standby_cpus, 0);
- stw_p(&sysib.reserved_cpus, 0);
- ebcdic_put(sysib.name, "QEMU ", 8);
- stl_p(&sysib.caf, 1000);
- stw_p(&sysib.dedicated_cpus, 0);
- stw_p(&sysib.shared_cpus, 0);
- cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
- } else {
- cc = 3;
+ {
+ if ((sel1 == 2) && (sel2 == 1)) {
+ /* LPAR CPU */
+ struct sysib_221 sysib;
+
+ memset(&sysib, 0, sizeof(sysib));
+ /* XXX make different for different CPUs? */
+ ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
+ ebcdic_put(sysib.plant, "QEMU", 4);
+ stw_p(&sysib.cpu_addr, env->cpu_num);
+ stw_p(&sysib.cpu_id, 0);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
+ } else if ((sel1 == 2) && (sel2 == 2)) {
+ /* LPAR CPUs */
+ struct sysib_222 sysib;
+
+ memset(&sysib, 0, sizeof(sysib));
+ stw_p(&sysib.lpar_num, 0);
+ sysib.lcpuc = 0;
+ /* XXX change when SMP comes */
+ stw_p(&sysib.total_cpus, 1);
+ stw_p(&sysib.conf_cpus, 1);
+ stw_p(&sysib.standby_cpus, 0);
+ stw_p(&sysib.reserved_cpus, 0);
+ ebcdic_put(sysib.name, "QEMU ", 8);
+ stl_p(&sysib.caf, 1000);
+ stw_p(&sysib.dedicated_cpus, 0);
+ stw_p(&sysib.shared_cpus, 0);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
+ } else {
+ cc = 3;
+ }
+ break;
}
- break;
- }
case STSI_LEVEL_3:
- {
- if ((sel1 == 2) && (sel2 == 2)) {
- /* VM CPUs */
- struct sysib_322 sysib;
-
- memset(&sysib, 0, sizeof(sysib));
- sysib.count = 1;
- /* XXX change when SMP comes */
- stw_p(&sysib.vm[0].total_cpus, 1);
- stw_p(&sysib.vm[0].conf_cpus, 1);
- stw_p(&sysib.vm[0].standby_cpus, 0);
- stw_p(&sysib.vm[0].reserved_cpus, 0);
- ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
- stl_p(&sysib.vm[0].caf, 1000);
- ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
- cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
- } else {
- cc = 3;
+ {
+ if ((sel1 == 2) && (sel2 == 2)) {
+ /* VM CPUs */
+ struct sysib_322 sysib;
+
+ memset(&sysib, 0, sizeof(sysib));
+ sysib.count = 1;
+ /* XXX change when SMP comes */
+ stw_p(&sysib.vm[0].total_cpus, 1);
+ stw_p(&sysib.vm[0].conf_cpus, 1);
+ stw_p(&sysib.vm[0].standby_cpus, 0);
+ stw_p(&sysib.vm[0].reserved_cpus, 0);
+ ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
+ stl_p(&sysib.vm[0].caf, 1000);
+ ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
+ } else {
+ cc = 3;
+ }
+ break;
}
- break;
- }
case STSI_LEVEL_CURRENT:
env->regs[0] = STSI_LEVEL_3;
break;
@@ -2781,6 +2837,7 @@ uint32_t HELPER(rrbe)(uint32_t r1, uint64_t r2)
{
uint8_t re;
uint8_t key;
+
if (r2 > ram_size) {
return 0;
}
@@ -2865,7 +2922,7 @@ static uint32_t mvc_asc(int64_t l, uint64_t a1, uint64_t mode1, uint64_t a2,
uint32_t HELPER(mvcs)(uint64_t l, uint64_t a1, uint64_t a2)
{
HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
- __FUNCTION__, l, a1, a2);
+ __func__, l, a1, a2);
return mvc_asc(l, a1, PSW_ASC_SECONDARY, a2, PSW_ASC_PRIMARY);
}
@@ -2873,7 +2930,7 @@ uint32_t HELPER(mvcs)(uint64_t l, uint64_t a1, uint64_t a2)
uint32_t HELPER(mvcp)(uint64_t l, uint64_t a1, uint64_t a2)
{
HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
- __FUNCTION__, l, a1, a2);
+ __func__, l, a1, a2);
return mvc_asc(l, a1, PSW_ASC_PRIMARY, a2, PSW_ASC_SECONDARY);
}
@@ -2883,9 +2940,9 @@ uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
int cc = 0;
HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
- __FUNCTION__, order_code, r1, cpu_addr);
+ __func__, order_code, r1, cpu_addr);
- /* Remember: Use "R1 or R1+1, whichever is the odd-numbered register"
+ /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
as parameter (input). Status (output) is always R1. */
switch (order_code) {
@@ -2901,7 +2958,7 @@ uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
env->regs[r1] &= 0xffffffff00000000ULL;
cc = 1;
break;
-#if !defined (CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
case SIGP_RESTART:
qemu_system_reset_request();
cpu_loop_exit(env);
@@ -2922,7 +2979,7 @@ uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
void HELPER(sacf)(uint64_t a1)
{
- HELPER_LOG("%s: %16" PRIx64 "\n", __FUNCTION__, a1);
+ HELPER_LOG("%s: %16" PRIx64 "\n", __func__, a1);
switch (a1 & 0xf00) {
case 0x000:
@@ -2953,13 +3010,13 @@ void HELPER(ipte)(uint64_t pte_addr, uint64_t vaddr)
/* XXX broadcast to other CPUs */
/* XXX Linux is nice enough to give us the exact pte address.
- According to spec we'd have to find it out ourselves */
+ According to spec we'd have to find it out ourselves */
/* XXX Linux is fine with overwriting the pte, the spec requires
- us to only set the invalid bit */
+ us to only set the invalid bit */
stq_phys(pte_addr, pte | _PAGE_INVALID);
/* XXX we exploit the fact that Linux passes the exact virtual
- address here - it's not obliged to! */
+ address here - it's not obliged to! */
tlb_flush_page(env, page);
/* XXX 31-bit hack */
@@ -3008,7 +3065,8 @@ uint32_t HELPER(lra)(uint64_t addr, uint32_t r1)
env->exception_index = old_exc;
if (!(env->psw.mask & PSW_MASK_64)) {
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | (ret & 0xffffffffULL);
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
+ (ret & 0xffffffffULL);
} else {
env->regs[r1] = ret;
}
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 01/21] target-s390x: fix style
2012-09-02 17:33 ` [Qemu-devel] [PATCH 01/21] target-s390x: fix style Blue Swirl
@ 2012-09-03 4:31 ` Alexander Graf
2012-09-03 19:10 ` Blue Swirl
2012-09-06 18:33 ` Alexander Graf
1 sibling, 1 reply; 64+ messages in thread
From: Alexander Graf @ 2012-09-03 4:31 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel qemu-devel, Richard Henderson
On 02.09.2012, at 13:33, Blue Swirl wrote:
> Before splitting op_helper.c and helper.c in the next patches,
> fix style issues. No functional changes.
>
> Replace also GCC specific __FUNCTION__ with
> standard __func__.
>
> Don't init static variable (cpu_s390x_init:inited) with 0.
>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Phew. Have you hooked up with Richard about these changes? He had quite a big rewrite of the s390 target in the works, and I don't want you guys to work needlessly on major conflicts :)
Alex
> ---
> target-s390x/helper.c | 96 +++++-----
> target-s390x/op_helper.c | 438 ++++++++++++++++++++++++++--------------------
> 2 files changed, 297 insertions(+), 237 deletions(-)
>
> diff --git a/target-s390x/helper.c b/target-s390x/helper.c
> index d0a1180..d98e6d9 100644
> --- a/target-s390x/helper.c
> +++ b/target-s390x/helper.c
> @@ -74,7 +74,7 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
> {
> S390CPU *cpu;
> CPUS390XState *env;
> - static int inited = 0;
> + static int inited;
>
> cpu = S390_CPU(object_new(TYPE_S390_CPU));
> env = &cpu->env;
> @@ -91,25 +91,27 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
>
> #if defined(CONFIG_USER_ONLY)
>
> -void do_interrupt (CPUS390XState *env)
> +void do_interrupt(CPUS390XState *env)
> {
> env->exception_index = -1;
> }
>
> -int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
> - int mmu_idx)
> +int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
> + int rw, int mmu_idx)
> {
> - /* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d\n",
> - __FUNCTION__, address, rw, mmu_idx); */
> + /* fprintf(stderr, "%s: address 0x%lx rw %d mmu_idx %d\n",
> + __func__, address, rw, mmu_idx); */
> env->exception_index = EXCP_ADDR;
> - env->__excp_addr = address; /* FIXME: find out how this works on a real machine */
> + /* FIXME: find out how this works on a real machine */
> + env->__excp_addr = address;
> return 1;
> }
>
> #else /* !CONFIG_USER_ONLY */
>
> /* Ensure to exit the TB after this call! */
> -static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilc)
> +static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
> + uint32_t ilc)
> {
> env->exception_index = EXCP_PGM;
> env->int_pgm_code = code;
> @@ -138,19 +140,20 @@ static int trans_bits(CPUS390XState *env, uint64_t mode)
> return bits;
> }
>
> -static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, uint64_t mode)
> +static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
> + uint64_t mode)
> {
> int ilc = ILC_LATER_INC_2;
> int bits = trans_bits(env, mode) | 4;
>
> - DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
> + DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
>
> stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
> trigger_pgm_exception(env, PGM_PROTECTION, ilc);
> }
>
> -static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type,
> - uint64_t asc, int rw)
> +static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
> + uint32_t type, uint64_t asc, int rw)
> {
> int ilc = ILC_LATER;
> int bits = trans_bits(env, asc);
> @@ -160,26 +163,26 @@ static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t
> ilc = 2;
> }
>
> - DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
> + DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
>
> stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
> trigger_pgm_exception(env, type, ilc);
> }
>
> -static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
> - uint64_t asce, int level, target_ulong *raddr,
> - int *flags, int rw)
> +static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
> + uint64_t asc, uint64_t asce, int level,
> + target_ulong *raddr, int *flags, int rw)
> {
> uint64_t offs = 0;
> uint64_t origin;
> uint64_t new_asce;
>
> - PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __FUNCTION__, asce);
> + PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);
>
> if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
> ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
> /* XXX different regions have different faults */
> - DPRINTF("%s: invalid region\n", __FUNCTION__);
> + DPRINTF("%s: invalid region\n", __func__);
> trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
> return -1;
> }
> @@ -222,7 +225,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t a
>
> new_asce = ldq_phys(origin + offs);
> PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
> - __FUNCTION__, origin, offs, new_asce);
> + __func__, origin, offs, new_asce);
>
> if (level != _ASCE_TYPE_SEGMENT) {
> /* yet another region */
> @@ -232,7 +235,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t a
>
> /* PTE */
> if (new_asce & _PAGE_INVALID) {
> - DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __FUNCTION__, new_asce);
> + DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce);
> trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
> return -1;
> }
> @@ -243,13 +246,14 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t a
>
> *raddr = new_asce & _ASCE_ORIGIN;
>
> - PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __FUNCTION__, new_asce);
> + PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce);
>
> return 0;
> }
>
> -static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
> - target_ulong *raddr, int *flags, int rw)
> +static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
> + uint64_t asc, target_ulong *raddr, int *flags,
> + int rw)
> {
> uint64_t asce = 0;
> int level, new_level;
> @@ -257,15 +261,15 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
>
> switch (asc) {
> case PSW_ASC_PRIMARY:
> - PTE_DPRINTF("%s: asc=primary\n", __FUNCTION__);
> + PTE_DPRINTF("%s: asc=primary\n", __func__);
> asce = env->cregs[1];
> break;
> case PSW_ASC_SECONDARY:
> - PTE_DPRINTF("%s: asc=secondary\n", __FUNCTION__);
> + PTE_DPRINTF("%s: asc=secondary\n", __func__);
> asce = env->cregs[7];
> break;
> case PSW_ASC_HOME:
> - PTE_DPRINTF("%s: asc=home\n", __FUNCTION__);
> + PTE_DPRINTF("%s: asc=home\n", __func__);
> asce = env->cregs[13];
> break;
> }
> @@ -276,8 +280,7 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
> case _ASCE_TYPE_REGION2:
> if (vaddr & 0xffe0000000000000ULL) {
> DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
> - " 0xffe0000000000000ULL\n", __FUNCTION__,
> - vaddr);
> + " 0xffe0000000000000ULL\n", __func__, vaddr);
> trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
> return -1;
> }
> @@ -285,8 +288,7 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
> case _ASCE_TYPE_REGION3:
> if (vaddr & 0xfffffc0000000000ULL) {
> DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
> - " 0xfffffc0000000000ULL\n", __FUNCTION__,
> - vaddr);
> + " 0xfffffc0000000000ULL\n", __func__, vaddr);
> trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
> return -1;
> }
> @@ -294,8 +296,7 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
> case _ASCE_TYPE_SEGMENT:
> if (vaddr & 0xffffffff80000000ULL) {
> DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
> - " 0xffffffff80000000ULL\n", __FUNCTION__,
> - vaddr);
> + " 0xffffffff80000000ULL\n", __func__, vaddr);
> trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
> return -1;
> }
> @@ -358,7 +359,7 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
> break;
> }
>
> -out:
> + out:
> /* Convert real address -> absolute address */
> if (*raddr < 0x2000) {
> *raddr = *raddr + env->psa;
> @@ -378,18 +379,18 @@ out:
> return r;
> }
>
> -int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong _vaddr, int rw,
> - int mmu_idx)
> +int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
> + int rw, int mmu_idx)
> {
> uint64_t asc = env->psw.mask & PSW_MASK_ASC;
> target_ulong vaddr, raddr;
> int prot;
>
> DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
> - __FUNCTION__, _vaddr, rw, mmu_idx);
> + __func__, _vaddr, rw, mmu_idx);
>
> - _vaddr &= TARGET_PAGE_MASK;
> - vaddr = _vaddr;
> + orig_vaddr &= TARGET_PAGE_MASK;
> + vaddr = orig_vaddr;
>
> /* 31-Bit mode */
> if (!(env->psw.mask & PSW_MASK_64)) {
> @@ -403,22 +404,23 @@ int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong _vaddr, int rw,
>
> /* check out of RAM access */
> if (raddr > (ram_size + virtio_size)) {
> - DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __FUNCTION__,
> + DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
> (uint64_t)aaddr, (uint64_t)ram_size);
> trigger_pgm_exception(env, PGM_ADDRESSING, ILC_LATER);
> return 1;
> }
>
> - DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __FUNCTION__,
> + DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
> (uint64_t)vaddr, (uint64_t)raddr, prot);
>
> - tlb_set_page(env, _vaddr, raddr, prot,
> + tlb_set_page(env, orig_vaddr, raddr, prot,
> mmu_idx, TARGET_PAGE_SIZE);
>
> return 0;
> }
>
> -target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env, target_ulong vaddr)
> +target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env,
> + target_ulong vaddr)
> {
> target_ulong raddr;
> int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> @@ -509,7 +511,7 @@ static void do_program_interrupt(CPUS390XState *env)
> break;
> }
>
> - qemu_log("%s: code=0x%x ilc=%d\n", __FUNCTION__, env->int_pgm_code, ilc);
> + qemu_log("%s: code=0x%x ilc=%d\n", __func__, env->int_pgm_code, ilc);
>
> lowcore = cpu_physical_memory_map(env->psa, &len, 1);
>
> @@ -522,7 +524,7 @@ static void do_program_interrupt(CPUS390XState *env)
>
> cpu_physical_memory_unmap(lowcore, len, 1, len);
>
> - DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
> + DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
> env->int_pgm_code, ilc, env->psw.mask,
> env->psw.addr);
>
> @@ -565,15 +567,15 @@ static void do_ext_interrupt(CPUS390XState *env)
> env->pending_int &= ~INTERRUPT_EXT;
> }
>
> - DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
> + DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
> env->psw.mask, env->psw.addr);
>
> load_psw(env, mask, addr);
> }
>
> -void do_interrupt (CPUS390XState *env)
> +void do_interrupt(CPUS390XState *env)
> {
> - qemu_log("%s: %d at pc=%" PRIx64 "\n", __FUNCTION__, env->exception_index,
> + qemu_log("%s: %d at pc=%" PRIx64 "\n", __func__, env->exception_index,
> env->psw.addr);
>
> s390_add_running_cpu(env);
> diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
> index abc35dd..195e93e 100644
> --- a/target-s390x/op_helper.c
> +++ b/target-s390x/op_helper.c
> @@ -31,13 +31,13 @@
> #include <linux/kvm.h>
> #endif
>
> -#if !defined (CONFIG_USER_ONLY)
> +#if !defined(CONFIG_USER_ONLY)
> #include "sysemu.h"
> #endif
>
> /*****************************************************************************/
> /* Softmmu support */
> -#if !defined (CONFIG_USER_ONLY)
> +#if !defined(CONFIG_USER_ONLY)
> #include "softmmu_exec.h"
>
> #define MMUSUFFIX _mmu
> @@ -95,7 +95,7 @@ void tlb_fill(CPUS390XState *env1, target_ulong addr, int is_write, int mmu_idx,
> /* raise an exception */
> void HELPER(exception)(uint32_t excp)
> {
> - HELPER_LOG("%s: exception %d\n", __FUNCTION__, excp);
> + HELPER_LOG("%s: exception %d\n", __func__, excp);
> env->exception_index = excp;
> cpu_loop_exit(env);
> }
> @@ -164,7 +164,7 @@ uint32_t HELPER(nc)(uint32_t l, uint64_t dest, uint64_t src)
> uint32_t cc = 0;
>
> HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
> - __FUNCTION__, l, dest, src);
> + __func__, l, dest, src);
> for (i = 0; i <= l; i++) {
> x = ldub(dest + i) & ldub(src + i);
> if (x) {
> @@ -183,7 +183,7 @@ uint32_t HELPER(xc)(uint32_t l, uint64_t dest, uint64_t src)
> uint32_t cc = 0;
>
> HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
> - __FUNCTION__, l, dest, src);
> + __func__, l, dest, src);
>
> #ifndef CONFIG_USER_ONLY
> /* xor with itself is the same as memset(0) */
> @@ -217,7 +217,7 @@ uint32_t HELPER(oc)(uint32_t l, uint64_t dest, uint64_t src)
> uint32_t cc = 0;
>
> HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
> - __FUNCTION__, l, dest, src);
> + __func__, l, dest, src);
> for (i = 0; i <= l; i++) {
> x = ldub(dest + i) | ldub(src + i);
> if (x) {
> @@ -236,7 +236,7 @@ void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
> uint32_t l_64 = (l + 1) / 8;
>
> HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
> - __FUNCTION__, l, dest, src);
> + __func__, l, dest, src);
>
> #ifndef CONFIG_USER_ONLY
> if ((l > 32) &&
> @@ -278,10 +278,11 @@ void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
> uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
> {
> int i;
> - unsigned char x,y;
> + unsigned char x, y;
> uint32_t cc;
> +
> HELPER_LOG("%s l %d s1 %" PRIx64 " s2 %" PRIx64 "\n",
> - __FUNCTION__, l, s1, s2);
> + __func__, l, s1, s2);
> for (i = 0; i <= l; i++) {
> x = ldub(s1 + i);
> y = ldub(s2 + i);
> @@ -295,7 +296,7 @@ uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
> }
> }
> cc = 0;
> -done:
> + done:
> HELPER_LOG("\n");
> return cc;
> }
> @@ -303,9 +304,10 @@ done:
> /* compare logical under mask */
> uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
> {
> - uint8_t r,d;
> + uint8_t r, d;
> uint32_t cc;
> - HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%" PRIx64 "\n", __FUNCTION__, r1,
> +
> + HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%" PRIx64 "\n", __func__, r1,
> mask, addr);
> cc = 0;
> while (mask) {
> @@ -313,7 +315,7 @@ uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
> d = ldub(addr);
> r = (r1 & 0xff000000UL) >> 24;
> HELPER_LOG("mask 0x%x %02x/%02x (0x%" PRIx64 ") ", mask, r, d,
> - addr);
> + addr);
> if (r < d) {
> cc = 1;
> break;
> @@ -334,7 +336,8 @@ uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
> void HELPER(stcm)(uint32_t r1, uint32_t mask, uint64_t addr)
> {
> uint8_t r;
> - HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%lx\n", __FUNCTION__, r1, mask,
> +
> + HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%lx\n", __func__, r1, mask,
> addr);
> while (mask) {
> if (mask & 8) {
> @@ -355,6 +358,7 @@ void HELPER(mlg)(uint32_t r1, uint64_t v2)
> #if HOST_LONG_BITS == 64 && defined(__GNUC__)
> /* assuming 64-bit hosts have __uint128_t */
> __uint128_t res = (__uint128_t)env->regs[r1 + 1];
> +
> res *= (__uint128_t)v2;
> env->regs[r1] = (uint64_t)(res >> 64);
> env->regs[r1 + 1] = (uint64_t)res;
> @@ -370,18 +374,18 @@ void HELPER(dlg)(uint32_t r1, uint64_t v2)
>
> if (!env->regs[r1]) {
> /* 64 -> 64/64 case */
> - env->regs[r1] = env->regs[r1+1] % divisor;
> - env->regs[r1+1] = env->regs[r1+1] / divisor;
> + env->regs[r1] = env->regs[r1 + 1] % divisor;
> + env->regs[r1 + 1] = env->regs[r1 + 1] / divisor;
> return;
> } else {
> -
> #if HOST_LONG_BITS == 64 && defined(__GNUC__)
> /* assuming 64-bit hosts have __uint128_t */
> __uint128_t dividend = (((__uint128_t)env->regs[r1]) << 64) |
> - (env->regs[r1+1]);
> + (env->regs[r1 + 1]);
> __uint128_t quotient = dividend / divisor;
> - env->regs[r1+1] = quotient;
> __uint128_t remainder = dividend % divisor;
> +
> + env->regs[r1 + 1] = quotient;
> env->regs[r1] = remainder;
> #else
> /* 32-bit hosts would need special wrapper functionality - just abort if
> @@ -431,7 +435,7 @@ uint32_t HELPER(srst)(uint32_t c, uint32_t r1, uint32_t r2)
> uint64_t str = get_address_31fix(r2);
> uint64_t end = get_address_31fix(r1);
>
> - HELPER_LOG("%s: c %d *r1 0x%" PRIx64 " *r2 0x%" PRIx64 "\n", __FUNCTION__,
> + HELPER_LOG("%s: c %d *r1 0x%" PRIx64 " *r2 0x%" PRIx64 "\n", __func__,
> c, env->regs[r1], env->regs[r2]);
>
> for (i = str; i != end; i++) {
> @@ -452,11 +456,12 @@ uint32_t HELPER(clst)(uint32_t c, uint32_t r1, uint32_t r2)
> uint64_t s2 = get_address_31fix(r2);
> uint8_t v1, v2;
> uint32_t cc;
> +
> c = c & 0xff;
> #ifdef CONFIG_USER_ONLY
> if (!c) {
> HELPER_LOG("%s: comparing '%s' and '%s'\n",
> - __FUNCTION__, (char*)g2h(s1), (char*)g2h(s2));
> + __func__, (char *)g2h(s1), (char *)g2h(s2));
> }
> #endif
> for (;;) {
> @@ -501,10 +506,11 @@ void HELPER(mvst)(uint32_t c, uint32_t r1, uint32_t r2)
> uint64_t dest = get_address_31fix(r1);
> uint64_t src = get_address_31fix(r2);
> uint8_t v;
> +
> c = c & 0xff;
> #ifdef CONFIG_USER_ONLY
> if (!c) {
> - HELPER_LOG("%s: copy '%s' to 0x%lx\n", __FUNCTION__, (char*)g2h(src),
> + HELPER_LOG("%s: copy '%s' to 0x%lx\n", __func__, (char *)g2h(src),
> dest);
> }
> #endif
> @@ -526,6 +532,7 @@ uint32_t HELPER(csg)(uint32_t r1, uint64_t a2, uint32_t r3)
> /* FIXME: locking? */
> uint32_t cc;
> uint64_t v2 = ldq(a2);
> +
> if (env->regs[r1] == v2) {
> cc = 0;
> stq(a2, env->regs[r3]);
> @@ -564,8 +571,9 @@ uint32_t HELPER(cs)(uint32_t r1, uint64_t a2, uint32_t r3)
> {
> /* FIXME: locking? */
> uint32_t cc;
> - HELPER_LOG("%s: r1 %d a2 0x%lx r3 %d\n", __FUNCTION__, r1, a2, r3);
> uint32_t v2 = ldl(a2);
> +
> + HELPER_LOG("%s: r1 %d a2 0x%lx r3 %d\n", __func__, r1, a2, r3);
> if (((uint32_t)env->regs[r1]) == v2) {
> cc = 0;
> stl(a2, (uint32_t)env->regs[r3]);
> @@ -612,14 +620,16 @@ static uint32_t helper_icm(uint32_t r1, uint64_t address, uint32_t mask)
> it does not change the program counter
> in other words: tricky...
> currently implemented by interpreting the cases it is most commonly used in
> - */
> +*/
> uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
> {
> uint16_t insn = lduw_code(addr);
> - HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __FUNCTION__, v1, addr,
> - insn);
> +
> + HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr,
> + insn);
> if ((insn & 0xf0ff) == 0xd000) {
> uint32_t l, insn2, b1, b2, d1, d2;
> +
> l = v1 & 0xff;
> insn2 = ldl_code(addr + 2);
> b1 = (insn2 >> 28) & 0xf;
> @@ -645,13 +655,14 @@ uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
> }
> } else if ((insn & 0xff00) == 0x0a00) {
> /* supervisor call */
> - HELPER_LOG("%s: svc %ld via execute\n", __FUNCTION__, (insn|v1) & 0xff);
> + HELPER_LOG("%s: svc %ld via execute\n", __func__, (insn | v1) & 0xff);
> env->psw.addr = ret - 4;
> - env->int_svc_code = (insn|v1) & 0xff;
> + env->int_svc_code = (insn | v1) & 0xff;
> env->int_svc_ilc = 4;
> helper_exception(EXCP_SVC);
> } else if ((insn & 0xff00) == 0xbf00) {
> uint32_t insn2, r1, r3, b2, d2;
> +
> insn2 = ldl_code(addr + 2);
> r1 = (insn2 >> 20) & 0xf;
> r3 = (insn2 >> 16) & 0xf;
> @@ -659,7 +670,7 @@ uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
> d2 = insn2 & 0xfff;
> cc = helper_icm(r1, get_address(0, b2, d2), r3);
> } else {
> -abort:
> + abort:
> cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n",
> insn);
> }
> @@ -689,7 +700,7 @@ int32_t HELPER(nabs_i32)(int32_t val)
> /* absolute value 64-bit */
> uint64_t HELPER(abs_i64)(int64_t val)
> {
> - HELPER_LOG("%s: val 0x%" PRIx64 "\n", __FUNCTION__, val);
> + HELPER_LOG("%s: val 0x%" PRIx64 "\n", __func__, val);
>
> if (val < 0) {
> return -val;
> @@ -774,9 +785,9 @@ void HELPER(ipm)(uint32_t cc, uint32_t r1)
> uint64_t r = env->regs[r1];
>
> r &= 0xffffffff00ffffffULL;
> - r |= (cc << 28) | ( (env->psw.mask >> 40) & 0xf );
> + r |= (cc << 28) | ((env->psw.mask >> 40) & 0xf);
> env->regs[r1] = r;
> - HELPER_LOG("%s: cc %d psw.mask 0x%lx r1 0x%lx\n", __FUNCTION__,
> + HELPER_LOG("%s: cc %d psw.mask 0x%lx r1 0x%lx\n", __func__,
> cc, env->psw.mask, r);
> }
>
> @@ -908,7 +919,7 @@ uint32_t HELPER(clcle)(uint32_t r1, uint64_t a2, uint32_t r3)
> uint64_t srclen = env->regs[r3 + 1];
> uint64_t src = get_address_31fix(r3);
> uint8_t pad = a2 & 0xff;
> - uint8_t v1 = 0,v2 = 0;
> + uint8_t v1 = 0, v2 = 0;
> uint32_t cc = 0;
>
> if (!(destlen || srclen)) {
> @@ -1036,7 +1047,7 @@ static uint32_t set_cc_nz_f128(float128 v)
> /* convert 32-bit int to 64-bit float */
> void HELPER(cdfbr)(uint32_t f1, int32_t v2)
> {
> - HELPER_LOG("%s: converting %d to f%d\n", __FUNCTION__, v2, f1);
> + HELPER_LOG("%s: converting %d to f%d\n", __func__, v2, f1);
> env->fregs[f1].d = int32_to_float64(v2, &env->fpu_status);
> }
>
> @@ -1044,6 +1055,7 @@ void HELPER(cdfbr)(uint32_t f1, int32_t v2)
> void HELPER(cxfbr)(uint32_t f1, int32_t v2)
> {
> CPU_QuadU v1;
> +
> v1.q = int32_to_float128(v2, &env->fpu_status);
> env->fregs[f1].ll = v1.ll.upper;
> env->fregs[f1 + 2].ll = v1.ll.lower;
> @@ -1052,14 +1064,14 @@ void HELPER(cxfbr)(uint32_t f1, int32_t v2)
> /* convert 64-bit int to 32-bit float */
> void HELPER(cegbr)(uint32_t f1, int64_t v2)
> {
> - HELPER_LOG("%s: converting %ld to f%d\n", __FUNCTION__, v2, f1);
> + HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
> env->fregs[f1].l.upper = int64_to_float32(v2, &env->fpu_status);
> }
>
> /* convert 64-bit int to 64-bit float */
> void HELPER(cdgbr)(uint32_t f1, int64_t v2)
> {
> - HELPER_LOG("%s: converting %ld to f%d\n", __FUNCTION__, v2, f1);
> + HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
> env->fregs[f1].d = int64_to_float64(v2, &env->fpu_status);
> }
>
> @@ -1067,8 +1079,9 @@ void HELPER(cdgbr)(uint32_t f1, int64_t v2)
> void HELPER(cxgbr)(uint32_t f1, int64_t v2)
> {
> CPU_QuadU x1;
> +
> x1.q = int64_to_float128(v2, &env->fpu_status);
> - HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __FUNCTION__, v2,
> + HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __func__, v2,
> x1.ll.upper, x1.ll.lower);
> env->fregs[f1].ll = x1.ll.upper;
> env->fregs[f1 + 2].ll = x1.ll.lower;
> @@ -1078,7 +1091,7 @@ void HELPER(cxgbr)(uint32_t f1, int64_t v2)
> void HELPER(cefbr)(uint32_t f1, int32_t v2)
> {
> env->fregs[f1].l.upper = int32_to_float32(v2, &env->fpu_status);
> - HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __FUNCTION__, v2,
> + HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __func__, v2,
> env->fregs[f1].l.upper, f1);
> }
>
> @@ -1088,7 +1101,7 @@ uint32_t HELPER(aebr)(uint32_t f1, uint32_t f2)
> env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
> env->fregs[f2].l.upper,
> &env->fpu_status);
> - HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __FUNCTION__,
> + HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
> env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
>
> return set_cc_nz_f32(env->fregs[f1].l.upper);
> @@ -1099,7 +1112,7 @@ uint32_t HELPER(adbr)(uint32_t f1, uint32_t f2)
> {
> env->fregs[f1].d = float64_add(env->fregs[f1].d, env->fregs[f2].d,
> &env->fpu_status);
> - HELPER_LOG("%s: adding 0x%ld resulting in 0x%ld in f%d\n", __FUNCTION__,
> + HELPER_LOG("%s: adding 0x%ld resulting in 0x%ld in f%d\n", __func__,
> env->fregs[f2].d, env->fregs[f1].d, f1);
>
> return set_cc_nz_f64(env->fregs[f1].d);
> @@ -1111,7 +1124,7 @@ uint32_t HELPER(sebr)(uint32_t f1, uint32_t f2)
> env->fregs[f1].l.upper = float32_sub(env->fregs[f1].l.upper,
> env->fregs[f2].l.upper,
> &env->fpu_status);
> - HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __FUNCTION__,
> + HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
> env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
>
> return set_cc_nz_f32(env->fregs[f1].l.upper);
> @@ -1123,7 +1136,7 @@ uint32_t HELPER(sdbr)(uint32_t f1, uint32_t f2)
> env->fregs[f1].d = float64_sub(env->fregs[f1].d, env->fregs[f2].d,
> &env->fpu_status);
> HELPER_LOG("%s: subtracting 0x%ld resulting in 0x%ld in f%d\n",
> - __FUNCTION__, env->fregs[f2].d, env->fregs[f1].d, f1);
> + __func__, env->fregs[f2].d, env->fregs[f1].d, f1);
>
> return set_cc_nz_f64(env->fregs[f1].d);
> }
> @@ -1140,12 +1153,13 @@ void HELPER(debr)(uint32_t f1, uint32_t f2)
> void HELPER(dxbr)(uint32_t f1, uint32_t f2)
> {
> CPU_QuadU v1;
> + CPU_QuadU v2;
> + CPU_QuadU res;
> +
> v1.ll.upper = env->fregs[f1].ll;
> v1.ll.lower = env->fregs[f1 + 2].ll;
> - CPU_QuadU v2;
> v2.ll.upper = env->fregs[f2].ll;
> v2.ll.lower = env->fregs[f2 + 2].ll;
> - CPU_QuadU res;
> res.q = float128_div(v1.q, v2.q, &env->fpu_status);
> env->fregs[f1].ll = res.ll.upper;
> env->fregs[f1 + 2].ll = res.ll.lower;
> @@ -1162,12 +1176,13 @@ void HELPER(mdbr)(uint32_t f1, uint32_t f2)
> void HELPER(mxbr)(uint32_t f1, uint32_t f2)
> {
> CPU_QuadU v1;
> + CPU_QuadU v2;
> + CPU_QuadU res;
> +
> v1.ll.upper = env->fregs[f1].ll;
> v1.ll.lower = env->fregs[f1 + 2].ll;
> - CPU_QuadU v2;
> v2.ll.upper = env->fregs[f2].ll;
> v2.ll.lower = env->fregs[f2 + 2].ll;
> - CPU_QuadU res;
> res.q = float128_mul(v1.q, v2.q, &env->fpu_status);
> env->fregs[f1].ll = res.ll.upper;
> env->fregs[f1 + 2].ll = res.ll.lower;
> @@ -1184,16 +1199,18 @@ void HELPER(ldebr)(uint32_t r1, uint32_t r2)
> void HELPER(ldxbr)(uint32_t f1, uint32_t f2)
> {
> CPU_QuadU x2;
> +
> x2.ll.upper = env->fregs[f2].ll;
> x2.ll.lower = env->fregs[f2 + 2].ll;
> env->fregs[f1].d = float128_to_float64(x2.q, &env->fpu_status);
> - HELPER_LOG("%s: to 0x%ld\n", __FUNCTION__, env->fregs[f1].d);
> + HELPER_LOG("%s: to 0x%ld\n", __func__, env->fregs[f1].d);
> }
>
> /* convert 64-bit float to 128-bit float */
> void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
> {
> CPU_QuadU res;
> +
> res.q = float64_to_float128(env->fregs[f2].d, &env->fpu_status);
> env->fregs[f1].ll = res.ll.upper;
> env->fregs[f1 + 2].ll = res.ll.lower;
> @@ -1203,6 +1220,7 @@ void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
> void HELPER(ledbr)(uint32_t f1, uint32_t f2)
> {
> float64 d2 = env->fregs[f2].d;
> +
> env->fregs[f1].l.upper = float64_to_float32(d2, &env->fpu_status);
> }
>
> @@ -1210,10 +1228,11 @@ void HELPER(ledbr)(uint32_t f1, uint32_t f2)
> void HELPER(lexbr)(uint32_t f1, uint32_t f2)
> {
> CPU_QuadU x2;
> +
> x2.ll.upper = env->fregs[f2].ll;
> x2.ll.lower = env->fregs[f2 + 2].ll;
> env->fregs[f1].l.upper = float128_to_float32(x2.q, &env->fpu_status);
> - HELPER_LOG("%s: to 0x%d\n", __FUNCTION__, env->fregs[f1].l.upper);
> + HELPER_LOG("%s: to 0x%d\n", __func__, env->fregs[f1].l.upper);
> }
>
> /* absolute value of 32-bit float */
> @@ -1221,6 +1240,7 @@ uint32_t HELPER(lpebr)(uint32_t f1, uint32_t f2)
> {
> float32 v1;
> float32 v2 = env->fregs[f2].d;
> +
> v1 = float32_abs(v2);
> env->fregs[f1].d = v1;
> return set_cc_nz_f32(v1);
> @@ -1231,6 +1251,7 @@ uint32_t HELPER(lpdbr)(uint32_t f1, uint32_t f2)
> {
> float64 v1;
> float64 v2 = env->fregs[f2].d;
> +
> v1 = float64_abs(v2);
> env->fregs[f1].d = v1;
> return set_cc_nz_f64(v1);
> @@ -1241,6 +1262,7 @@ uint32_t HELPER(lpxbr)(uint32_t f1, uint32_t f2)
> {
> CPU_QuadU v1;
> CPU_QuadU v2;
> +
> v2.ll.upper = env->fregs[f2].ll;
> v2.ll.lower = env->fregs[f2 + 2].ll;
> v1.q = float128_abs(v2.q);
> @@ -1267,6 +1289,7 @@ uint32_t HELPER(ltebr)(uint32_t f1, uint32_t f2)
> uint32_t HELPER(ltxbr)(uint32_t f1, uint32_t f2)
> {
> CPU_QuadU x;
> +
> x.ll.upper = env->fregs[f2].ll;
> x.ll.lower = env->fregs[f2 + 2].ll;
> env->fregs[f1].ll = x.ll.upper;
> @@ -1294,6 +1317,7 @@ uint32_t HELPER(lcdbr)(uint32_t f1, uint32_t f2)
> uint32_t HELPER(lcxbr)(uint32_t f1, uint32_t f2)
> {
> CPU_QuadU x1, x2;
> +
> x2.ll.upper = env->fregs[f2].ll;
> x2.ll.lower = env->fregs[f2 + 2].ll;
> x1.q = float128_chs(x2.q);
> @@ -1307,8 +1331,9 @@ void HELPER(aeb)(uint32_t f1, uint32_t val)
> {
> float32 v1 = env->fregs[f1].l.upper;
> CPU_FloatU v2;
> +
> v2.l = val;
> - HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __FUNCTION__,
> + HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __func__,
> v1, f1, v2.f);
> env->fregs[f1].l.upper = float32_add(v1, v2.f, &env->fpu_status);
> }
> @@ -1318,8 +1343,9 @@ void HELPER(deb)(uint32_t f1, uint32_t val)
> {
> float32 v1 = env->fregs[f1].l.upper;
> CPU_FloatU v2;
> +
> v2.l = val;
> - HELPER_LOG("%s: dividing 0x%d from f%d by 0x%d\n", __FUNCTION__,
> + HELPER_LOG("%s: dividing 0x%d from f%d by 0x%d\n", __func__,
> v1, f1, v2.f);
> env->fregs[f1].l.upper = float32_div(v1, v2.f, &env->fpu_status);
> }
> @@ -1329,8 +1355,9 @@ void HELPER(meeb)(uint32_t f1, uint32_t val)
> {
> float32 v1 = env->fregs[f1].l.upper;
> CPU_FloatU v2;
> +
> v2.l = val;
> - HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __FUNCTION__,
> + HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __func__,
> v1, f1, v2.f);
> env->fregs[f1].l.upper = float32_mul(v1, v2.f, &env->fpu_status);
> }
> @@ -1340,7 +1367,8 @@ uint32_t HELPER(cebr)(uint32_t f1, uint32_t f2)
> {
> float32 v1 = env->fregs[f1].l.upper;
> float32 v2 = env->fregs[f2].l.upper;
> - HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __FUNCTION__,
> +
> + HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __func__,
> v1, f1, v2);
> return set_cc_f32(v1, v2);
> }
> @@ -1350,7 +1378,8 @@ uint32_t HELPER(cdbr)(uint32_t f1, uint32_t f2)
> {
> float64 v1 = env->fregs[f1].d;
> float64 v2 = env->fregs[f2].d;
> - HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __FUNCTION__,
> +
> + HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __func__,
> v1, f1, v2);
> return set_cc_f64(v1, v2);
> }
> @@ -1359,14 +1388,15 @@ uint32_t HELPER(cdbr)(uint32_t f1, uint32_t f2)
> uint32_t HELPER(cxbr)(uint32_t f1, uint32_t f2)
> {
> CPU_QuadU v1;
> + CPU_QuadU v2;
> +
> v1.ll.upper = env->fregs[f1].ll;
> v1.ll.lower = env->fregs[f1 + 2].ll;
> - CPU_QuadU v2;
> v2.ll.upper = env->fregs[f2].ll;
> v2.ll.lower = env->fregs[f2 + 2].ll;
>
> return float_comp_to_cc(float128_compare_quiet(v1.q, v2.q,
> - &env->fpu_status));
> + &env->fpu_status));
> }
>
> /* 64-bit FP compare RM */
> @@ -1374,8 +1404,9 @@ uint32_t HELPER(cdb)(uint32_t f1, uint64_t a2)
> {
> float64 v1 = env->fregs[f1].d;
> CPU_DoubleU v2;
> +
> v2.ll = ldq(a2);
> - HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __FUNCTION__, v1,
> + HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __func__, v1,
> f1, v2.d);
> return set_cc_f64(v1, v2.d);
> }
> @@ -1385,8 +1416,9 @@ uint32_t HELPER(adb)(uint32_t f1, uint64_t a2)
> {
> float64 v1 = env->fregs[f1].d;
> CPU_DoubleU v2;
> +
> v2.ll = ldq(a2);
> - HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __FUNCTION__,
> + HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __func__,
> v1, f1, v2.d);
> env->fregs[f1].d = v1 = float64_add(v1, v2.d, &env->fpu_status);
> return set_cc_nz_f64(v1);
> @@ -1397,6 +1429,7 @@ void HELPER(seb)(uint32_t f1, uint32_t val)
> {
> float32 v1 = env->fregs[f1].l.upper;
> CPU_FloatU v2;
> +
> v2.l = val;
> env->fregs[f1].l.upper = float32_sub(v1, v2.f, &env->fpu_status);
> }
> @@ -1406,6 +1439,7 @@ uint32_t HELPER(sdb)(uint32_t f1, uint64_t a2)
> {
> float64 v1 = env->fregs[f1].d;
> CPU_DoubleU v2;
> +
> v2.ll = ldq(a2);
> env->fregs[f1].d = v1 = float64_sub(v1, v2.d, &env->fpu_status);
> return set_cc_nz_f64(v1);
> @@ -1416,8 +1450,9 @@ void HELPER(mdb)(uint32_t f1, uint64_t a2)
> {
> float64 v1 = env->fregs[f1].d;
> CPU_DoubleU v2;
> +
> v2.ll = ldq(a2);
> - HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __FUNCTION__,
> + HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __func__,
> v1, f1, v2.d);
> env->fregs[f1].d = float64_mul(v1, v2.d, &env->fpu_status);
> }
> @@ -1427,8 +1462,9 @@ void HELPER(ddb)(uint32_t f1, uint64_t a2)
> {
> float64 v1 = env->fregs[f1].d;
> CPU_DoubleU v2;
> +
> v2.ll = ldq(a2);
> - HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __FUNCTION__,
> + HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __func__,
> v1, f1, v2.d);
> env->fregs[f1].d = float64_div(v1, v2.d, &env->fpu_status);
> }
> @@ -1464,6 +1500,7 @@ static void set_round_mode(int m3)
> uint32_t HELPER(cgebr)(uint32_t r1, uint32_t f2, uint32_t m3)
> {
> float32 v2 = env->fregs[f2].l.upper;
> +
> set_round_mode(m3);
> env->regs[r1] = float32_to_int64(v2, &env->fpu_status);
> return set_cc_nz_f32(v2);
> @@ -1473,6 +1510,7 @@ uint32_t HELPER(cgebr)(uint32_t r1, uint32_t f2, uint32_t m3)
> uint32_t HELPER(cgdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
> {
> float64 v2 = env->fregs[f2].d;
> +
> set_round_mode(m3);
> env->regs[r1] = float64_to_int64(v2, &env->fpu_status);
> return set_cc_nz_f64(v2);
> @@ -1482,6 +1520,7 @@ uint32_t HELPER(cgdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
> uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
> {
> CPU_QuadU v2;
> +
> v2.ll.upper = env->fregs[f2].ll;
> v2.ll.lower = env->fregs[f2 + 2].ll;
> set_round_mode(m3);
> @@ -1501,9 +1540,10 @@ uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
> uint32_t HELPER(cfebr)(uint32_t r1, uint32_t f2, uint32_t m3)
> {
> float32 v2 = env->fregs[f2].l.upper;
> +
> set_round_mode(m3);
> env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
> - float32_to_int32(v2, &env->fpu_status);
> + float32_to_int32(v2, &env->fpu_status);
> return set_cc_nz_f32(v2);
> }
>
> @@ -1511,9 +1551,10 @@ uint32_t HELPER(cfebr)(uint32_t r1, uint32_t f2, uint32_t m3)
> uint32_t HELPER(cfdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
> {
> float64 v2 = env->fregs[f2].d;
> +
> set_round_mode(m3);
> env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
> - float64_to_int32(v2, &env->fpu_status);
> + float64_to_int32(v2, &env->fpu_status);
> return set_cc_nz_f64(v2);
> }
>
> @@ -1521,10 +1562,11 @@ uint32_t HELPER(cfdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
> uint32_t HELPER(cfxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
> {
> CPU_QuadU v2;
> +
> v2.ll.upper = env->fregs[f2].ll;
> v2.ll.lower = env->fregs[f2 + 2].ll;
> env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
> - float128_to_int32(v2.q, &env->fpu_status);
> + float128_to_int32(v2.q, &env->fpu_status);
> return set_cc_nz_f128(v2.q);
> }
>
> @@ -1544,6 +1586,7 @@ void HELPER(lzdr)(uint32_t f1)
> void HELPER(lzxr)(uint32_t f1)
> {
> CPU_QuadU x;
> +
> x.q = float64_to_float128(float64_zero, &env->fpu_status);
> env->fregs[f1].ll = x.ll.upper;
> env->fregs[f1 + 1].ll = x.ll.lower;
> @@ -1553,12 +1596,13 @@ void HELPER(lzxr)(uint32_t f1)
> uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
> {
> CPU_QuadU v1;
> + CPU_QuadU v2;
> + CPU_QuadU res;
> +
> v1.ll.upper = env->fregs[f1].ll;
> v1.ll.lower = env->fregs[f1 + 2].ll;
> - CPU_QuadU v2;
> v2.ll.upper = env->fregs[f2].ll;
> v2.ll.lower = env->fregs[f2 + 2].ll;
> - CPU_QuadU res;
> res.q = float128_sub(v1.q, v2.q, &env->fpu_status);
> env->fregs[f1].ll = res.ll.upper;
> env->fregs[f1 + 2].ll = res.ll.lower;
> @@ -1569,12 +1613,13 @@ uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
> uint32_t HELPER(axbr)(uint32_t f1, uint32_t f2)
> {
> CPU_QuadU v1;
> + CPU_QuadU v2;
> + CPU_QuadU res;
> +
> v1.ll.upper = env->fregs[f1].ll;
> v1.ll.lower = env->fregs[f1 + 2].ll;
> - CPU_QuadU v2;
> v2.ll.upper = env->fregs[f2].ll;
> v2.ll.lower = env->fregs[f2 + 2].ll;
> - CPU_QuadU res;
> res.q = float128_add(v1.q, v2.q, &env->fpu_status);
> env->fregs[f1].ll = res.ll.upper;
> env->fregs[f1 + 2].ll = res.ll.lower;
> @@ -1599,8 +1644,9 @@ void HELPER(ddbr)(uint32_t f1, uint32_t f2)
> /* 64-bit FP multiply and add RM */
> void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
> {
> - HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __FUNCTION__, f1, a2, f3);
> CPU_DoubleU v2;
> +
> + HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __func__, f1, a2, f3);
> v2.ll = ldq(a2);
> env->fregs[f1].d = float64_add(env->fregs[f1].d,
> float64_mul(v2.d, env->fregs[f3].d,
> @@ -1611,7 +1657,7 @@ void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
> /* 64-bit FP multiply and add RR */
> void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
> {
> - HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __FUNCTION__, f1, f2, f3);
> + HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
> env->fregs[f1].d = float64_add(float64_mul(env->fregs[f2].d,
> env->fregs[f3].d,
> &env->fpu_status),
> @@ -1621,7 +1667,7 @@ void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
> /* 64-bit FP multiply and subtract RR */
> void HELPER(msdbr)(uint32_t f1, uint32_t f3, uint32_t f2)
> {
> - HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __FUNCTION__, f1, f2, f3);
> + HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
> env->fregs[f1].d = float64_sub(float64_mul(env->fregs[f2].d,
> env->fregs[f3].d,
> &env->fpu_status),
> @@ -1642,6 +1688,7 @@ void HELPER(maebr)(uint32_t f1, uint32_t f3, uint32_t f2)
> void HELPER(ldeb)(uint32_t f1, uint64_t a2)
> {
> uint32_t v2;
> +
> v2 = ldl(a2);
> env->fregs[f1].d = float32_to_float64(v2,
> &env->fpu_status);
> @@ -1651,8 +1698,9 @@ void HELPER(ldeb)(uint32_t f1, uint64_t a2)
> void HELPER(lxdb)(uint32_t f1, uint64_t a2)
> {
> CPU_DoubleU v2;
> - v2.ll = ldq(a2);
> CPU_QuadU v1;
> +
> + v2.ll = ldq(a2);
> v1.q = float64_to_float128(v2.d, &env->fpu_status);
> env->fregs[f1].ll = v1.ll.upper;
> env->fregs[f1 + 2].ll = v1.ll.lower;
> @@ -1665,7 +1713,7 @@ uint32_t HELPER(tceb)(uint32_t f1, uint64_t m2)
> int neg = float32_is_neg(v1);
> uint32_t cc = 0;
>
> - HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __FUNCTION__, (long)v1, m2, neg);
> + HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, (long)v1, m2, neg);
> if ((float32_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
> (float32_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
> (float32_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
> @@ -1687,7 +1735,7 @@ uint32_t HELPER(tcdb)(uint32_t f1, uint64_t m2)
> int neg = float64_is_neg(v1);
> uint32_t cc = 0;
>
> - HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __FUNCTION__, v1, m2, neg);
> + HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, v1, m2, neg);
> if ((float64_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
> (float64_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
> (float64_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
> @@ -1706,10 +1754,12 @@ uint32_t HELPER(tcxb)(uint32_t f1, uint64_t m2)
> {
> CPU_QuadU v1;
> uint32_t cc = 0;
> + int neg;
> +
> v1.ll.upper = env->fregs[f1].ll;
> v1.ll.lower = env->fregs[f1 + 2].ll;
>
> - int neg = float128_is_neg(v1.q);
> + neg = float128_is_neg(v1.q);
> if ((float128_is_zero(v1.q) && (m2 & (1 << (11-neg)))) ||
> (float128_is_infinity(v1.q) && (m2 & (1 << (5-neg)))) ||
> (float128_is_any_nan(v1.q) && (m2 & (1 << (3-neg)))) ||
> @@ -1787,7 +1837,7 @@ void HELPER(cksm)(uint32_t r1, uint32_t r2)
>
> /* store result */
> env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
> - ((uint32_t)cksm + (cksm >> 32));
> + ((uint32_t)cksm + (cksm >> 32));
> }
>
> static inline uint32_t cc_calc_ltgt_32(CPUS390XState *env, int32_t src,
> @@ -1848,10 +1898,12 @@ static inline uint32_t cc_calc_ltugtu_64(CPUS390XState *env, uint64_t src,
> }
> }
>
> -static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val, uint32_t mask)
> +static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val,
> + uint32_t mask)
> {
> - HELPER_LOG("%s: val 0x%x mask 0x%x\n", __FUNCTION__, val, mask);
> uint16_t r = val & mask;
> +
> + HELPER_LOG("%s: val 0x%x mask 0x%x\n", __func__, val, mask);
> if (r == 0 || mask == 0) {
> return 0;
> } else if (r == mask) {
> @@ -1862,10 +1914,12 @@ static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val, uint32_t
> }
>
> /* set condition code for test under mask */
> -static inline uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val, uint32_t mask)
> +static inline uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val,
> + uint32_t mask)
> {
> uint16_t r = val & mask;
> - HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __FUNCTION__, val, mask, r);
> +
> + HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __func__, val, mask, r);
> if (r == 0 || mask == 0) {
> return 0;
> } else if (r == mask) {
> @@ -1888,8 +1942,8 @@ static inline uint32_t cc_calc_nz(CPUS390XState *env, uint64_t dst)
> return !!dst;
> }
>
> -static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1, int64_t a2,
> - int64_t ar)
> +static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1,
> + int64_t a2, int64_t ar)
> {
> if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
> return 3; /* overflow */
> @@ -1904,8 +1958,8 @@ static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1, int64_t a2
> }
> }
>
> -static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1, uint64_t a2,
> - uint64_t ar)
> +static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1,
> + uint64_t a2, uint64_t ar)
> {
> if (ar == 0) {
> if (a1) {
> @@ -1915,15 +1969,15 @@ static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1, uint64_t
> }
> } else {
> if (ar < a1 || ar < a2) {
> - return 3;
> + return 3;
> } else {
> - return 1;
> + return 1;
> }
> }
> }
>
> -static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1, int64_t a2,
> - int64_t ar)
> +static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1,
> + int64_t a2, int64_t ar)
> {
> if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
> return 3; /* overflow */
> @@ -1938,8 +1992,8 @@ static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1, int64_t a2
> }
> }
>
> -static inline uint32_t cc_calc_subu_64(CPUS390XState *env, uint64_t a1, uint64_t a2,
> - uint64_t ar)
> +static inline uint32_t cc_calc_subu_64(CPUS390XState *env, uint64_t a1,
> + uint64_t a2, uint64_t ar)
> {
> if (ar == 0) {
> return 2;
> @@ -1982,8 +2036,8 @@ static inline uint32_t cc_calc_comp_64(CPUS390XState *env, int64_t dst)
> }
>
>
> -static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1, int32_t a2,
> - int32_t ar)
> +static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1,
> + int32_t a2, int32_t ar)
> {
> if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
> return 3; /* overflow */
> @@ -1998,26 +2052,26 @@ static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1, int32_t a2
> }
> }
>
> -static inline uint32_t cc_calc_addu_32(CPUS390XState *env, uint32_t a1, uint32_t a2,
> - uint32_t ar)
> +static inline uint32_t cc_calc_addu_32(CPUS390XState *env, uint32_t a1,
> + uint32_t a2, uint32_t ar)
> {
> if (ar == 0) {
> if (a1) {
> - return 2;
> + return 2;
> } else {
> - return 0;
> + return 0;
> }
> } else {
> if (ar < a1 || ar < a2) {
> - return 3;
> + return 3;
> } else {
> - return 1;
> + return 1;
> }
> }
> }
>
> -static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1, int32_t a2,
> - int32_t ar)
> +static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1,
> + int32_t a2, int32_t ar)
> {
> if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
> return 3; /* overflow */
> @@ -2032,8 +2086,8 @@ static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1, int32_t a2
> }
> }
>
> -static inline uint32_t cc_calc_subu_32(CPUS390XState *env, uint32_t a1, uint32_t a2,
> - uint32_t ar)
> +static inline uint32_t cc_calc_subu_32(CPUS390XState *env, uint32_t a1,
> + uint32_t a2, uint32_t ar)
> {
> if (ar == 0) {
> return 2;
> @@ -2076,11 +2130,12 @@ static inline uint32_t cc_calc_comp_32(CPUS390XState *env, int32_t dst)
> }
>
> /* calculate condition code for insert character under mask insn */
> -static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask, uint32_t val)
> +static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask,
> + uint32_t val)
> {
> - HELPER_LOG("%s: mask 0x%x val %d\n", __FUNCTION__, mask, val);
> uint32_t cc;
>
> + HELPER_LOG("%s: mask 0x%x val %d\n", __func__, mask, val);
> if (mask == 0xf) {
> if (!val) {
> return 0;
> @@ -2107,7 +2162,8 @@ static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask, uint32_
> return cc;
> }
>
> -static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src, uint64_t shift)
> +static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src,
> + uint64_t shift)
> {
> uint64_t mask = ((1ULL << shift) - 1ULL) << (64 - shift);
> uint64_t match, r;
> @@ -2136,8 +2192,8 @@ static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src, uint64_t s
> }
>
>
> -static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src,
> - uint64_t dst, uint64_t vr)
> +static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
> + uint64_t src, uint64_t dst, uint64_t vr)
> {
> uint32_t r = 0;
>
> @@ -2244,7 +2300,7 @@ static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t s
> cpu_abort(env, "Unknown CC operation: %s\n", cc_name(cc_op));
> }
>
> - HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __FUNCTION__,
> + HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__,
> cc_name(cc_op), src, dst, vr, r);
> return r;
> }
> @@ -2334,6 +2390,7 @@ void HELPER(tr)(uint32_t len, uint64_t array, uint64_t trans)
> for (i = 0; i <= len; i++) {
> uint8_t byte = ldub(array + i);
> uint8_t new_byte = ldub(trans + byte);
> +
> stb(array + i, new_byte);
> }
> }
> @@ -2363,7 +2420,7 @@ static void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
> }
>
> /*
> - * ret < 0 indicates program check, ret = 0,1,2,3 -> cc
> + * ret < 0 indicates program check, ret = 0, 1, 2, 3 -> cc
> */
> int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
> {
> @@ -2382,24 +2439,24 @@ int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
> return -PGM_SPECIFICATION;
> }
>
> - switch(code) {
> - case SCLP_CMDW_READ_SCP_INFO:
> - case SCLP_CMDW_READ_SCP_INFO_FORCED:
> - while ((ram_size >> (20 + shift)) > 65535) {
> - shift++;
> - }
> - stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
> - stb_phys(sccb + SCP_INCREMENT, 1 << shift);
> - stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
> + switch (code) {
> + case SCLP_CMDW_READ_SCP_INFO:
> + case SCLP_CMDW_READ_SCP_INFO_FORCED:
> + while ((ram_size >> (20 + shift)) > 65535) {
> + shift++;
> + }
> + stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
> + stb_phys(sccb + SCP_INCREMENT, 1 << shift);
> + stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
>
> - s390_sclp_extint(sccb & ~3);
> - break;
> - default:
> + s390_sclp_extint(sccb & ~3);
> + break;
> + default:
> #ifdef DEBUG_HELPER
> - printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
> + printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
> #endif
> - r = 3;
> - break;
> + r = 3;
> + break;
> }
>
> return r;
> @@ -2479,7 +2536,7 @@ static inline uint64_t clock_value(CPUS390XState *env)
> uint64_t time;
>
> time = env->tod_offset +
> - time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
> + time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
>
> return time;
> }
> @@ -2503,7 +2560,6 @@ uint32_t HELPER(stcke)(uint64_t a1)
> /* XXX programmable fields */
> stw(a1 + 17, 0);
>
> -
> return 0;
> }
>
> @@ -2584,7 +2640,7 @@ uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
> ebcdic_put(sysib.model, "QEMU ", 16);
> ebcdic_put(sysib.sequence, "QEMU ", 16);
> ebcdic_put(sysib.plant, "QEMU", 4);
> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
> } else if ((sel1 == 2) && (sel2 == 1)) {
> /* Basic Machine CPU */
> struct sysib_121 sysib;
> @@ -2594,7 +2650,7 @@ uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
> ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
> ebcdic_put(sysib.plant, "QEMU", 4);
> stw_p(&sysib.cpu_addr, env->cpu_num);
> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
> } else if ((sel1 == 2) && (sel2 == 2)) {
> /* Basic Machine CPUs */
> struct sysib_122 sysib;
> @@ -2606,68 +2662,68 @@ uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
> stw_p(&sysib.active_cpus, 1);
> stw_p(&sysib.standby_cpus, 0);
> stw_p(&sysib.reserved_cpus, 0);
> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
> } else {
> cc = 3;
> }
> break;
> case STSI_LEVEL_2:
> - {
> - if ((sel1 == 2) && (sel2 == 1)) {
> - /* LPAR CPU */
> - struct sysib_221 sysib;
> -
> - memset(&sysib, 0, sizeof(sysib));
> - /* XXX make different for different CPUs? */
> - ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
> - ebcdic_put(sysib.plant, "QEMU", 4);
> - stw_p(&sysib.cpu_addr, env->cpu_num);
> - stw_p(&sysib.cpu_id, 0);
> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
> - } else if ((sel1 == 2) && (sel2 == 2)) {
> - /* LPAR CPUs */
> - struct sysib_222 sysib;
> -
> - memset(&sysib, 0, sizeof(sysib));
> - stw_p(&sysib.lpar_num, 0);
> - sysib.lcpuc = 0;
> - /* XXX change when SMP comes */
> - stw_p(&sysib.total_cpus, 1);
> - stw_p(&sysib.conf_cpus, 1);
> - stw_p(&sysib.standby_cpus, 0);
> - stw_p(&sysib.reserved_cpus, 0);
> - ebcdic_put(sysib.name, "QEMU ", 8);
> - stl_p(&sysib.caf, 1000);
> - stw_p(&sysib.dedicated_cpus, 0);
> - stw_p(&sysib.shared_cpus, 0);
> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
> - } else {
> - cc = 3;
> + {
> + if ((sel1 == 2) && (sel2 == 1)) {
> + /* LPAR CPU */
> + struct sysib_221 sysib;
> +
> + memset(&sysib, 0, sizeof(sysib));
> + /* XXX make different for different CPUs? */
> + ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
> + ebcdic_put(sysib.plant, "QEMU", 4);
> + stw_p(&sysib.cpu_addr, env->cpu_num);
> + stw_p(&sysib.cpu_id, 0);
> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
> + } else if ((sel1 == 2) && (sel2 == 2)) {
> + /* LPAR CPUs */
> + struct sysib_222 sysib;
> +
> + memset(&sysib, 0, sizeof(sysib));
> + stw_p(&sysib.lpar_num, 0);
> + sysib.lcpuc = 0;
> + /* XXX change when SMP comes */
> + stw_p(&sysib.total_cpus, 1);
> + stw_p(&sysib.conf_cpus, 1);
> + stw_p(&sysib.standby_cpus, 0);
> + stw_p(&sysib.reserved_cpus, 0);
> + ebcdic_put(sysib.name, "QEMU ", 8);
> + stl_p(&sysib.caf, 1000);
> + stw_p(&sysib.dedicated_cpus, 0);
> + stw_p(&sysib.shared_cpus, 0);
> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
> + } else {
> + cc = 3;
> + }
> + break;
> }
> - break;
> - }
> case STSI_LEVEL_3:
> - {
> - if ((sel1 == 2) && (sel2 == 2)) {
> - /* VM CPUs */
> - struct sysib_322 sysib;
> -
> - memset(&sysib, 0, sizeof(sysib));
> - sysib.count = 1;
> - /* XXX change when SMP comes */
> - stw_p(&sysib.vm[0].total_cpus, 1);
> - stw_p(&sysib.vm[0].conf_cpus, 1);
> - stw_p(&sysib.vm[0].standby_cpus, 0);
> - stw_p(&sysib.vm[0].reserved_cpus, 0);
> - ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
> - stl_p(&sysib.vm[0].caf, 1000);
> - ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
> - } else {
> - cc = 3;
> + {
> + if ((sel1 == 2) && (sel2 == 2)) {
> + /* VM CPUs */
> + struct sysib_322 sysib;
> +
> + memset(&sysib, 0, sizeof(sysib));
> + sysib.count = 1;
> + /* XXX change when SMP comes */
> + stw_p(&sysib.vm[0].total_cpus, 1);
> + stw_p(&sysib.vm[0].conf_cpus, 1);
> + stw_p(&sysib.vm[0].standby_cpus, 0);
> + stw_p(&sysib.vm[0].reserved_cpus, 0);
> + ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
> + stl_p(&sysib.vm[0].caf, 1000);
> + ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
> + } else {
> + cc = 3;
> + }
> + break;
> }
> - break;
> - }
> case STSI_LEVEL_CURRENT:
> env->regs[0] = STSI_LEVEL_3;
> break;
> @@ -2781,6 +2837,7 @@ uint32_t HELPER(rrbe)(uint32_t r1, uint64_t r2)
> {
> uint8_t re;
> uint8_t key;
> +
> if (r2 > ram_size) {
> return 0;
> }
> @@ -2865,7 +2922,7 @@ static uint32_t mvc_asc(int64_t l, uint64_t a1, uint64_t mode1, uint64_t a2,
> uint32_t HELPER(mvcs)(uint64_t l, uint64_t a1, uint64_t a2)
> {
> HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
> - __FUNCTION__, l, a1, a2);
> + __func__, l, a1, a2);
>
> return mvc_asc(l, a1, PSW_ASC_SECONDARY, a2, PSW_ASC_PRIMARY);
> }
> @@ -2873,7 +2930,7 @@ uint32_t HELPER(mvcs)(uint64_t l, uint64_t a1, uint64_t a2)
> uint32_t HELPER(mvcp)(uint64_t l, uint64_t a1, uint64_t a2)
> {
> HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
> - __FUNCTION__, l, a1, a2);
> + __func__, l, a1, a2);
>
> return mvc_asc(l, a1, PSW_ASC_PRIMARY, a2, PSW_ASC_SECONDARY);
> }
> @@ -2883,9 +2940,9 @@ uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
> int cc = 0;
>
> HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
> - __FUNCTION__, order_code, r1, cpu_addr);
> + __func__, order_code, r1, cpu_addr);
>
> - /* Remember: Use "R1 or R1+1, whichever is the odd-numbered register"
> + /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
> as parameter (input). Status (output) is always R1. */
>
> switch (order_code) {
> @@ -2901,7 +2958,7 @@ uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
> env->regs[r1] &= 0xffffffff00000000ULL;
> cc = 1;
> break;
> -#if !defined (CONFIG_USER_ONLY)
> +#if !defined(CONFIG_USER_ONLY)
> case SIGP_RESTART:
> qemu_system_reset_request();
> cpu_loop_exit(env);
> @@ -2922,7 +2979,7 @@ uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
>
> void HELPER(sacf)(uint64_t a1)
> {
> - HELPER_LOG("%s: %16" PRIx64 "\n", __FUNCTION__, a1);
> + HELPER_LOG("%s: %16" PRIx64 "\n", __func__, a1);
>
> switch (a1 & 0xf00) {
> case 0x000:
> @@ -2953,13 +3010,13 @@ void HELPER(ipte)(uint64_t pte_addr, uint64_t vaddr)
> /* XXX broadcast to other CPUs */
>
> /* XXX Linux is nice enough to give us the exact pte address.
> - According to spec we'd have to find it out ourselves */
> + According to spec we'd have to find it out ourselves */
> /* XXX Linux is fine with overwriting the pte, the spec requires
> - us to only set the invalid bit */
> + us to only set the invalid bit */
> stq_phys(pte_addr, pte | _PAGE_INVALID);
>
> /* XXX we exploit the fact that Linux passes the exact virtual
> - address here - it's not obliged to! */
> + address here - it's not obliged to! */
> tlb_flush_page(env, page);
>
> /* XXX 31-bit hack */
> @@ -3008,7 +3065,8 @@ uint32_t HELPER(lra)(uint64_t addr, uint32_t r1)
> env->exception_index = old_exc;
>
> if (!(env->psw.mask & PSW_MASK_64)) {
> - env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | (ret & 0xffffffffULL);
> + env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
> + (ret & 0xffffffffULL);
> } else {
> env->regs[r1] = ret;
> }
> --
> 1.7.2.5
>
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 01/21] target-s390x: fix style
2012-09-03 4:31 ` Alexander Graf
@ 2012-09-03 19:10 ` Blue Swirl
2012-09-03 23:33 ` Alexander Graf
2012-09-04 14:54 ` Richard Henderson
0 siblings, 2 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-03 19:10 UTC (permalink / raw)
To: Alexander Graf, Richard Henderson; +Cc: qemu-devel qemu-devel
On Mon, Sep 3, 2012 at 4:31 AM, Alexander Graf <agraf@suse.de> wrote:
>
> On 02.09.2012, at 13:33, Blue Swirl wrote:
>
>> Before splitting op_helper.c and helper.c in the next patches,
>> fix style issues. No functional changes.
>>
>> Replace also GCC specific __FUNCTION__ with
>> standard __func__.
>>
>> Don't init static variable (cpu_s390x_init:inited) with 0.
>>
>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>
>
> Phew. Have you hooked up with Richard about these changes? He had quite a big rewrite of the s390 target in the works, and I don't want you guys to work needlessly on major conflicts :)
I missed that one. He's rewriting translate.c, while I'm mostly
touching op_helper.c. I'd expect it would be simpler for Richard to
rebase on my series, because they only change helper calls but don't
otherwise touch code. His series rearranges the code heavily and if I
rebased on that, it would probably make the patch conflicts harder to
resolve. What do you think?
>
>
> Alex
>
>> ---
>> target-s390x/helper.c | 96 +++++-----
>> target-s390x/op_helper.c | 438 ++++++++++++++++++++++++++--------------------
>> 2 files changed, 297 insertions(+), 237 deletions(-)
>>
>> diff --git a/target-s390x/helper.c b/target-s390x/helper.c
>> index d0a1180..d98e6d9 100644
>> --- a/target-s390x/helper.c
>> +++ b/target-s390x/helper.c
>> @@ -74,7 +74,7 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
>> {
>> S390CPU *cpu;
>> CPUS390XState *env;
>> - static int inited = 0;
>> + static int inited;
>>
>> cpu = S390_CPU(object_new(TYPE_S390_CPU));
>> env = &cpu->env;
>> @@ -91,25 +91,27 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
>>
>> #if defined(CONFIG_USER_ONLY)
>>
>> -void do_interrupt (CPUS390XState *env)
>> +void do_interrupt(CPUS390XState *env)
>> {
>> env->exception_index = -1;
>> }
>>
>> -int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
>> - int mmu_idx)
>> +int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
>> + int rw, int mmu_idx)
>> {
>> - /* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d\n",
>> - __FUNCTION__, address, rw, mmu_idx); */
>> + /* fprintf(stderr, "%s: address 0x%lx rw %d mmu_idx %d\n",
>> + __func__, address, rw, mmu_idx); */
>> env->exception_index = EXCP_ADDR;
>> - env->__excp_addr = address; /* FIXME: find out how this works on a real machine */
>> + /* FIXME: find out how this works on a real machine */
>> + env->__excp_addr = address;
>> return 1;
>> }
>>
>> #else /* !CONFIG_USER_ONLY */
>>
>> /* Ensure to exit the TB after this call! */
>> -static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilc)
>> +static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
>> + uint32_t ilc)
>> {
>> env->exception_index = EXCP_PGM;
>> env->int_pgm_code = code;
>> @@ -138,19 +140,20 @@ static int trans_bits(CPUS390XState *env, uint64_t mode)
>> return bits;
>> }
>>
>> -static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, uint64_t mode)
>> +static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
>> + uint64_t mode)
>> {
>> int ilc = ILC_LATER_INC_2;
>> int bits = trans_bits(env, mode) | 4;
>>
>> - DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
>> + DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
>>
>> stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
>> trigger_pgm_exception(env, PGM_PROTECTION, ilc);
>> }
>>
>> -static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type,
>> - uint64_t asc, int rw)
>> +static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
>> + uint32_t type, uint64_t asc, int rw)
>> {
>> int ilc = ILC_LATER;
>> int bits = trans_bits(env, asc);
>> @@ -160,26 +163,26 @@ static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t
>> ilc = 2;
>> }
>>
>> - DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
>> + DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
>>
>> stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
>> trigger_pgm_exception(env, type, ilc);
>> }
>>
>> -static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
>> - uint64_t asce, int level, target_ulong *raddr,
>> - int *flags, int rw)
>> +static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
>> + uint64_t asc, uint64_t asce, int level,
>> + target_ulong *raddr, int *flags, int rw)
>> {
>> uint64_t offs = 0;
>> uint64_t origin;
>> uint64_t new_asce;
>>
>> - PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __FUNCTION__, asce);
>> + PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);
>>
>> if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
>> ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
>> /* XXX different regions have different faults */
>> - DPRINTF("%s: invalid region\n", __FUNCTION__);
>> + DPRINTF("%s: invalid region\n", __func__);
>> trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
>> return -1;
>> }
>> @@ -222,7 +225,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t a
>>
>> new_asce = ldq_phys(origin + offs);
>> PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
>> - __FUNCTION__, origin, offs, new_asce);
>> + __func__, origin, offs, new_asce);
>>
>> if (level != _ASCE_TYPE_SEGMENT) {
>> /* yet another region */
>> @@ -232,7 +235,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t a
>>
>> /* PTE */
>> if (new_asce & _PAGE_INVALID) {
>> - DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __FUNCTION__, new_asce);
>> + DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce);
>> trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
>> return -1;
>> }
>> @@ -243,13 +246,14 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t a
>>
>> *raddr = new_asce & _ASCE_ORIGIN;
>>
>> - PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __FUNCTION__, new_asce);
>> + PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce);
>>
>> return 0;
>> }
>>
>> -static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
>> - target_ulong *raddr, int *flags, int rw)
>> +static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
>> + uint64_t asc, target_ulong *raddr, int *flags,
>> + int rw)
>> {
>> uint64_t asce = 0;
>> int level, new_level;
>> @@ -257,15 +261,15 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
>>
>> switch (asc) {
>> case PSW_ASC_PRIMARY:
>> - PTE_DPRINTF("%s: asc=primary\n", __FUNCTION__);
>> + PTE_DPRINTF("%s: asc=primary\n", __func__);
>> asce = env->cregs[1];
>> break;
>> case PSW_ASC_SECONDARY:
>> - PTE_DPRINTF("%s: asc=secondary\n", __FUNCTION__);
>> + PTE_DPRINTF("%s: asc=secondary\n", __func__);
>> asce = env->cregs[7];
>> break;
>> case PSW_ASC_HOME:
>> - PTE_DPRINTF("%s: asc=home\n", __FUNCTION__);
>> + PTE_DPRINTF("%s: asc=home\n", __func__);
>> asce = env->cregs[13];
>> break;
>> }
>> @@ -276,8 +280,7 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
>> case _ASCE_TYPE_REGION2:
>> if (vaddr & 0xffe0000000000000ULL) {
>> DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
>> - " 0xffe0000000000000ULL\n", __FUNCTION__,
>> - vaddr);
>> + " 0xffe0000000000000ULL\n", __func__, vaddr);
>> trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
>> return -1;
>> }
>> @@ -285,8 +288,7 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
>> case _ASCE_TYPE_REGION3:
>> if (vaddr & 0xfffffc0000000000ULL) {
>> DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
>> - " 0xfffffc0000000000ULL\n", __FUNCTION__,
>> - vaddr);
>> + " 0xfffffc0000000000ULL\n", __func__, vaddr);
>> trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
>> return -1;
>> }
>> @@ -294,8 +296,7 @@ static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t as
>> case _ASCE_TYPE_SEGMENT:
>> if (vaddr & 0xffffffff80000000ULL) {
>> DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
>> - " 0xffffffff80000000ULL\n", __FUNCTION__,
>> - vaddr);
>> + " 0xffffffff80000000ULL\n", __func__, vaddr);
>> trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
>> return -1;
>> }
>> @@ -358,7 +359,7 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
>> break;
>> }
>>
>> -out:
>> + out:
>> /* Convert real address -> absolute address */
>> if (*raddr < 0x2000) {
>> *raddr = *raddr + env->psa;
>> @@ -378,18 +379,18 @@ out:
>> return r;
>> }
>>
>> -int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong _vaddr, int rw,
>> - int mmu_idx)
>> +int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
>> + int rw, int mmu_idx)
>> {
>> uint64_t asc = env->psw.mask & PSW_MASK_ASC;
>> target_ulong vaddr, raddr;
>> int prot;
>>
>> DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
>> - __FUNCTION__, _vaddr, rw, mmu_idx);
>> + __func__, _vaddr, rw, mmu_idx);
>>
>> - _vaddr &= TARGET_PAGE_MASK;
>> - vaddr = _vaddr;
>> + orig_vaddr &= TARGET_PAGE_MASK;
>> + vaddr = orig_vaddr;
>>
>> /* 31-Bit mode */
>> if (!(env->psw.mask & PSW_MASK_64)) {
>> @@ -403,22 +404,23 @@ int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong _vaddr, int rw,
>>
>> /* check out of RAM access */
>> if (raddr > (ram_size + virtio_size)) {
>> - DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __FUNCTION__,
>> + DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
>> (uint64_t)aaddr, (uint64_t)ram_size);
>> trigger_pgm_exception(env, PGM_ADDRESSING, ILC_LATER);
>> return 1;
>> }
>>
>> - DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __FUNCTION__,
>> + DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
>> (uint64_t)vaddr, (uint64_t)raddr, prot);
>>
>> - tlb_set_page(env, _vaddr, raddr, prot,
>> + tlb_set_page(env, orig_vaddr, raddr, prot,
>> mmu_idx, TARGET_PAGE_SIZE);
>>
>> return 0;
>> }
>>
>> -target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env, target_ulong vaddr)
>> +target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env,
>> + target_ulong vaddr)
>> {
>> target_ulong raddr;
>> int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
>> @@ -509,7 +511,7 @@ static void do_program_interrupt(CPUS390XState *env)
>> break;
>> }
>>
>> - qemu_log("%s: code=0x%x ilc=%d\n", __FUNCTION__, env->int_pgm_code, ilc);
>> + qemu_log("%s: code=0x%x ilc=%d\n", __func__, env->int_pgm_code, ilc);
>>
>> lowcore = cpu_physical_memory_map(env->psa, &len, 1);
>>
>> @@ -522,7 +524,7 @@ static void do_program_interrupt(CPUS390XState *env)
>>
>> cpu_physical_memory_unmap(lowcore, len, 1, len);
>>
>> - DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
>> + DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
>> env->int_pgm_code, ilc, env->psw.mask,
>> env->psw.addr);
>>
>> @@ -565,15 +567,15 @@ static void do_ext_interrupt(CPUS390XState *env)
>> env->pending_int &= ~INTERRUPT_EXT;
>> }
>>
>> - DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
>> + DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
>> env->psw.mask, env->psw.addr);
>>
>> load_psw(env, mask, addr);
>> }
>>
>> -void do_interrupt (CPUS390XState *env)
>> +void do_interrupt(CPUS390XState *env)
>> {
>> - qemu_log("%s: %d at pc=%" PRIx64 "\n", __FUNCTION__, env->exception_index,
>> + qemu_log("%s: %d at pc=%" PRIx64 "\n", __func__, env->exception_index,
>> env->psw.addr);
>>
>> s390_add_running_cpu(env);
>> diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
>> index abc35dd..195e93e 100644
>> --- a/target-s390x/op_helper.c
>> +++ b/target-s390x/op_helper.c
>> @@ -31,13 +31,13 @@
>> #include <linux/kvm.h>
>> #endif
>>
>> -#if !defined (CONFIG_USER_ONLY)
>> +#if !defined(CONFIG_USER_ONLY)
>> #include "sysemu.h"
>> #endif
>>
>> /*****************************************************************************/
>> /* Softmmu support */
>> -#if !defined (CONFIG_USER_ONLY)
>> +#if !defined(CONFIG_USER_ONLY)
>> #include "softmmu_exec.h"
>>
>> #define MMUSUFFIX _mmu
>> @@ -95,7 +95,7 @@ void tlb_fill(CPUS390XState *env1, target_ulong addr, int is_write, int mmu_idx,
>> /* raise an exception */
>> void HELPER(exception)(uint32_t excp)
>> {
>> - HELPER_LOG("%s: exception %d\n", __FUNCTION__, excp);
>> + HELPER_LOG("%s: exception %d\n", __func__, excp);
>> env->exception_index = excp;
>> cpu_loop_exit(env);
>> }
>> @@ -164,7 +164,7 @@ uint32_t HELPER(nc)(uint32_t l, uint64_t dest, uint64_t src)
>> uint32_t cc = 0;
>>
>> HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
>> - __FUNCTION__, l, dest, src);
>> + __func__, l, dest, src);
>> for (i = 0; i <= l; i++) {
>> x = ldub(dest + i) & ldub(src + i);
>> if (x) {
>> @@ -183,7 +183,7 @@ uint32_t HELPER(xc)(uint32_t l, uint64_t dest, uint64_t src)
>> uint32_t cc = 0;
>>
>> HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
>> - __FUNCTION__, l, dest, src);
>> + __func__, l, dest, src);
>>
>> #ifndef CONFIG_USER_ONLY
>> /* xor with itself is the same as memset(0) */
>> @@ -217,7 +217,7 @@ uint32_t HELPER(oc)(uint32_t l, uint64_t dest, uint64_t src)
>> uint32_t cc = 0;
>>
>> HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
>> - __FUNCTION__, l, dest, src);
>> + __func__, l, dest, src);
>> for (i = 0; i <= l; i++) {
>> x = ldub(dest + i) | ldub(src + i);
>> if (x) {
>> @@ -236,7 +236,7 @@ void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
>> uint32_t l_64 = (l + 1) / 8;
>>
>> HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
>> - __FUNCTION__, l, dest, src);
>> + __func__, l, dest, src);
>>
>> #ifndef CONFIG_USER_ONLY
>> if ((l > 32) &&
>> @@ -278,10 +278,11 @@ void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
>> uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
>> {
>> int i;
>> - unsigned char x,y;
>> + unsigned char x, y;
>> uint32_t cc;
>> +
>> HELPER_LOG("%s l %d s1 %" PRIx64 " s2 %" PRIx64 "\n",
>> - __FUNCTION__, l, s1, s2);
>> + __func__, l, s1, s2);
>> for (i = 0; i <= l; i++) {
>> x = ldub(s1 + i);
>> y = ldub(s2 + i);
>> @@ -295,7 +296,7 @@ uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
>> }
>> }
>> cc = 0;
>> -done:
>> + done:
>> HELPER_LOG("\n");
>> return cc;
>> }
>> @@ -303,9 +304,10 @@ done:
>> /* compare logical under mask */
>> uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
>> {
>> - uint8_t r,d;
>> + uint8_t r, d;
>> uint32_t cc;
>> - HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%" PRIx64 "\n", __FUNCTION__, r1,
>> +
>> + HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%" PRIx64 "\n", __func__, r1,
>> mask, addr);
>> cc = 0;
>> while (mask) {
>> @@ -313,7 +315,7 @@ uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
>> d = ldub(addr);
>> r = (r1 & 0xff000000UL) >> 24;
>> HELPER_LOG("mask 0x%x %02x/%02x (0x%" PRIx64 ") ", mask, r, d,
>> - addr);
>> + addr);
>> if (r < d) {
>> cc = 1;
>> break;
>> @@ -334,7 +336,8 @@ uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
>> void HELPER(stcm)(uint32_t r1, uint32_t mask, uint64_t addr)
>> {
>> uint8_t r;
>> - HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%lx\n", __FUNCTION__, r1, mask,
>> +
>> + HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%lx\n", __func__, r1, mask,
>> addr);
>> while (mask) {
>> if (mask & 8) {
>> @@ -355,6 +358,7 @@ void HELPER(mlg)(uint32_t r1, uint64_t v2)
>> #if HOST_LONG_BITS == 64 && defined(__GNUC__)
>> /* assuming 64-bit hosts have __uint128_t */
>> __uint128_t res = (__uint128_t)env->regs[r1 + 1];
>> +
>> res *= (__uint128_t)v2;
>> env->regs[r1] = (uint64_t)(res >> 64);
>> env->regs[r1 + 1] = (uint64_t)res;
>> @@ -370,18 +374,18 @@ void HELPER(dlg)(uint32_t r1, uint64_t v2)
>>
>> if (!env->regs[r1]) {
>> /* 64 -> 64/64 case */
>> - env->regs[r1] = env->regs[r1+1] % divisor;
>> - env->regs[r1+1] = env->regs[r1+1] / divisor;
>> + env->regs[r1] = env->regs[r1 + 1] % divisor;
>> + env->regs[r1 + 1] = env->regs[r1 + 1] / divisor;
>> return;
>> } else {
>> -
>> #if HOST_LONG_BITS == 64 && defined(__GNUC__)
>> /* assuming 64-bit hosts have __uint128_t */
>> __uint128_t dividend = (((__uint128_t)env->regs[r1]) << 64) |
>> - (env->regs[r1+1]);
>> + (env->regs[r1 + 1]);
>> __uint128_t quotient = dividend / divisor;
>> - env->regs[r1+1] = quotient;
>> __uint128_t remainder = dividend % divisor;
>> +
>> + env->regs[r1 + 1] = quotient;
>> env->regs[r1] = remainder;
>> #else
>> /* 32-bit hosts would need special wrapper functionality - just abort if
>> @@ -431,7 +435,7 @@ uint32_t HELPER(srst)(uint32_t c, uint32_t r1, uint32_t r2)
>> uint64_t str = get_address_31fix(r2);
>> uint64_t end = get_address_31fix(r1);
>>
>> - HELPER_LOG("%s: c %d *r1 0x%" PRIx64 " *r2 0x%" PRIx64 "\n", __FUNCTION__,
>> + HELPER_LOG("%s: c %d *r1 0x%" PRIx64 " *r2 0x%" PRIx64 "\n", __func__,
>> c, env->regs[r1], env->regs[r2]);
>>
>> for (i = str; i != end; i++) {
>> @@ -452,11 +456,12 @@ uint32_t HELPER(clst)(uint32_t c, uint32_t r1, uint32_t r2)
>> uint64_t s2 = get_address_31fix(r2);
>> uint8_t v1, v2;
>> uint32_t cc;
>> +
>> c = c & 0xff;
>> #ifdef CONFIG_USER_ONLY
>> if (!c) {
>> HELPER_LOG("%s: comparing '%s' and '%s'\n",
>> - __FUNCTION__, (char*)g2h(s1), (char*)g2h(s2));
>> + __func__, (char *)g2h(s1), (char *)g2h(s2));
>> }
>> #endif
>> for (;;) {
>> @@ -501,10 +506,11 @@ void HELPER(mvst)(uint32_t c, uint32_t r1, uint32_t r2)
>> uint64_t dest = get_address_31fix(r1);
>> uint64_t src = get_address_31fix(r2);
>> uint8_t v;
>> +
>> c = c & 0xff;
>> #ifdef CONFIG_USER_ONLY
>> if (!c) {
>> - HELPER_LOG("%s: copy '%s' to 0x%lx\n", __FUNCTION__, (char*)g2h(src),
>> + HELPER_LOG("%s: copy '%s' to 0x%lx\n", __func__, (char *)g2h(src),
>> dest);
>> }
>> #endif
>> @@ -526,6 +532,7 @@ uint32_t HELPER(csg)(uint32_t r1, uint64_t a2, uint32_t r3)
>> /* FIXME: locking? */
>> uint32_t cc;
>> uint64_t v2 = ldq(a2);
>> +
>> if (env->regs[r1] == v2) {
>> cc = 0;
>> stq(a2, env->regs[r3]);
>> @@ -564,8 +571,9 @@ uint32_t HELPER(cs)(uint32_t r1, uint64_t a2, uint32_t r3)
>> {
>> /* FIXME: locking? */
>> uint32_t cc;
>> - HELPER_LOG("%s: r1 %d a2 0x%lx r3 %d\n", __FUNCTION__, r1, a2, r3);
>> uint32_t v2 = ldl(a2);
>> +
>> + HELPER_LOG("%s: r1 %d a2 0x%lx r3 %d\n", __func__, r1, a2, r3);
>> if (((uint32_t)env->regs[r1]) == v2) {
>> cc = 0;
>> stl(a2, (uint32_t)env->regs[r3]);
>> @@ -612,14 +620,16 @@ static uint32_t helper_icm(uint32_t r1, uint64_t address, uint32_t mask)
>> it does not change the program counter
>> in other words: tricky...
>> currently implemented by interpreting the cases it is most commonly used in
>> - */
>> +*/
>> uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
>> {
>> uint16_t insn = lduw_code(addr);
>> - HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __FUNCTION__, v1, addr,
>> - insn);
>> +
>> + HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr,
>> + insn);
>> if ((insn & 0xf0ff) == 0xd000) {
>> uint32_t l, insn2, b1, b2, d1, d2;
>> +
>> l = v1 & 0xff;
>> insn2 = ldl_code(addr + 2);
>> b1 = (insn2 >> 28) & 0xf;
>> @@ -645,13 +655,14 @@ uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
>> }
>> } else if ((insn & 0xff00) == 0x0a00) {
>> /* supervisor call */
>> - HELPER_LOG("%s: svc %ld via execute\n", __FUNCTION__, (insn|v1) & 0xff);
>> + HELPER_LOG("%s: svc %ld via execute\n", __func__, (insn | v1) & 0xff);
>> env->psw.addr = ret - 4;
>> - env->int_svc_code = (insn|v1) & 0xff;
>> + env->int_svc_code = (insn | v1) & 0xff;
>> env->int_svc_ilc = 4;
>> helper_exception(EXCP_SVC);
>> } else if ((insn & 0xff00) == 0xbf00) {
>> uint32_t insn2, r1, r3, b2, d2;
>> +
>> insn2 = ldl_code(addr + 2);
>> r1 = (insn2 >> 20) & 0xf;
>> r3 = (insn2 >> 16) & 0xf;
>> @@ -659,7 +670,7 @@ uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
>> d2 = insn2 & 0xfff;
>> cc = helper_icm(r1, get_address(0, b2, d2), r3);
>> } else {
>> -abort:
>> + abort:
>> cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n",
>> insn);
>> }
>> @@ -689,7 +700,7 @@ int32_t HELPER(nabs_i32)(int32_t val)
>> /* absolute value 64-bit */
>> uint64_t HELPER(abs_i64)(int64_t val)
>> {
>> - HELPER_LOG("%s: val 0x%" PRIx64 "\n", __FUNCTION__, val);
>> + HELPER_LOG("%s: val 0x%" PRIx64 "\n", __func__, val);
>>
>> if (val < 0) {
>> return -val;
>> @@ -774,9 +785,9 @@ void HELPER(ipm)(uint32_t cc, uint32_t r1)
>> uint64_t r = env->regs[r1];
>>
>> r &= 0xffffffff00ffffffULL;
>> - r |= (cc << 28) | ( (env->psw.mask >> 40) & 0xf );
>> + r |= (cc << 28) | ((env->psw.mask >> 40) & 0xf);
>> env->regs[r1] = r;
>> - HELPER_LOG("%s: cc %d psw.mask 0x%lx r1 0x%lx\n", __FUNCTION__,
>> + HELPER_LOG("%s: cc %d psw.mask 0x%lx r1 0x%lx\n", __func__,
>> cc, env->psw.mask, r);
>> }
>>
>> @@ -908,7 +919,7 @@ uint32_t HELPER(clcle)(uint32_t r1, uint64_t a2, uint32_t r3)
>> uint64_t srclen = env->regs[r3 + 1];
>> uint64_t src = get_address_31fix(r3);
>> uint8_t pad = a2 & 0xff;
>> - uint8_t v1 = 0,v2 = 0;
>> + uint8_t v1 = 0, v2 = 0;
>> uint32_t cc = 0;
>>
>> if (!(destlen || srclen)) {
>> @@ -1036,7 +1047,7 @@ static uint32_t set_cc_nz_f128(float128 v)
>> /* convert 32-bit int to 64-bit float */
>> void HELPER(cdfbr)(uint32_t f1, int32_t v2)
>> {
>> - HELPER_LOG("%s: converting %d to f%d\n", __FUNCTION__, v2, f1);
>> + HELPER_LOG("%s: converting %d to f%d\n", __func__, v2, f1);
>> env->fregs[f1].d = int32_to_float64(v2, &env->fpu_status);
>> }
>>
>> @@ -1044,6 +1055,7 @@ void HELPER(cdfbr)(uint32_t f1, int32_t v2)
>> void HELPER(cxfbr)(uint32_t f1, int32_t v2)
>> {
>> CPU_QuadU v1;
>> +
>> v1.q = int32_to_float128(v2, &env->fpu_status);
>> env->fregs[f1].ll = v1.ll.upper;
>> env->fregs[f1 + 2].ll = v1.ll.lower;
>> @@ -1052,14 +1064,14 @@ void HELPER(cxfbr)(uint32_t f1, int32_t v2)
>> /* convert 64-bit int to 32-bit float */
>> void HELPER(cegbr)(uint32_t f1, int64_t v2)
>> {
>> - HELPER_LOG("%s: converting %ld to f%d\n", __FUNCTION__, v2, f1);
>> + HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
>> env->fregs[f1].l.upper = int64_to_float32(v2, &env->fpu_status);
>> }
>>
>> /* convert 64-bit int to 64-bit float */
>> void HELPER(cdgbr)(uint32_t f1, int64_t v2)
>> {
>> - HELPER_LOG("%s: converting %ld to f%d\n", __FUNCTION__, v2, f1);
>> + HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
>> env->fregs[f1].d = int64_to_float64(v2, &env->fpu_status);
>> }
>>
>> @@ -1067,8 +1079,9 @@ void HELPER(cdgbr)(uint32_t f1, int64_t v2)
>> void HELPER(cxgbr)(uint32_t f1, int64_t v2)
>> {
>> CPU_QuadU x1;
>> +
>> x1.q = int64_to_float128(v2, &env->fpu_status);
>> - HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __FUNCTION__, v2,
>> + HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __func__, v2,
>> x1.ll.upper, x1.ll.lower);
>> env->fregs[f1].ll = x1.ll.upper;
>> env->fregs[f1 + 2].ll = x1.ll.lower;
>> @@ -1078,7 +1091,7 @@ void HELPER(cxgbr)(uint32_t f1, int64_t v2)
>> void HELPER(cefbr)(uint32_t f1, int32_t v2)
>> {
>> env->fregs[f1].l.upper = int32_to_float32(v2, &env->fpu_status);
>> - HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __FUNCTION__, v2,
>> + HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __func__, v2,
>> env->fregs[f1].l.upper, f1);
>> }
>>
>> @@ -1088,7 +1101,7 @@ uint32_t HELPER(aebr)(uint32_t f1, uint32_t f2)
>> env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
>> env->fregs[f2].l.upper,
>> &env->fpu_status);
>> - HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __FUNCTION__,
>> + HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
>> env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
>>
>> return set_cc_nz_f32(env->fregs[f1].l.upper);
>> @@ -1099,7 +1112,7 @@ uint32_t HELPER(adbr)(uint32_t f1, uint32_t f2)
>> {
>> env->fregs[f1].d = float64_add(env->fregs[f1].d, env->fregs[f2].d,
>> &env->fpu_status);
>> - HELPER_LOG("%s: adding 0x%ld resulting in 0x%ld in f%d\n", __FUNCTION__,
>> + HELPER_LOG("%s: adding 0x%ld resulting in 0x%ld in f%d\n", __func__,
>> env->fregs[f2].d, env->fregs[f1].d, f1);
>>
>> return set_cc_nz_f64(env->fregs[f1].d);
>> @@ -1111,7 +1124,7 @@ uint32_t HELPER(sebr)(uint32_t f1, uint32_t f2)
>> env->fregs[f1].l.upper = float32_sub(env->fregs[f1].l.upper,
>> env->fregs[f2].l.upper,
>> &env->fpu_status);
>> - HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __FUNCTION__,
>> + HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
>> env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
>>
>> return set_cc_nz_f32(env->fregs[f1].l.upper);
>> @@ -1123,7 +1136,7 @@ uint32_t HELPER(sdbr)(uint32_t f1, uint32_t f2)
>> env->fregs[f1].d = float64_sub(env->fregs[f1].d, env->fregs[f2].d,
>> &env->fpu_status);
>> HELPER_LOG("%s: subtracting 0x%ld resulting in 0x%ld in f%d\n",
>> - __FUNCTION__, env->fregs[f2].d, env->fregs[f1].d, f1);
>> + __func__, env->fregs[f2].d, env->fregs[f1].d, f1);
>>
>> return set_cc_nz_f64(env->fregs[f1].d);
>> }
>> @@ -1140,12 +1153,13 @@ void HELPER(debr)(uint32_t f1, uint32_t f2)
>> void HELPER(dxbr)(uint32_t f1, uint32_t f2)
>> {
>> CPU_QuadU v1;
>> + CPU_QuadU v2;
>> + CPU_QuadU res;
>> +
>> v1.ll.upper = env->fregs[f1].ll;
>> v1.ll.lower = env->fregs[f1 + 2].ll;
>> - CPU_QuadU v2;
>> v2.ll.upper = env->fregs[f2].ll;
>> v2.ll.lower = env->fregs[f2 + 2].ll;
>> - CPU_QuadU res;
>> res.q = float128_div(v1.q, v2.q, &env->fpu_status);
>> env->fregs[f1].ll = res.ll.upper;
>> env->fregs[f1 + 2].ll = res.ll.lower;
>> @@ -1162,12 +1176,13 @@ void HELPER(mdbr)(uint32_t f1, uint32_t f2)
>> void HELPER(mxbr)(uint32_t f1, uint32_t f2)
>> {
>> CPU_QuadU v1;
>> + CPU_QuadU v2;
>> + CPU_QuadU res;
>> +
>> v1.ll.upper = env->fregs[f1].ll;
>> v1.ll.lower = env->fregs[f1 + 2].ll;
>> - CPU_QuadU v2;
>> v2.ll.upper = env->fregs[f2].ll;
>> v2.ll.lower = env->fregs[f2 + 2].ll;
>> - CPU_QuadU res;
>> res.q = float128_mul(v1.q, v2.q, &env->fpu_status);
>> env->fregs[f1].ll = res.ll.upper;
>> env->fregs[f1 + 2].ll = res.ll.lower;
>> @@ -1184,16 +1199,18 @@ void HELPER(ldebr)(uint32_t r1, uint32_t r2)
>> void HELPER(ldxbr)(uint32_t f1, uint32_t f2)
>> {
>> CPU_QuadU x2;
>> +
>> x2.ll.upper = env->fregs[f2].ll;
>> x2.ll.lower = env->fregs[f2 + 2].ll;
>> env->fregs[f1].d = float128_to_float64(x2.q, &env->fpu_status);
>> - HELPER_LOG("%s: to 0x%ld\n", __FUNCTION__, env->fregs[f1].d);
>> + HELPER_LOG("%s: to 0x%ld\n", __func__, env->fregs[f1].d);
>> }
>>
>> /* convert 64-bit float to 128-bit float */
>> void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
>> {
>> CPU_QuadU res;
>> +
>> res.q = float64_to_float128(env->fregs[f2].d, &env->fpu_status);
>> env->fregs[f1].ll = res.ll.upper;
>> env->fregs[f1 + 2].ll = res.ll.lower;
>> @@ -1203,6 +1220,7 @@ void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
>> void HELPER(ledbr)(uint32_t f1, uint32_t f2)
>> {
>> float64 d2 = env->fregs[f2].d;
>> +
>> env->fregs[f1].l.upper = float64_to_float32(d2, &env->fpu_status);
>> }
>>
>> @@ -1210,10 +1228,11 @@ void HELPER(ledbr)(uint32_t f1, uint32_t f2)
>> void HELPER(lexbr)(uint32_t f1, uint32_t f2)
>> {
>> CPU_QuadU x2;
>> +
>> x2.ll.upper = env->fregs[f2].ll;
>> x2.ll.lower = env->fregs[f2 + 2].ll;
>> env->fregs[f1].l.upper = float128_to_float32(x2.q, &env->fpu_status);
>> - HELPER_LOG("%s: to 0x%d\n", __FUNCTION__, env->fregs[f1].l.upper);
>> + HELPER_LOG("%s: to 0x%d\n", __func__, env->fregs[f1].l.upper);
>> }
>>
>> /* absolute value of 32-bit float */
>> @@ -1221,6 +1240,7 @@ uint32_t HELPER(lpebr)(uint32_t f1, uint32_t f2)
>> {
>> float32 v1;
>> float32 v2 = env->fregs[f2].d;
>> +
>> v1 = float32_abs(v2);
>> env->fregs[f1].d = v1;
>> return set_cc_nz_f32(v1);
>> @@ -1231,6 +1251,7 @@ uint32_t HELPER(lpdbr)(uint32_t f1, uint32_t f2)
>> {
>> float64 v1;
>> float64 v2 = env->fregs[f2].d;
>> +
>> v1 = float64_abs(v2);
>> env->fregs[f1].d = v1;
>> return set_cc_nz_f64(v1);
>> @@ -1241,6 +1262,7 @@ uint32_t HELPER(lpxbr)(uint32_t f1, uint32_t f2)
>> {
>> CPU_QuadU v1;
>> CPU_QuadU v2;
>> +
>> v2.ll.upper = env->fregs[f2].ll;
>> v2.ll.lower = env->fregs[f2 + 2].ll;
>> v1.q = float128_abs(v2.q);
>> @@ -1267,6 +1289,7 @@ uint32_t HELPER(ltebr)(uint32_t f1, uint32_t f2)
>> uint32_t HELPER(ltxbr)(uint32_t f1, uint32_t f2)
>> {
>> CPU_QuadU x;
>> +
>> x.ll.upper = env->fregs[f2].ll;
>> x.ll.lower = env->fregs[f2 + 2].ll;
>> env->fregs[f1].ll = x.ll.upper;
>> @@ -1294,6 +1317,7 @@ uint32_t HELPER(lcdbr)(uint32_t f1, uint32_t f2)
>> uint32_t HELPER(lcxbr)(uint32_t f1, uint32_t f2)
>> {
>> CPU_QuadU x1, x2;
>> +
>> x2.ll.upper = env->fregs[f2].ll;
>> x2.ll.lower = env->fregs[f2 + 2].ll;
>> x1.q = float128_chs(x2.q);
>> @@ -1307,8 +1331,9 @@ void HELPER(aeb)(uint32_t f1, uint32_t val)
>> {
>> float32 v1 = env->fregs[f1].l.upper;
>> CPU_FloatU v2;
>> +
>> v2.l = val;
>> - HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __FUNCTION__,
>> + HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __func__,
>> v1, f1, v2.f);
>> env->fregs[f1].l.upper = float32_add(v1, v2.f, &env->fpu_status);
>> }
>> @@ -1318,8 +1343,9 @@ void HELPER(deb)(uint32_t f1, uint32_t val)
>> {
>> float32 v1 = env->fregs[f1].l.upper;
>> CPU_FloatU v2;
>> +
>> v2.l = val;
>> - HELPER_LOG("%s: dividing 0x%d from f%d by 0x%d\n", __FUNCTION__,
>> + HELPER_LOG("%s: dividing 0x%d from f%d by 0x%d\n", __func__,
>> v1, f1, v2.f);
>> env->fregs[f1].l.upper = float32_div(v1, v2.f, &env->fpu_status);
>> }
>> @@ -1329,8 +1355,9 @@ void HELPER(meeb)(uint32_t f1, uint32_t val)
>> {
>> float32 v1 = env->fregs[f1].l.upper;
>> CPU_FloatU v2;
>> +
>> v2.l = val;
>> - HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __FUNCTION__,
>> + HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __func__,
>> v1, f1, v2.f);
>> env->fregs[f1].l.upper = float32_mul(v1, v2.f, &env->fpu_status);
>> }
>> @@ -1340,7 +1367,8 @@ uint32_t HELPER(cebr)(uint32_t f1, uint32_t f2)
>> {
>> float32 v1 = env->fregs[f1].l.upper;
>> float32 v2 = env->fregs[f2].l.upper;
>> - HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __FUNCTION__,
>> +
>> + HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __func__,
>> v1, f1, v2);
>> return set_cc_f32(v1, v2);
>> }
>> @@ -1350,7 +1378,8 @@ uint32_t HELPER(cdbr)(uint32_t f1, uint32_t f2)
>> {
>> float64 v1 = env->fregs[f1].d;
>> float64 v2 = env->fregs[f2].d;
>> - HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __FUNCTION__,
>> +
>> + HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __func__,
>> v1, f1, v2);
>> return set_cc_f64(v1, v2);
>> }
>> @@ -1359,14 +1388,15 @@ uint32_t HELPER(cdbr)(uint32_t f1, uint32_t f2)
>> uint32_t HELPER(cxbr)(uint32_t f1, uint32_t f2)
>> {
>> CPU_QuadU v1;
>> + CPU_QuadU v2;
>> +
>> v1.ll.upper = env->fregs[f1].ll;
>> v1.ll.lower = env->fregs[f1 + 2].ll;
>> - CPU_QuadU v2;
>> v2.ll.upper = env->fregs[f2].ll;
>> v2.ll.lower = env->fregs[f2 + 2].ll;
>>
>> return float_comp_to_cc(float128_compare_quiet(v1.q, v2.q,
>> - &env->fpu_status));
>> + &env->fpu_status));
>> }
>>
>> /* 64-bit FP compare RM */
>> @@ -1374,8 +1404,9 @@ uint32_t HELPER(cdb)(uint32_t f1, uint64_t a2)
>> {
>> float64 v1 = env->fregs[f1].d;
>> CPU_DoubleU v2;
>> +
>> v2.ll = ldq(a2);
>> - HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __FUNCTION__, v1,
>> + HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __func__, v1,
>> f1, v2.d);
>> return set_cc_f64(v1, v2.d);
>> }
>> @@ -1385,8 +1416,9 @@ uint32_t HELPER(adb)(uint32_t f1, uint64_t a2)
>> {
>> float64 v1 = env->fregs[f1].d;
>> CPU_DoubleU v2;
>> +
>> v2.ll = ldq(a2);
>> - HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __FUNCTION__,
>> + HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __func__,
>> v1, f1, v2.d);
>> env->fregs[f1].d = v1 = float64_add(v1, v2.d, &env->fpu_status);
>> return set_cc_nz_f64(v1);
>> @@ -1397,6 +1429,7 @@ void HELPER(seb)(uint32_t f1, uint32_t val)
>> {
>> float32 v1 = env->fregs[f1].l.upper;
>> CPU_FloatU v2;
>> +
>> v2.l = val;
>> env->fregs[f1].l.upper = float32_sub(v1, v2.f, &env->fpu_status);
>> }
>> @@ -1406,6 +1439,7 @@ uint32_t HELPER(sdb)(uint32_t f1, uint64_t a2)
>> {
>> float64 v1 = env->fregs[f1].d;
>> CPU_DoubleU v2;
>> +
>> v2.ll = ldq(a2);
>> env->fregs[f1].d = v1 = float64_sub(v1, v2.d, &env->fpu_status);
>> return set_cc_nz_f64(v1);
>> @@ -1416,8 +1450,9 @@ void HELPER(mdb)(uint32_t f1, uint64_t a2)
>> {
>> float64 v1 = env->fregs[f1].d;
>> CPU_DoubleU v2;
>> +
>> v2.ll = ldq(a2);
>> - HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __FUNCTION__,
>> + HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __func__,
>> v1, f1, v2.d);
>> env->fregs[f1].d = float64_mul(v1, v2.d, &env->fpu_status);
>> }
>> @@ -1427,8 +1462,9 @@ void HELPER(ddb)(uint32_t f1, uint64_t a2)
>> {
>> float64 v1 = env->fregs[f1].d;
>> CPU_DoubleU v2;
>> +
>> v2.ll = ldq(a2);
>> - HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __FUNCTION__,
>> + HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __func__,
>> v1, f1, v2.d);
>> env->fregs[f1].d = float64_div(v1, v2.d, &env->fpu_status);
>> }
>> @@ -1464,6 +1500,7 @@ static void set_round_mode(int m3)
>> uint32_t HELPER(cgebr)(uint32_t r1, uint32_t f2, uint32_t m3)
>> {
>> float32 v2 = env->fregs[f2].l.upper;
>> +
>> set_round_mode(m3);
>> env->regs[r1] = float32_to_int64(v2, &env->fpu_status);
>> return set_cc_nz_f32(v2);
>> @@ -1473,6 +1510,7 @@ uint32_t HELPER(cgebr)(uint32_t r1, uint32_t f2, uint32_t m3)
>> uint32_t HELPER(cgdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
>> {
>> float64 v2 = env->fregs[f2].d;
>> +
>> set_round_mode(m3);
>> env->regs[r1] = float64_to_int64(v2, &env->fpu_status);
>> return set_cc_nz_f64(v2);
>> @@ -1482,6 +1520,7 @@ uint32_t HELPER(cgdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
>> uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
>> {
>> CPU_QuadU v2;
>> +
>> v2.ll.upper = env->fregs[f2].ll;
>> v2.ll.lower = env->fregs[f2 + 2].ll;
>> set_round_mode(m3);
>> @@ -1501,9 +1540,10 @@ uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
>> uint32_t HELPER(cfebr)(uint32_t r1, uint32_t f2, uint32_t m3)
>> {
>> float32 v2 = env->fregs[f2].l.upper;
>> +
>> set_round_mode(m3);
>> env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
>> - float32_to_int32(v2, &env->fpu_status);
>> + float32_to_int32(v2, &env->fpu_status);
>> return set_cc_nz_f32(v2);
>> }
>>
>> @@ -1511,9 +1551,10 @@ uint32_t HELPER(cfebr)(uint32_t r1, uint32_t f2, uint32_t m3)
>> uint32_t HELPER(cfdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
>> {
>> float64 v2 = env->fregs[f2].d;
>> +
>> set_round_mode(m3);
>> env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
>> - float64_to_int32(v2, &env->fpu_status);
>> + float64_to_int32(v2, &env->fpu_status);
>> return set_cc_nz_f64(v2);
>> }
>>
>> @@ -1521,10 +1562,11 @@ uint32_t HELPER(cfdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
>> uint32_t HELPER(cfxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
>> {
>> CPU_QuadU v2;
>> +
>> v2.ll.upper = env->fregs[f2].ll;
>> v2.ll.lower = env->fregs[f2 + 2].ll;
>> env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
>> - float128_to_int32(v2.q, &env->fpu_status);
>> + float128_to_int32(v2.q, &env->fpu_status);
>> return set_cc_nz_f128(v2.q);
>> }
>>
>> @@ -1544,6 +1586,7 @@ void HELPER(lzdr)(uint32_t f1)
>> void HELPER(lzxr)(uint32_t f1)
>> {
>> CPU_QuadU x;
>> +
>> x.q = float64_to_float128(float64_zero, &env->fpu_status);
>> env->fregs[f1].ll = x.ll.upper;
>> env->fregs[f1 + 1].ll = x.ll.lower;
>> @@ -1553,12 +1596,13 @@ void HELPER(lzxr)(uint32_t f1)
>> uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
>> {
>> CPU_QuadU v1;
>> + CPU_QuadU v2;
>> + CPU_QuadU res;
>> +
>> v1.ll.upper = env->fregs[f1].ll;
>> v1.ll.lower = env->fregs[f1 + 2].ll;
>> - CPU_QuadU v2;
>> v2.ll.upper = env->fregs[f2].ll;
>> v2.ll.lower = env->fregs[f2 + 2].ll;
>> - CPU_QuadU res;
>> res.q = float128_sub(v1.q, v2.q, &env->fpu_status);
>> env->fregs[f1].ll = res.ll.upper;
>> env->fregs[f1 + 2].ll = res.ll.lower;
>> @@ -1569,12 +1613,13 @@ uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
>> uint32_t HELPER(axbr)(uint32_t f1, uint32_t f2)
>> {
>> CPU_QuadU v1;
>> + CPU_QuadU v2;
>> + CPU_QuadU res;
>> +
>> v1.ll.upper = env->fregs[f1].ll;
>> v1.ll.lower = env->fregs[f1 + 2].ll;
>> - CPU_QuadU v2;
>> v2.ll.upper = env->fregs[f2].ll;
>> v2.ll.lower = env->fregs[f2 + 2].ll;
>> - CPU_QuadU res;
>> res.q = float128_add(v1.q, v2.q, &env->fpu_status);
>> env->fregs[f1].ll = res.ll.upper;
>> env->fregs[f1 + 2].ll = res.ll.lower;
>> @@ -1599,8 +1644,9 @@ void HELPER(ddbr)(uint32_t f1, uint32_t f2)
>> /* 64-bit FP multiply and add RM */
>> void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
>> {
>> - HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __FUNCTION__, f1, a2, f3);
>> CPU_DoubleU v2;
>> +
>> + HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __func__, f1, a2, f3);
>> v2.ll = ldq(a2);
>> env->fregs[f1].d = float64_add(env->fregs[f1].d,
>> float64_mul(v2.d, env->fregs[f3].d,
>> @@ -1611,7 +1657,7 @@ void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
>> /* 64-bit FP multiply and add RR */
>> void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
>> {
>> - HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __FUNCTION__, f1, f2, f3);
>> + HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
>> env->fregs[f1].d = float64_add(float64_mul(env->fregs[f2].d,
>> env->fregs[f3].d,
>> &env->fpu_status),
>> @@ -1621,7 +1667,7 @@ void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
>> /* 64-bit FP multiply and subtract RR */
>> void HELPER(msdbr)(uint32_t f1, uint32_t f3, uint32_t f2)
>> {
>> - HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __FUNCTION__, f1, f2, f3);
>> + HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
>> env->fregs[f1].d = float64_sub(float64_mul(env->fregs[f2].d,
>> env->fregs[f3].d,
>> &env->fpu_status),
>> @@ -1642,6 +1688,7 @@ void HELPER(maebr)(uint32_t f1, uint32_t f3, uint32_t f2)
>> void HELPER(ldeb)(uint32_t f1, uint64_t a2)
>> {
>> uint32_t v2;
>> +
>> v2 = ldl(a2);
>> env->fregs[f1].d = float32_to_float64(v2,
>> &env->fpu_status);
>> @@ -1651,8 +1698,9 @@ void HELPER(ldeb)(uint32_t f1, uint64_t a2)
>> void HELPER(lxdb)(uint32_t f1, uint64_t a2)
>> {
>> CPU_DoubleU v2;
>> - v2.ll = ldq(a2);
>> CPU_QuadU v1;
>> +
>> + v2.ll = ldq(a2);
>> v1.q = float64_to_float128(v2.d, &env->fpu_status);
>> env->fregs[f1].ll = v1.ll.upper;
>> env->fregs[f1 + 2].ll = v1.ll.lower;
>> @@ -1665,7 +1713,7 @@ uint32_t HELPER(tceb)(uint32_t f1, uint64_t m2)
>> int neg = float32_is_neg(v1);
>> uint32_t cc = 0;
>>
>> - HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __FUNCTION__, (long)v1, m2, neg);
>> + HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, (long)v1, m2, neg);
>> if ((float32_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
>> (float32_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
>> (float32_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
>> @@ -1687,7 +1735,7 @@ uint32_t HELPER(tcdb)(uint32_t f1, uint64_t m2)
>> int neg = float64_is_neg(v1);
>> uint32_t cc = 0;
>>
>> - HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __FUNCTION__, v1, m2, neg);
>> + HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, v1, m2, neg);
>> if ((float64_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
>> (float64_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
>> (float64_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
>> @@ -1706,10 +1754,12 @@ uint32_t HELPER(tcxb)(uint32_t f1, uint64_t m2)
>> {
>> CPU_QuadU v1;
>> uint32_t cc = 0;
>> + int neg;
>> +
>> v1.ll.upper = env->fregs[f1].ll;
>> v1.ll.lower = env->fregs[f1 + 2].ll;
>>
>> - int neg = float128_is_neg(v1.q);
>> + neg = float128_is_neg(v1.q);
>> if ((float128_is_zero(v1.q) && (m2 & (1 << (11-neg)))) ||
>> (float128_is_infinity(v1.q) && (m2 & (1 << (5-neg)))) ||
>> (float128_is_any_nan(v1.q) && (m2 & (1 << (3-neg)))) ||
>> @@ -1787,7 +1837,7 @@ void HELPER(cksm)(uint32_t r1, uint32_t r2)
>>
>> /* store result */
>> env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
>> - ((uint32_t)cksm + (cksm >> 32));
>> + ((uint32_t)cksm + (cksm >> 32));
>> }
>>
>> static inline uint32_t cc_calc_ltgt_32(CPUS390XState *env, int32_t src,
>> @@ -1848,10 +1898,12 @@ static inline uint32_t cc_calc_ltugtu_64(CPUS390XState *env, uint64_t src,
>> }
>> }
>>
>> -static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val, uint32_t mask)
>> +static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val,
>> + uint32_t mask)
>> {
>> - HELPER_LOG("%s: val 0x%x mask 0x%x\n", __FUNCTION__, val, mask);
>> uint16_t r = val & mask;
>> +
>> + HELPER_LOG("%s: val 0x%x mask 0x%x\n", __func__, val, mask);
>> if (r == 0 || mask == 0) {
>> return 0;
>> } else if (r == mask) {
>> @@ -1862,10 +1914,12 @@ static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val, uint32_t
>> }
>>
>> /* set condition code for test under mask */
>> -static inline uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val, uint32_t mask)
>> +static inline uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val,
>> + uint32_t mask)
>> {
>> uint16_t r = val & mask;
>> - HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __FUNCTION__, val, mask, r);
>> +
>> + HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __func__, val, mask, r);
>> if (r == 0 || mask == 0) {
>> return 0;
>> } else if (r == mask) {
>> @@ -1888,8 +1942,8 @@ static inline uint32_t cc_calc_nz(CPUS390XState *env, uint64_t dst)
>> return !!dst;
>> }
>>
>> -static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1, int64_t a2,
>> - int64_t ar)
>> +static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1,
>> + int64_t a2, int64_t ar)
>> {
>> if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
>> return 3; /* overflow */
>> @@ -1904,8 +1958,8 @@ static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1, int64_t a2
>> }
>> }
>>
>> -static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1, uint64_t a2,
>> - uint64_t ar)
>> +static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1,
>> + uint64_t a2, uint64_t ar)
>> {
>> if (ar == 0) {
>> if (a1) {
>> @@ -1915,15 +1969,15 @@ static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1, uint64_t
>> }
>> } else {
>> if (ar < a1 || ar < a2) {
>> - return 3;
>> + return 3;
>> } else {
>> - return 1;
>> + return 1;
>> }
>> }
>> }
>>
>> -static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1, int64_t a2,
>> - int64_t ar)
>> +static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1,
>> + int64_t a2, int64_t ar)
>> {
>> if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
>> return 3; /* overflow */
>> @@ -1938,8 +1992,8 @@ static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1, int64_t a2
>> }
>> }
>>
>> -static inline uint32_t cc_calc_subu_64(CPUS390XState *env, uint64_t a1, uint64_t a2,
>> - uint64_t ar)
>> +static inline uint32_t cc_calc_subu_64(CPUS390XState *env, uint64_t a1,
>> + uint64_t a2, uint64_t ar)
>> {
>> if (ar == 0) {
>> return 2;
>> @@ -1982,8 +2036,8 @@ static inline uint32_t cc_calc_comp_64(CPUS390XState *env, int64_t dst)
>> }
>>
>>
>> -static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1, int32_t a2,
>> - int32_t ar)
>> +static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1,
>> + int32_t a2, int32_t ar)
>> {
>> if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
>> return 3; /* overflow */
>> @@ -1998,26 +2052,26 @@ static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1, int32_t a2
>> }
>> }
>>
>> -static inline uint32_t cc_calc_addu_32(CPUS390XState *env, uint32_t a1, uint32_t a2,
>> - uint32_t ar)
>> +static inline uint32_t cc_calc_addu_32(CPUS390XState *env, uint32_t a1,
>> + uint32_t a2, uint32_t ar)
>> {
>> if (ar == 0) {
>> if (a1) {
>> - return 2;
>> + return 2;
>> } else {
>> - return 0;
>> + return 0;
>> }
>> } else {
>> if (ar < a1 || ar < a2) {
>> - return 3;
>> + return 3;
>> } else {
>> - return 1;
>> + return 1;
>> }
>> }
>> }
>>
>> -static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1, int32_t a2,
>> - int32_t ar)
>> +static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1,
>> + int32_t a2, int32_t ar)
>> {
>> if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
>> return 3; /* overflow */
>> @@ -2032,8 +2086,8 @@ static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1, int32_t a2
>> }
>> }
>>
>> -static inline uint32_t cc_calc_subu_32(CPUS390XState *env, uint32_t a1, uint32_t a2,
>> - uint32_t ar)
>> +static inline uint32_t cc_calc_subu_32(CPUS390XState *env, uint32_t a1,
>> + uint32_t a2, uint32_t ar)
>> {
>> if (ar == 0) {
>> return 2;
>> @@ -2076,11 +2130,12 @@ static inline uint32_t cc_calc_comp_32(CPUS390XState *env, int32_t dst)
>> }
>>
>> /* calculate condition code for insert character under mask insn */
>> -static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask, uint32_t val)
>> +static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask,
>> + uint32_t val)
>> {
>> - HELPER_LOG("%s: mask 0x%x val %d\n", __FUNCTION__, mask, val);
>> uint32_t cc;
>>
>> + HELPER_LOG("%s: mask 0x%x val %d\n", __func__, mask, val);
>> if (mask == 0xf) {
>> if (!val) {
>> return 0;
>> @@ -2107,7 +2162,8 @@ static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask, uint32_
>> return cc;
>> }
>>
>> -static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src, uint64_t shift)
>> +static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src,
>> + uint64_t shift)
>> {
>> uint64_t mask = ((1ULL << shift) - 1ULL) << (64 - shift);
>> uint64_t match, r;
>> @@ -2136,8 +2192,8 @@ static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src, uint64_t s
>> }
>>
>>
>> -static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src,
>> - uint64_t dst, uint64_t vr)
>> +static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
>> + uint64_t src, uint64_t dst, uint64_t vr)
>> {
>> uint32_t r = 0;
>>
>> @@ -2244,7 +2300,7 @@ static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t s
>> cpu_abort(env, "Unknown CC operation: %s\n", cc_name(cc_op));
>> }
>>
>> - HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __FUNCTION__,
>> + HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__,
>> cc_name(cc_op), src, dst, vr, r);
>> return r;
>> }
>> @@ -2334,6 +2390,7 @@ void HELPER(tr)(uint32_t len, uint64_t array, uint64_t trans)
>> for (i = 0; i <= len; i++) {
>> uint8_t byte = ldub(array + i);
>> uint8_t new_byte = ldub(trans + byte);
>> +
>> stb(array + i, new_byte);
>> }
>> }
>> @@ -2363,7 +2420,7 @@ static void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
>> }
>>
>> /*
>> - * ret < 0 indicates program check, ret = 0,1,2,3 -> cc
>> + * ret < 0 indicates program check, ret = 0, 1, 2, 3 -> cc
>> */
>> int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
>> {
>> @@ -2382,24 +2439,24 @@ int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
>> return -PGM_SPECIFICATION;
>> }
>>
>> - switch(code) {
>> - case SCLP_CMDW_READ_SCP_INFO:
>> - case SCLP_CMDW_READ_SCP_INFO_FORCED:
>> - while ((ram_size >> (20 + shift)) > 65535) {
>> - shift++;
>> - }
>> - stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
>> - stb_phys(sccb + SCP_INCREMENT, 1 << shift);
>> - stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
>> + switch (code) {
>> + case SCLP_CMDW_READ_SCP_INFO:
>> + case SCLP_CMDW_READ_SCP_INFO_FORCED:
>> + while ((ram_size >> (20 + shift)) > 65535) {
>> + shift++;
>> + }
>> + stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
>> + stb_phys(sccb + SCP_INCREMENT, 1 << shift);
>> + stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
>>
>> - s390_sclp_extint(sccb & ~3);
>> - break;
>> - default:
>> + s390_sclp_extint(sccb & ~3);
>> + break;
>> + default:
>> #ifdef DEBUG_HELPER
>> - printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
>> + printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
>> #endif
>> - r = 3;
>> - break;
>> + r = 3;
>> + break;
>> }
>>
>> return r;
>> @@ -2479,7 +2536,7 @@ static inline uint64_t clock_value(CPUS390XState *env)
>> uint64_t time;
>>
>> time = env->tod_offset +
>> - time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
>> + time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
>>
>> return time;
>> }
>> @@ -2503,7 +2560,6 @@ uint32_t HELPER(stcke)(uint64_t a1)
>> /* XXX programmable fields */
>> stw(a1 + 17, 0);
>>
>> -
>> return 0;
>> }
>>
>> @@ -2584,7 +2640,7 @@ uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
>> ebcdic_put(sysib.model, "QEMU ", 16);
>> ebcdic_put(sysib.sequence, "QEMU ", 16);
>> ebcdic_put(sysib.plant, "QEMU", 4);
>> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
>> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
>> } else if ((sel1 == 2) && (sel2 == 1)) {
>> /* Basic Machine CPU */
>> struct sysib_121 sysib;
>> @@ -2594,7 +2650,7 @@ uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
>> ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
>> ebcdic_put(sysib.plant, "QEMU", 4);
>> stw_p(&sysib.cpu_addr, env->cpu_num);
>> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
>> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
>> } else if ((sel1 == 2) && (sel2 == 2)) {
>> /* Basic Machine CPUs */
>> struct sysib_122 sysib;
>> @@ -2606,68 +2662,68 @@ uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
>> stw_p(&sysib.active_cpus, 1);
>> stw_p(&sysib.standby_cpus, 0);
>> stw_p(&sysib.reserved_cpus, 0);
>> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
>> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
>> } else {
>> cc = 3;
>> }
>> break;
>> case STSI_LEVEL_2:
>> - {
>> - if ((sel1 == 2) && (sel2 == 1)) {
>> - /* LPAR CPU */
>> - struct sysib_221 sysib;
>> -
>> - memset(&sysib, 0, sizeof(sysib));
>> - /* XXX make different for different CPUs? */
>> - ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
>> - ebcdic_put(sysib.plant, "QEMU", 4);
>> - stw_p(&sysib.cpu_addr, env->cpu_num);
>> - stw_p(&sysib.cpu_id, 0);
>> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
>> - } else if ((sel1 == 2) && (sel2 == 2)) {
>> - /* LPAR CPUs */
>> - struct sysib_222 sysib;
>> -
>> - memset(&sysib, 0, sizeof(sysib));
>> - stw_p(&sysib.lpar_num, 0);
>> - sysib.lcpuc = 0;
>> - /* XXX change when SMP comes */
>> - stw_p(&sysib.total_cpus, 1);
>> - stw_p(&sysib.conf_cpus, 1);
>> - stw_p(&sysib.standby_cpus, 0);
>> - stw_p(&sysib.reserved_cpus, 0);
>> - ebcdic_put(sysib.name, "QEMU ", 8);
>> - stl_p(&sysib.caf, 1000);
>> - stw_p(&sysib.dedicated_cpus, 0);
>> - stw_p(&sysib.shared_cpus, 0);
>> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
>> - } else {
>> - cc = 3;
>> + {
>> + if ((sel1 == 2) && (sel2 == 1)) {
>> + /* LPAR CPU */
>> + struct sysib_221 sysib;
>> +
>> + memset(&sysib, 0, sizeof(sysib));
>> + /* XXX make different for different CPUs? */
>> + ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
>> + ebcdic_put(sysib.plant, "QEMU", 4);
>> + stw_p(&sysib.cpu_addr, env->cpu_num);
>> + stw_p(&sysib.cpu_id, 0);
>> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
>> + } else if ((sel1 == 2) && (sel2 == 2)) {
>> + /* LPAR CPUs */
>> + struct sysib_222 sysib;
>> +
>> + memset(&sysib, 0, sizeof(sysib));
>> + stw_p(&sysib.lpar_num, 0);
>> + sysib.lcpuc = 0;
>> + /* XXX change when SMP comes */
>> + stw_p(&sysib.total_cpus, 1);
>> + stw_p(&sysib.conf_cpus, 1);
>> + stw_p(&sysib.standby_cpus, 0);
>> + stw_p(&sysib.reserved_cpus, 0);
>> + ebcdic_put(sysib.name, "QEMU ", 8);
>> + stl_p(&sysib.caf, 1000);
>> + stw_p(&sysib.dedicated_cpus, 0);
>> + stw_p(&sysib.shared_cpus, 0);
>> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
>> + } else {
>> + cc = 3;
>> + }
>> + break;
>> }
>> - break;
>> - }
>> case STSI_LEVEL_3:
>> - {
>> - if ((sel1 == 2) && (sel2 == 2)) {
>> - /* VM CPUs */
>> - struct sysib_322 sysib;
>> -
>> - memset(&sysib, 0, sizeof(sysib));
>> - sysib.count = 1;
>> - /* XXX change when SMP comes */
>> - stw_p(&sysib.vm[0].total_cpus, 1);
>> - stw_p(&sysib.vm[0].conf_cpus, 1);
>> - stw_p(&sysib.vm[0].standby_cpus, 0);
>> - stw_p(&sysib.vm[0].reserved_cpus, 0);
>> - ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
>> - stl_p(&sysib.vm[0].caf, 1000);
>> - ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
>> - cpu_physical_memory_rw(a0, (uint8_t*)&sysib, sizeof(sysib), 1);
>> - } else {
>> - cc = 3;
>> + {
>> + if ((sel1 == 2) && (sel2 == 2)) {
>> + /* VM CPUs */
>> + struct sysib_322 sysib;
>> +
>> + memset(&sysib, 0, sizeof(sysib));
>> + sysib.count = 1;
>> + /* XXX change when SMP comes */
>> + stw_p(&sysib.vm[0].total_cpus, 1);
>> + stw_p(&sysib.vm[0].conf_cpus, 1);
>> + stw_p(&sysib.vm[0].standby_cpus, 0);
>> + stw_p(&sysib.vm[0].reserved_cpus, 0);
>> + ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
>> + stl_p(&sysib.vm[0].caf, 1000);
>> + ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
>> + cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
>> + } else {
>> + cc = 3;
>> + }
>> + break;
>> }
>> - break;
>> - }
>> case STSI_LEVEL_CURRENT:
>> env->regs[0] = STSI_LEVEL_3;
>> break;
>> @@ -2781,6 +2837,7 @@ uint32_t HELPER(rrbe)(uint32_t r1, uint64_t r2)
>> {
>> uint8_t re;
>> uint8_t key;
>> +
>> if (r2 > ram_size) {
>> return 0;
>> }
>> @@ -2865,7 +2922,7 @@ static uint32_t mvc_asc(int64_t l, uint64_t a1, uint64_t mode1, uint64_t a2,
>> uint32_t HELPER(mvcs)(uint64_t l, uint64_t a1, uint64_t a2)
>> {
>> HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
>> - __FUNCTION__, l, a1, a2);
>> + __func__, l, a1, a2);
>>
>> return mvc_asc(l, a1, PSW_ASC_SECONDARY, a2, PSW_ASC_PRIMARY);
>> }
>> @@ -2873,7 +2930,7 @@ uint32_t HELPER(mvcs)(uint64_t l, uint64_t a1, uint64_t a2)
>> uint32_t HELPER(mvcp)(uint64_t l, uint64_t a1, uint64_t a2)
>> {
>> HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
>> - __FUNCTION__, l, a1, a2);
>> + __func__, l, a1, a2);
>>
>> return mvc_asc(l, a1, PSW_ASC_PRIMARY, a2, PSW_ASC_SECONDARY);
>> }
>> @@ -2883,9 +2940,9 @@ uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
>> int cc = 0;
>>
>> HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
>> - __FUNCTION__, order_code, r1, cpu_addr);
>> + __func__, order_code, r1, cpu_addr);
>>
>> - /* Remember: Use "R1 or R1+1, whichever is the odd-numbered register"
>> + /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
>> as parameter (input). Status (output) is always R1. */
>>
>> switch (order_code) {
>> @@ -2901,7 +2958,7 @@ uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
>> env->regs[r1] &= 0xffffffff00000000ULL;
>> cc = 1;
>> break;
>> -#if !defined (CONFIG_USER_ONLY)
>> +#if !defined(CONFIG_USER_ONLY)
>> case SIGP_RESTART:
>> qemu_system_reset_request();
>> cpu_loop_exit(env);
>> @@ -2922,7 +2979,7 @@ uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
>>
>> void HELPER(sacf)(uint64_t a1)
>> {
>> - HELPER_LOG("%s: %16" PRIx64 "\n", __FUNCTION__, a1);
>> + HELPER_LOG("%s: %16" PRIx64 "\n", __func__, a1);
>>
>> switch (a1 & 0xf00) {
>> case 0x000:
>> @@ -2953,13 +3010,13 @@ void HELPER(ipte)(uint64_t pte_addr, uint64_t vaddr)
>> /* XXX broadcast to other CPUs */
>>
>> /* XXX Linux is nice enough to give us the exact pte address.
>> - According to spec we'd have to find it out ourselves */
>> + According to spec we'd have to find it out ourselves */
>> /* XXX Linux is fine with overwriting the pte, the spec requires
>> - us to only set the invalid bit */
>> + us to only set the invalid bit */
>> stq_phys(pte_addr, pte | _PAGE_INVALID);
>>
>> /* XXX we exploit the fact that Linux passes the exact virtual
>> - address here - it's not obliged to! */
>> + address here - it's not obliged to! */
>> tlb_flush_page(env, page);
>>
>> /* XXX 31-bit hack */
>> @@ -3008,7 +3065,8 @@ uint32_t HELPER(lra)(uint64_t addr, uint32_t r1)
>> env->exception_index = old_exc;
>>
>> if (!(env->psw.mask & PSW_MASK_64)) {
>> - env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | (ret & 0xffffffffULL);
>> + env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
>> + (ret & 0xffffffffULL);
>> } else {
>> env->regs[r1] = ret;
>> }
>> --
>> 1.7.2.5
>>
>
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 01/21] target-s390x: fix style
2012-09-03 19:10 ` Blue Swirl
@ 2012-09-03 23:33 ` Alexander Graf
2012-09-04 14:54 ` Richard Henderson
1 sibling, 0 replies; 64+ messages in thread
From: Alexander Graf @ 2012-09-03 23:33 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel qemu-devel, Richard Henderson
On 03.09.2012, at 15:10, Blue Swirl <blauwirbel@gmail.com> wrote:
> On Mon, Sep 3, 2012 at 4:31 AM, Alexander Graf <agraf@suse.de> wrote:
>>
>> On 02.09.2012, at 13:33, Blue Swirl wrote:
>>
>>> Before splitting op_helper.c and helper.c in the next patches,
>>> fix style issues. No functional changes.
>>>
>>> Replace also GCC specific __FUNCTION__ with
>>> standard __func__.
>>>
>>> Don't init static variable (cpu_s390x_init:inited) with 0.
>>>
>>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>>
>>
>> Phew. Have you hooked up with Richard about these changes? He had quite a big rewrite of the s390 target in the works, and I don't want you guys to work needlessly on major conflicts :)
>
> I missed that one. He's rewriting translate.c, while I'm mostly
> touching op_helper.c. I'd expect it would be simpler for Richard to
> rebase on my series, because they only change helper calls but don't
> otherwise touch code. His series rearranges the code heavily and if I
> rebased on that, it would probably make the patch conflicts harder to
> resolve. What do you think?
I also think that way around makes more sense, but mainly because you posted patches while he posted an RFC :).
Either way, will hopefully get around to review and/or apply your patches next week :)
Alex
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 01/21] target-s390x: fix style
2012-09-03 19:10 ` Blue Swirl
2012-09-03 23:33 ` Alexander Graf
@ 2012-09-04 14:54 ` Richard Henderson
1 sibling, 0 replies; 64+ messages in thread
From: Richard Henderson @ 2012-09-04 14:54 UTC (permalink / raw)
To: Blue Swirl; +Cc: Alexander Graf, qemu-devel qemu-devel
On 2012-09-03 12:10, Blue Swirl wrote:
> I missed that one. He's rewriting translate.c, while I'm mostly
> touching op_helper.c. I'd expect it would be simpler for Richard to
> rebase on my series, because they only change helper calls but don't
> otherwise touch code. His series rearranges the code heavily and if I
> rebased on that, it would probably make the patch conflicts harder to
> resolve. What do you think?
Do go ahead with the areg0 patches first.
r~
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 01/21] target-s390x: fix style
2012-09-02 17:33 ` [Qemu-devel] [PATCH 01/21] target-s390x: fix style Blue Swirl
2012-09-03 4:31 ` Alexander Graf
@ 2012-09-06 18:33 ` Alexander Graf
2012-09-08 8:09 ` Blue Swirl
1 sibling, 1 reply; 64+ messages in thread
From: Alexander Graf @ 2012-09-06 18:33 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel
On 02.09.2012, at 13:33, Blue Swirl wrote:
> Before splitting op_helper.c and helper.c in the next patches,
> fix style issues. No functional changes.
>
> Replace also GCC specific __FUNCTION__ with
> standard __func__.
>
> Don't init static variable (cpu_s390x_init:inited) with 0.
>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Thanks, applied [01-12] to s390-next.
Alex
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 01/21] target-s390x: fix style
2012-09-06 18:33 ` Alexander Graf
@ 2012-09-08 8:09 ` Blue Swirl
0 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-08 8:09 UTC (permalink / raw)
To: Alexander Graf; +Cc: qemu-devel
On Thu, Sep 6, 2012 at 6:33 PM, Alexander Graf <agraf@suse.de> wrote:
>
> On 02.09.2012, at 13:33, Blue Swirl wrote:
>
>> Before splitting op_helper.c and helper.c in the next patches,
>> fix style issues. No functional changes.
>>
>> Replace also GCC specific __FUNCTION__ with
>> standard __func__.
>>
>> Don't init static variable (cpu_s390x_init:inited) with 0.
>>
>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>
> Thanks, applied [01-12] to s390-next.
Please send a pull request soon, as the first set in the series it is
blocking the rest.
>
>
> Alex
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 01/21] target-s390x: fix style Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-04 18:42 ` Richard Henderson
2012-09-02 17:33 ` [Qemu-devel] [PATCH 03/21] target-s390x: split condition code helpers Blue Swirl
` (19 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Move floating point instructions to fpu_helper.c.
While exporting some condition code helpers,
avoid duplicate identifier conflict with translate.c.
Remove unused set_cc_nz_f64() in translate.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
target-s390x/Makefile.objs | 2 +
target-s390x/cpu.h | 6 +
target-s390x/fpu_helper.c | 836 ++++++++++++++++++++++++++++++++++++++++++++
target-s390x/op_helper.c | 802 ------------------------------------------
target-s390x/translate.c | 11 +-
5 files changed, 847 insertions(+), 810 deletions(-)
create mode 100644 target-s390x/fpu_helper.c
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index 80be3bb..23b3bd9 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -1,5 +1,7 @@
obj-y += translate.o op_helper.o helper.o cpu.o interrupt.o
+obj-y += fpu_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o
$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
+$(obj)/fpu_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 18ac6e3..b4620c5 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -999,4 +999,10 @@ static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
env->psw.addr = tb->pc;
}
+/* fpu_helper.c */
+uint32_t set_cc_f32(float32 v1, float32 v2);
+uint32_t set_cc_f64(float64 v1, float64 v2);
+uint32_t set_cc_nz_f32(float32 v);
+uint32_t set_cc_nz_f64(float64 v);
+
#endif
diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c
new file mode 100644
index 0000000..1389052
--- /dev/null
+++ b/target-s390x/fpu_helper.c
@@ -0,0 +1,836 @@
+/*
+ * S/390 FPU helper routines
+ *
+ * Copyright (c) 2009 Ulrich Hecht
+ * Copyright (c) 2009 Alexander Graf
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "dyngen-exec.h"
+#include "helper.h"
+
+#if !defined(CONFIG_USER_ONLY)
+#include "softmmu_exec.h"
+#endif
+
+/* #define DEBUG_HELPER */
+#ifdef DEBUG_HELPER
+#define HELPER_LOG(x...) qemu_log(x)
+#else
+#define HELPER_LOG(x...)
+#endif
+
+static inline int float_comp_to_cc(int float_compare)
+{
+ switch (float_compare) {
+ case float_relation_equal:
+ return 0;
+ case float_relation_less:
+ return 1;
+ case float_relation_greater:
+ return 2;
+ case float_relation_unordered:
+ return 3;
+ default:
+ cpu_abort(env, "unknown return value for float compare\n");
+ }
+}
+
+/* condition codes for binary FP ops */
+uint32_t set_cc_f32(float32 v1, float32 v2)
+{
+ return float_comp_to_cc(float32_compare_quiet(v1, v2, &env->fpu_status));
+}
+
+uint32_t set_cc_f64(float64 v1, float64 v2)
+{
+ return float_comp_to_cc(float64_compare_quiet(v1, v2, &env->fpu_status));
+}
+
+/* condition codes for unary FP ops */
+uint32_t set_cc_nz_f32(float32 v)
+{
+ if (float32_is_any_nan(v)) {
+ return 3;
+ } else if (float32_is_zero(v)) {
+ return 0;
+ } else if (float32_is_neg(v)) {
+ return 1;
+ } else {
+ return 2;
+ }
+}
+
+uint32_t set_cc_nz_f64(float64 v)
+{
+ if (float64_is_any_nan(v)) {
+ return 3;
+ } else if (float64_is_zero(v)) {
+ return 0;
+ } else if (float64_is_neg(v)) {
+ return 1;
+ } else {
+ return 2;
+ }
+}
+
+static uint32_t set_cc_nz_f128(float128 v)
+{
+ if (float128_is_any_nan(v)) {
+ return 3;
+ } else if (float128_is_zero(v)) {
+ return 0;
+ } else if (float128_is_neg(v)) {
+ return 1;
+ } else {
+ return 2;
+ }
+}
+
+/* convert 32-bit int to 64-bit float */
+void HELPER(cdfbr)(uint32_t f1, int32_t v2)
+{
+ HELPER_LOG("%s: converting %d to f%d\n", __func__, v2, f1);
+ env->fregs[f1].d = int32_to_float64(v2, &env->fpu_status);
+}
+
+/* convert 32-bit int to 128-bit float */
+void HELPER(cxfbr)(uint32_t f1, int32_t v2)
+{
+ CPU_QuadU v1;
+
+ v1.q = int32_to_float128(v2, &env->fpu_status);
+ env->fregs[f1].ll = v1.ll.upper;
+ env->fregs[f1 + 2].ll = v1.ll.lower;
+}
+
+/* convert 64-bit int to 32-bit float */
+void HELPER(cegbr)(uint32_t f1, int64_t v2)
+{
+ HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
+ env->fregs[f1].l.upper = int64_to_float32(v2, &env->fpu_status);
+}
+
+/* convert 64-bit int to 64-bit float */
+void HELPER(cdgbr)(uint32_t f1, int64_t v2)
+{
+ HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
+ env->fregs[f1].d = int64_to_float64(v2, &env->fpu_status);
+}
+
+/* convert 64-bit int to 128-bit float */
+void HELPER(cxgbr)(uint32_t f1, int64_t v2)
+{
+ CPU_QuadU x1;
+
+ x1.q = int64_to_float128(v2, &env->fpu_status);
+ HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __func__, v2,
+ x1.ll.upper, x1.ll.lower);
+ env->fregs[f1].ll = x1.ll.upper;
+ env->fregs[f1 + 2].ll = x1.ll.lower;
+}
+
+/* convert 32-bit int to 32-bit float */
+void HELPER(cefbr)(uint32_t f1, int32_t v2)
+{
+ env->fregs[f1].l.upper = int32_to_float32(v2, &env->fpu_status);
+ HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __func__, v2,
+ env->fregs[f1].l.upper, f1);
+}
+
+/* 32-bit FP addition RR */
+uint32_t HELPER(aebr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
+ env->fregs[f2].l.upper,
+ &env->fpu_status);
+ HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
+ env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
+
+ return set_cc_nz_f32(env->fregs[f1].l.upper);
+}
+
+/* 64-bit FP addition RR */
+uint32_t HELPER(adbr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].d = float64_add(env->fregs[f1].d, env->fregs[f2].d,
+ &env->fpu_status);
+ HELPER_LOG("%s: adding 0x%ld resulting in 0x%ld in f%d\n", __func__,
+ env->fregs[f2].d, env->fregs[f1].d, f1);
+
+ return set_cc_nz_f64(env->fregs[f1].d);
+}
+
+/* 32-bit FP subtraction RR */
+uint32_t HELPER(sebr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].l.upper = float32_sub(env->fregs[f1].l.upper,
+ env->fregs[f2].l.upper,
+ &env->fpu_status);
+ HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
+ env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
+
+ return set_cc_nz_f32(env->fregs[f1].l.upper);
+}
+
+/* 64-bit FP subtraction RR */
+uint32_t HELPER(sdbr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].d = float64_sub(env->fregs[f1].d, env->fregs[f2].d,
+ &env->fpu_status);
+ HELPER_LOG("%s: subtracting 0x%ld resulting in 0x%ld in f%d\n",
+ __func__, env->fregs[f2].d, env->fregs[f1].d, f1);
+
+ return set_cc_nz_f64(env->fregs[f1].d);
+}
+
+/* 32-bit FP division RR */
+void HELPER(debr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].l.upper = float32_div(env->fregs[f1].l.upper,
+ env->fregs[f2].l.upper,
+ &env->fpu_status);
+}
+
+/* 128-bit FP division RR */
+void HELPER(dxbr)(uint32_t f1, uint32_t f2)
+{
+ CPU_QuadU v1;
+ CPU_QuadU v2;
+ CPU_QuadU res;
+
+ v1.ll.upper = env->fregs[f1].ll;
+ v1.ll.lower = env->fregs[f1 + 2].ll;
+ v2.ll.upper = env->fregs[f2].ll;
+ v2.ll.lower = env->fregs[f2 + 2].ll;
+ res.q = float128_div(v1.q, v2.q, &env->fpu_status);
+ env->fregs[f1].ll = res.ll.upper;
+ env->fregs[f1 + 2].ll = res.ll.lower;
+}
+
+/* 64-bit FP multiplication RR */
+void HELPER(mdbr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].d = float64_mul(env->fregs[f1].d, env->fregs[f2].d,
+ &env->fpu_status);
+}
+
+/* 128-bit FP multiplication RR */
+void HELPER(mxbr)(uint32_t f1, uint32_t f2)
+{
+ CPU_QuadU v1;
+ CPU_QuadU v2;
+ CPU_QuadU res;
+
+ v1.ll.upper = env->fregs[f1].ll;
+ v1.ll.lower = env->fregs[f1 + 2].ll;
+ v2.ll.upper = env->fregs[f2].ll;
+ v2.ll.lower = env->fregs[f2 + 2].ll;
+ res.q = float128_mul(v1.q, v2.q, &env->fpu_status);
+ env->fregs[f1].ll = res.ll.upper;
+ env->fregs[f1 + 2].ll = res.ll.lower;
+}
+
+/* convert 32-bit float to 64-bit float */
+void HELPER(ldebr)(uint32_t r1, uint32_t r2)
+{
+ env->fregs[r1].d = float32_to_float64(env->fregs[r2].l.upper,
+ &env->fpu_status);
+}
+
+/* convert 128-bit float to 64-bit float */
+void HELPER(ldxbr)(uint32_t f1, uint32_t f2)
+{
+ CPU_QuadU x2;
+
+ x2.ll.upper = env->fregs[f2].ll;
+ x2.ll.lower = env->fregs[f2 + 2].ll;
+ env->fregs[f1].d = float128_to_float64(x2.q, &env->fpu_status);
+ HELPER_LOG("%s: to 0x%ld\n", __func__, env->fregs[f1].d);
+}
+
+/* convert 64-bit float to 128-bit float */
+void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
+{
+ CPU_QuadU res;
+
+ res.q = float64_to_float128(env->fregs[f2].d, &env->fpu_status);
+ env->fregs[f1].ll = res.ll.upper;
+ env->fregs[f1 + 2].ll = res.ll.lower;
+}
+
+/* convert 64-bit float to 32-bit float */
+void HELPER(ledbr)(uint32_t f1, uint32_t f2)
+{
+ float64 d2 = env->fregs[f2].d;
+
+ env->fregs[f1].l.upper = float64_to_float32(d2, &env->fpu_status);
+}
+
+/* convert 128-bit float to 32-bit float */
+void HELPER(lexbr)(uint32_t f1, uint32_t f2)
+{
+ CPU_QuadU x2;
+
+ x2.ll.upper = env->fregs[f2].ll;
+ x2.ll.lower = env->fregs[f2 + 2].ll;
+ env->fregs[f1].l.upper = float128_to_float32(x2.q, &env->fpu_status);
+ HELPER_LOG("%s: to 0x%d\n", __func__, env->fregs[f1].l.upper);
+}
+
+/* absolute value of 32-bit float */
+uint32_t HELPER(lpebr)(uint32_t f1, uint32_t f2)
+{
+ float32 v1;
+ float32 v2 = env->fregs[f2].d;
+
+ v1 = float32_abs(v2);
+ env->fregs[f1].d = v1;
+ return set_cc_nz_f32(v1);
+}
+
+/* absolute value of 64-bit float */
+uint32_t HELPER(lpdbr)(uint32_t f1, uint32_t f2)
+{
+ float64 v1;
+ float64 v2 = env->fregs[f2].d;
+
+ v1 = float64_abs(v2);
+ env->fregs[f1].d = v1;
+ return set_cc_nz_f64(v1);
+}
+
+/* absolute value of 128-bit float */
+uint32_t HELPER(lpxbr)(uint32_t f1, uint32_t f2)
+{
+ CPU_QuadU v1;
+ CPU_QuadU v2;
+
+ v2.ll.upper = env->fregs[f2].ll;
+ v2.ll.lower = env->fregs[f2 + 2].ll;
+ v1.q = float128_abs(v2.q);
+ env->fregs[f1].ll = v1.ll.upper;
+ env->fregs[f1 + 2].ll = v1.ll.lower;
+ return set_cc_nz_f128(v1.q);
+}
+
+/* load and test 64-bit float */
+uint32_t HELPER(ltdbr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].d = env->fregs[f2].d;
+ return set_cc_nz_f64(env->fregs[f1].d);
+}
+
+/* load and test 32-bit float */
+uint32_t HELPER(ltebr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].l.upper = env->fregs[f2].l.upper;
+ return set_cc_nz_f32(env->fregs[f1].l.upper);
+}
+
+/* load and test 128-bit float */
+uint32_t HELPER(ltxbr)(uint32_t f1, uint32_t f2)
+{
+ CPU_QuadU x;
+
+ x.ll.upper = env->fregs[f2].ll;
+ x.ll.lower = env->fregs[f2 + 2].ll;
+ env->fregs[f1].ll = x.ll.upper;
+ env->fregs[f1 + 2].ll = x.ll.lower;
+ return set_cc_nz_f128(x.q);
+}
+
+/* load complement of 32-bit float */
+uint32_t HELPER(lcebr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].l.upper = float32_chs(env->fregs[f2].l.upper);
+
+ return set_cc_nz_f32(env->fregs[f1].l.upper);
+}
+
+/* load complement of 64-bit float */
+uint32_t HELPER(lcdbr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].d = float64_chs(env->fregs[f2].d);
+
+ return set_cc_nz_f64(env->fregs[f1].d);
+}
+
+/* load complement of 128-bit float */
+uint32_t HELPER(lcxbr)(uint32_t f1, uint32_t f2)
+{
+ CPU_QuadU x1, x2;
+
+ x2.ll.upper = env->fregs[f2].ll;
+ x2.ll.lower = env->fregs[f2 + 2].ll;
+ x1.q = float128_chs(x2.q);
+ env->fregs[f1].ll = x1.ll.upper;
+ env->fregs[f1 + 2].ll = x1.ll.lower;
+ return set_cc_nz_f128(x1.q);
+}
+
+/* 32-bit FP addition RM */
+void HELPER(aeb)(uint32_t f1, uint32_t val)
+{
+ float32 v1 = env->fregs[f1].l.upper;
+ CPU_FloatU v2;
+
+ v2.l = val;
+ HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __func__,
+ v1, f1, v2.f);
+ env->fregs[f1].l.upper = float32_add(v1, v2.f, &env->fpu_status);
+}
+
+/* 32-bit FP division RM */
+void HELPER(deb)(uint32_t f1, uint32_t val)
+{
+ float32 v1 = env->fregs[f1].l.upper;
+ CPU_FloatU v2;
+
+ v2.l = val;
+ HELPER_LOG("%s: dividing 0x%d from f%d by 0x%d\n", __func__,
+ v1, f1, v2.f);
+ env->fregs[f1].l.upper = float32_div(v1, v2.f, &env->fpu_status);
+}
+
+/* 32-bit FP multiplication RM */
+void HELPER(meeb)(uint32_t f1, uint32_t val)
+{
+ float32 v1 = env->fregs[f1].l.upper;
+ CPU_FloatU v2;
+
+ v2.l = val;
+ HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __func__,
+ v1, f1, v2.f);
+ env->fregs[f1].l.upper = float32_mul(v1, v2.f, &env->fpu_status);
+}
+
+/* 32-bit FP compare RR */
+uint32_t HELPER(cebr)(uint32_t f1, uint32_t f2)
+{
+ float32 v1 = env->fregs[f1].l.upper;
+ float32 v2 = env->fregs[f2].l.upper;
+
+ HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __func__,
+ v1, f1, v2);
+ return set_cc_f32(v1, v2);
+}
+
+/* 64-bit FP compare RR */
+uint32_t HELPER(cdbr)(uint32_t f1, uint32_t f2)
+{
+ float64 v1 = env->fregs[f1].d;
+ float64 v2 = env->fregs[f2].d;
+
+ HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __func__,
+ v1, f1, v2);
+ return set_cc_f64(v1, v2);
+}
+
+/* 128-bit FP compare RR */
+uint32_t HELPER(cxbr)(uint32_t f1, uint32_t f2)
+{
+ CPU_QuadU v1;
+ CPU_QuadU v2;
+
+ v1.ll.upper = env->fregs[f1].ll;
+ v1.ll.lower = env->fregs[f1 + 2].ll;
+ v2.ll.upper = env->fregs[f2].ll;
+ v2.ll.lower = env->fregs[f2 + 2].ll;
+
+ return float_comp_to_cc(float128_compare_quiet(v1.q, v2.q,
+ &env->fpu_status));
+}
+
+/* 64-bit FP compare RM */
+uint32_t HELPER(cdb)(uint32_t f1, uint64_t a2)
+{
+ float64 v1 = env->fregs[f1].d;
+ CPU_DoubleU v2;
+
+ v2.ll = ldq(a2);
+ HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __func__, v1,
+ f1, v2.d);
+ return set_cc_f64(v1, v2.d);
+}
+
+/* 64-bit FP addition RM */
+uint32_t HELPER(adb)(uint32_t f1, uint64_t a2)
+{
+ float64 v1 = env->fregs[f1].d;
+ CPU_DoubleU v2;
+
+ v2.ll = ldq(a2);
+ HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __func__,
+ v1, f1, v2.d);
+ env->fregs[f1].d = v1 = float64_add(v1, v2.d, &env->fpu_status);
+ return set_cc_nz_f64(v1);
+}
+
+/* 32-bit FP subtraction RM */
+void HELPER(seb)(uint32_t f1, uint32_t val)
+{
+ float32 v1 = env->fregs[f1].l.upper;
+ CPU_FloatU v2;
+
+ v2.l = val;
+ env->fregs[f1].l.upper = float32_sub(v1, v2.f, &env->fpu_status);
+}
+
+/* 64-bit FP subtraction RM */
+uint32_t HELPER(sdb)(uint32_t f1, uint64_t a2)
+{
+ float64 v1 = env->fregs[f1].d;
+ CPU_DoubleU v2;
+
+ v2.ll = ldq(a2);
+ env->fregs[f1].d = v1 = float64_sub(v1, v2.d, &env->fpu_status);
+ return set_cc_nz_f64(v1);
+}
+
+/* 64-bit FP multiplication RM */
+void HELPER(mdb)(uint32_t f1, uint64_t a2)
+{
+ float64 v1 = env->fregs[f1].d;
+ CPU_DoubleU v2;
+
+ v2.ll = ldq(a2);
+ HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __func__,
+ v1, f1, v2.d);
+ env->fregs[f1].d = float64_mul(v1, v2.d, &env->fpu_status);
+}
+
+/* 64-bit FP division RM */
+void HELPER(ddb)(uint32_t f1, uint64_t a2)
+{
+ float64 v1 = env->fregs[f1].d;
+ CPU_DoubleU v2;
+
+ v2.ll = ldq(a2);
+ HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __func__,
+ v1, f1, v2.d);
+ env->fregs[f1].d = float64_div(v1, v2.d, &env->fpu_status);
+}
+
+static void set_round_mode(int m3)
+{
+ switch (m3) {
+ case 0:
+ /* current mode */
+ break;
+ case 1:
+ /* biased round no nearest */
+ case 4:
+ /* round to nearest */
+ set_float_rounding_mode(float_round_nearest_even, &env->fpu_status);
+ break;
+ case 5:
+ /* round to zero */
+ set_float_rounding_mode(float_round_to_zero, &env->fpu_status);
+ break;
+ case 6:
+ /* round to +inf */
+ set_float_rounding_mode(float_round_up, &env->fpu_status);
+ break;
+ case 7:
+ /* round to -inf */
+ set_float_rounding_mode(float_round_down, &env->fpu_status);
+ break;
+ }
+}
+
+/* convert 32-bit float to 64-bit int */
+uint32_t HELPER(cgebr)(uint32_t r1, uint32_t f2, uint32_t m3)
+{
+ float32 v2 = env->fregs[f2].l.upper;
+
+ set_round_mode(m3);
+ env->regs[r1] = float32_to_int64(v2, &env->fpu_status);
+ return set_cc_nz_f32(v2);
+}
+
+/* convert 64-bit float to 64-bit int */
+uint32_t HELPER(cgdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
+{
+ float64 v2 = env->fregs[f2].d;
+
+ set_round_mode(m3);
+ env->regs[r1] = float64_to_int64(v2, &env->fpu_status);
+ return set_cc_nz_f64(v2);
+}
+
+/* convert 128-bit float to 64-bit int */
+uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
+{
+ CPU_QuadU v2;
+
+ v2.ll.upper = env->fregs[f2].ll;
+ v2.ll.lower = env->fregs[f2 + 2].ll;
+ set_round_mode(m3);
+ env->regs[r1] = float128_to_int64(v2.q, &env->fpu_status);
+ if (float128_is_any_nan(v2.q)) {
+ return 3;
+ } else if (float128_is_zero(v2.q)) {
+ return 0;
+ } else if (float128_is_neg(v2.q)) {
+ return 1;
+ } else {
+ return 2;
+ }
+}
+
+/* convert 32-bit float to 32-bit int */
+uint32_t HELPER(cfebr)(uint32_t r1, uint32_t f2, uint32_t m3)
+{
+ float32 v2 = env->fregs[f2].l.upper;
+
+ set_round_mode(m3);
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
+ float32_to_int32(v2, &env->fpu_status);
+ return set_cc_nz_f32(v2);
+}
+
+/* convert 64-bit float to 32-bit int */
+uint32_t HELPER(cfdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
+{
+ float64 v2 = env->fregs[f2].d;
+
+ set_round_mode(m3);
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
+ float64_to_int32(v2, &env->fpu_status);
+ return set_cc_nz_f64(v2);
+}
+
+/* convert 128-bit float to 32-bit int */
+uint32_t HELPER(cfxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
+{
+ CPU_QuadU v2;
+
+ v2.ll.upper = env->fregs[f2].ll;
+ v2.ll.lower = env->fregs[f2 + 2].ll;
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
+ float128_to_int32(v2.q, &env->fpu_status);
+ return set_cc_nz_f128(v2.q);
+}
+
+/* load 32-bit FP zero */
+void HELPER(lzer)(uint32_t f1)
+{
+ env->fregs[f1].l.upper = float32_zero;
+}
+
+/* load 64-bit FP zero */
+void HELPER(lzdr)(uint32_t f1)
+{
+ env->fregs[f1].d = float64_zero;
+}
+
+/* load 128-bit FP zero */
+void HELPER(lzxr)(uint32_t f1)
+{
+ CPU_QuadU x;
+
+ x.q = float64_to_float128(float64_zero, &env->fpu_status);
+ env->fregs[f1].ll = x.ll.upper;
+ env->fregs[f1 + 1].ll = x.ll.lower;
+}
+
+/* 128-bit FP subtraction RR */
+uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
+{
+ CPU_QuadU v1;
+ CPU_QuadU v2;
+ CPU_QuadU res;
+
+ v1.ll.upper = env->fregs[f1].ll;
+ v1.ll.lower = env->fregs[f1 + 2].ll;
+ v2.ll.upper = env->fregs[f2].ll;
+ v2.ll.lower = env->fregs[f2 + 2].ll;
+ res.q = float128_sub(v1.q, v2.q, &env->fpu_status);
+ env->fregs[f1].ll = res.ll.upper;
+ env->fregs[f1 + 2].ll = res.ll.lower;
+ return set_cc_nz_f128(res.q);
+}
+
+/* 128-bit FP addition RR */
+uint32_t HELPER(axbr)(uint32_t f1, uint32_t f2)
+{
+ CPU_QuadU v1;
+ CPU_QuadU v2;
+ CPU_QuadU res;
+
+ v1.ll.upper = env->fregs[f1].ll;
+ v1.ll.lower = env->fregs[f1 + 2].ll;
+ v2.ll.upper = env->fregs[f2].ll;
+ v2.ll.lower = env->fregs[f2 + 2].ll;
+ res.q = float128_add(v1.q, v2.q, &env->fpu_status);
+ env->fregs[f1].ll = res.ll.upper;
+ env->fregs[f1 + 2].ll = res.ll.lower;
+ return set_cc_nz_f128(res.q);
+}
+
+/* 32-bit FP multiplication RR */
+void HELPER(meebr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].l.upper = float32_mul(env->fregs[f1].l.upper,
+ env->fregs[f2].l.upper,
+ &env->fpu_status);
+}
+
+/* 64-bit FP division RR */
+void HELPER(ddbr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].d = float64_div(env->fregs[f1].d, env->fregs[f2].d,
+ &env->fpu_status);
+}
+
+/* 64-bit FP multiply and add RM */
+void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
+{
+ CPU_DoubleU v2;
+
+ HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __func__, f1, a2, f3);
+ v2.ll = ldq(a2);
+ env->fregs[f1].d = float64_add(env->fregs[f1].d,
+ float64_mul(v2.d, env->fregs[f3].d,
+ &env->fpu_status),
+ &env->fpu_status);
+}
+
+/* 64-bit FP multiply and add RR */
+void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
+{
+ HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
+ env->fregs[f1].d = float64_add(float64_mul(env->fregs[f2].d,
+ env->fregs[f3].d,
+ &env->fpu_status),
+ env->fregs[f1].d, &env->fpu_status);
+}
+
+/* 64-bit FP multiply and subtract RR */
+void HELPER(msdbr)(uint32_t f1, uint32_t f3, uint32_t f2)
+{
+ HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
+ env->fregs[f1].d = float64_sub(float64_mul(env->fregs[f2].d,
+ env->fregs[f3].d,
+ &env->fpu_status),
+ env->fregs[f1].d, &env->fpu_status);
+}
+
+/* 32-bit FP multiply and add RR */
+void HELPER(maebr)(uint32_t f1, uint32_t f3, uint32_t f2)
+{
+ env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
+ float32_mul(env->fregs[f2].l.upper,
+ env->fregs[f3].l.upper,
+ &env->fpu_status),
+ &env->fpu_status);
+}
+
+/* convert 32-bit float to 64-bit float */
+void HELPER(ldeb)(uint32_t f1, uint64_t a2)
+{
+ uint32_t v2;
+
+ v2 = ldl(a2);
+ env->fregs[f1].d = float32_to_float64(v2,
+ &env->fpu_status);
+}
+
+/* convert 64-bit float to 128-bit float */
+void HELPER(lxdb)(uint32_t f1, uint64_t a2)
+{
+ CPU_DoubleU v2;
+ CPU_QuadU v1;
+
+ v2.ll = ldq(a2);
+ v1.q = float64_to_float128(v2.d, &env->fpu_status);
+ env->fregs[f1].ll = v1.ll.upper;
+ env->fregs[f1 + 2].ll = v1.ll.lower;
+}
+
+/* test data class 32-bit */
+uint32_t HELPER(tceb)(uint32_t f1, uint64_t m2)
+{
+ float32 v1 = env->fregs[f1].l.upper;
+ int neg = float32_is_neg(v1);
+ uint32_t cc = 0;
+
+ HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, (long)v1, m2, neg);
+ if ((float32_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
+ (float32_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
+ (float32_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
+ (float32_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
+ cc = 1;
+ } else if (m2 & (1 << (9-neg))) {
+ /* assume normalized number */
+ cc = 1;
+ }
+
+ /* FIXME: denormalized? */
+ return cc;
+}
+
+/* test data class 64-bit */
+uint32_t HELPER(tcdb)(uint32_t f1, uint64_t m2)
+{
+ float64 v1 = env->fregs[f1].d;
+ int neg = float64_is_neg(v1);
+ uint32_t cc = 0;
+
+ HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, v1, m2, neg);
+ if ((float64_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
+ (float64_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
+ (float64_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
+ (float64_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
+ cc = 1;
+ } else if (m2 & (1 << (9-neg))) {
+ /* assume normalized number */
+ cc = 1;
+ }
+ /* FIXME: denormalized? */
+ return cc;
+}
+
+/* test data class 128-bit */
+uint32_t HELPER(tcxb)(uint32_t f1, uint64_t m2)
+{
+ CPU_QuadU v1;
+ uint32_t cc = 0;
+ int neg;
+
+ v1.ll.upper = env->fregs[f1].ll;
+ v1.ll.lower = env->fregs[f1 + 2].ll;
+
+ neg = float128_is_neg(v1.q);
+ if ((float128_is_zero(v1.q) && (m2 & (1 << (11-neg)))) ||
+ (float128_is_infinity(v1.q) && (m2 & (1 << (5-neg)))) ||
+ (float128_is_any_nan(v1.q) && (m2 & (1 << (3-neg)))) ||
+ (float128_is_signaling_nan(v1.q) && (m2 & (1 << (1-neg))))) {
+ cc = 1;
+ } else if (m2 & (1 << (9-neg))) {
+ /* assume normalized number */
+ cc = 1;
+ }
+ /* FIXME: denormalized? */
+ return cc;
+}
+
+/* square root 64-bit RR */
+void HELPER(sqdbr)(uint32_t f1, uint32_t f2)
+{
+ env->fregs[f1].d = float64_sqrt(env->fregs[f2].d, &env->fpu_status);
+}
diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
index 195e93e..270bf14 100644
--- a/target-s390x/op_helper.c
+++ b/target-s390x/op_helper.c
@@ -977,802 +977,6 @@ uint32_t HELPER(slbg)(uint32_t cc, uint32_t r1, uint64_t v1, uint64_t v2)
}
}
-static inline int float_comp_to_cc(int float_compare)
-{
- switch (float_compare) {
- case float_relation_equal:
- return 0;
- case float_relation_less:
- return 1;
- case float_relation_greater:
- return 2;
- case float_relation_unordered:
- return 3;
- default:
- cpu_abort(env, "unknown return value for float compare\n");
- }
-}
-
-/* condition codes for binary FP ops */
-static uint32_t set_cc_f32(float32 v1, float32 v2)
-{
- return float_comp_to_cc(float32_compare_quiet(v1, v2, &env->fpu_status));
-}
-
-static uint32_t set_cc_f64(float64 v1, float64 v2)
-{
- return float_comp_to_cc(float64_compare_quiet(v1, v2, &env->fpu_status));
-}
-
-/* condition codes for unary FP ops */
-static uint32_t set_cc_nz_f32(float32 v)
-{
- if (float32_is_any_nan(v)) {
- return 3;
- } else if (float32_is_zero(v)) {
- return 0;
- } else if (float32_is_neg(v)) {
- return 1;
- } else {
- return 2;
- }
-}
-
-static uint32_t set_cc_nz_f64(float64 v)
-{
- if (float64_is_any_nan(v)) {
- return 3;
- } else if (float64_is_zero(v)) {
- return 0;
- } else if (float64_is_neg(v)) {
- return 1;
- } else {
- return 2;
- }
-}
-
-static uint32_t set_cc_nz_f128(float128 v)
-{
- if (float128_is_any_nan(v)) {
- return 3;
- } else if (float128_is_zero(v)) {
- return 0;
- } else if (float128_is_neg(v)) {
- return 1;
- } else {
- return 2;
- }
-}
-
-/* convert 32-bit int to 64-bit float */
-void HELPER(cdfbr)(uint32_t f1, int32_t v2)
-{
- HELPER_LOG("%s: converting %d to f%d\n", __func__, v2, f1);
- env->fregs[f1].d = int32_to_float64(v2, &env->fpu_status);
-}
-
-/* convert 32-bit int to 128-bit float */
-void HELPER(cxfbr)(uint32_t f1, int32_t v2)
-{
- CPU_QuadU v1;
-
- v1.q = int32_to_float128(v2, &env->fpu_status);
- env->fregs[f1].ll = v1.ll.upper;
- env->fregs[f1 + 2].ll = v1.ll.lower;
-}
-
-/* convert 64-bit int to 32-bit float */
-void HELPER(cegbr)(uint32_t f1, int64_t v2)
-{
- HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
- env->fregs[f1].l.upper = int64_to_float32(v2, &env->fpu_status);
-}
-
-/* convert 64-bit int to 64-bit float */
-void HELPER(cdgbr)(uint32_t f1, int64_t v2)
-{
- HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
- env->fregs[f1].d = int64_to_float64(v2, &env->fpu_status);
-}
-
-/* convert 64-bit int to 128-bit float */
-void HELPER(cxgbr)(uint32_t f1, int64_t v2)
-{
- CPU_QuadU x1;
-
- x1.q = int64_to_float128(v2, &env->fpu_status);
- HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __func__, v2,
- x1.ll.upper, x1.ll.lower);
- env->fregs[f1].ll = x1.ll.upper;
- env->fregs[f1 + 2].ll = x1.ll.lower;
-}
-
-/* convert 32-bit int to 32-bit float */
-void HELPER(cefbr)(uint32_t f1, int32_t v2)
-{
- env->fregs[f1].l.upper = int32_to_float32(v2, &env->fpu_status);
- HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __func__, v2,
- env->fregs[f1].l.upper, f1);
-}
-
-/* 32-bit FP addition RR */
-uint32_t HELPER(aebr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
- env->fregs[f2].l.upper,
- &env->fpu_status);
- HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
- env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
-
- return set_cc_nz_f32(env->fregs[f1].l.upper);
-}
-
-/* 64-bit FP addition RR */
-uint32_t HELPER(adbr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].d = float64_add(env->fregs[f1].d, env->fregs[f2].d,
- &env->fpu_status);
- HELPER_LOG("%s: adding 0x%ld resulting in 0x%ld in f%d\n", __func__,
- env->fregs[f2].d, env->fregs[f1].d, f1);
-
- return set_cc_nz_f64(env->fregs[f1].d);
-}
-
-/* 32-bit FP subtraction RR */
-uint32_t HELPER(sebr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].l.upper = float32_sub(env->fregs[f1].l.upper,
- env->fregs[f2].l.upper,
- &env->fpu_status);
- HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
- env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
-
- return set_cc_nz_f32(env->fregs[f1].l.upper);
-}
-
-/* 64-bit FP subtraction RR */
-uint32_t HELPER(sdbr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].d = float64_sub(env->fregs[f1].d, env->fregs[f2].d,
- &env->fpu_status);
- HELPER_LOG("%s: subtracting 0x%ld resulting in 0x%ld in f%d\n",
- __func__, env->fregs[f2].d, env->fregs[f1].d, f1);
-
- return set_cc_nz_f64(env->fregs[f1].d);
-}
-
-/* 32-bit FP division RR */
-void HELPER(debr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].l.upper = float32_div(env->fregs[f1].l.upper,
- env->fregs[f2].l.upper,
- &env->fpu_status);
-}
-
-/* 128-bit FP division RR */
-void HELPER(dxbr)(uint32_t f1, uint32_t f2)
-{
- CPU_QuadU v1;
- CPU_QuadU v2;
- CPU_QuadU res;
-
- v1.ll.upper = env->fregs[f1].ll;
- v1.ll.lower = env->fregs[f1 + 2].ll;
- v2.ll.upper = env->fregs[f2].ll;
- v2.ll.lower = env->fregs[f2 + 2].ll;
- res.q = float128_div(v1.q, v2.q, &env->fpu_status);
- env->fregs[f1].ll = res.ll.upper;
- env->fregs[f1 + 2].ll = res.ll.lower;
-}
-
-/* 64-bit FP multiplication RR */
-void HELPER(mdbr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].d = float64_mul(env->fregs[f1].d, env->fregs[f2].d,
- &env->fpu_status);
-}
-
-/* 128-bit FP multiplication RR */
-void HELPER(mxbr)(uint32_t f1, uint32_t f2)
-{
- CPU_QuadU v1;
- CPU_QuadU v2;
- CPU_QuadU res;
-
- v1.ll.upper = env->fregs[f1].ll;
- v1.ll.lower = env->fregs[f1 + 2].ll;
- v2.ll.upper = env->fregs[f2].ll;
- v2.ll.lower = env->fregs[f2 + 2].ll;
- res.q = float128_mul(v1.q, v2.q, &env->fpu_status);
- env->fregs[f1].ll = res.ll.upper;
- env->fregs[f1 + 2].ll = res.ll.lower;
-}
-
-/* convert 32-bit float to 64-bit float */
-void HELPER(ldebr)(uint32_t r1, uint32_t r2)
-{
- env->fregs[r1].d = float32_to_float64(env->fregs[r2].l.upper,
- &env->fpu_status);
-}
-
-/* convert 128-bit float to 64-bit float */
-void HELPER(ldxbr)(uint32_t f1, uint32_t f2)
-{
- CPU_QuadU x2;
-
- x2.ll.upper = env->fregs[f2].ll;
- x2.ll.lower = env->fregs[f2 + 2].ll;
- env->fregs[f1].d = float128_to_float64(x2.q, &env->fpu_status);
- HELPER_LOG("%s: to 0x%ld\n", __func__, env->fregs[f1].d);
-}
-
-/* convert 64-bit float to 128-bit float */
-void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
-{
- CPU_QuadU res;
-
- res.q = float64_to_float128(env->fregs[f2].d, &env->fpu_status);
- env->fregs[f1].ll = res.ll.upper;
- env->fregs[f1 + 2].ll = res.ll.lower;
-}
-
-/* convert 64-bit float to 32-bit float */
-void HELPER(ledbr)(uint32_t f1, uint32_t f2)
-{
- float64 d2 = env->fregs[f2].d;
-
- env->fregs[f1].l.upper = float64_to_float32(d2, &env->fpu_status);
-}
-
-/* convert 128-bit float to 32-bit float */
-void HELPER(lexbr)(uint32_t f1, uint32_t f2)
-{
- CPU_QuadU x2;
-
- x2.ll.upper = env->fregs[f2].ll;
- x2.ll.lower = env->fregs[f2 + 2].ll;
- env->fregs[f1].l.upper = float128_to_float32(x2.q, &env->fpu_status);
- HELPER_LOG("%s: to 0x%d\n", __func__, env->fregs[f1].l.upper);
-}
-
-/* absolute value of 32-bit float */
-uint32_t HELPER(lpebr)(uint32_t f1, uint32_t f2)
-{
- float32 v1;
- float32 v2 = env->fregs[f2].d;
-
- v1 = float32_abs(v2);
- env->fregs[f1].d = v1;
- return set_cc_nz_f32(v1);
-}
-
-/* absolute value of 64-bit float */
-uint32_t HELPER(lpdbr)(uint32_t f1, uint32_t f2)
-{
- float64 v1;
- float64 v2 = env->fregs[f2].d;
-
- v1 = float64_abs(v2);
- env->fregs[f1].d = v1;
- return set_cc_nz_f64(v1);
-}
-
-/* absolute value of 128-bit float */
-uint32_t HELPER(lpxbr)(uint32_t f1, uint32_t f2)
-{
- CPU_QuadU v1;
- CPU_QuadU v2;
-
- v2.ll.upper = env->fregs[f2].ll;
- v2.ll.lower = env->fregs[f2 + 2].ll;
- v1.q = float128_abs(v2.q);
- env->fregs[f1].ll = v1.ll.upper;
- env->fregs[f1 + 2].ll = v1.ll.lower;
- return set_cc_nz_f128(v1.q);
-}
-
-/* load and test 64-bit float */
-uint32_t HELPER(ltdbr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].d = env->fregs[f2].d;
- return set_cc_nz_f64(env->fregs[f1].d);
-}
-
-/* load and test 32-bit float */
-uint32_t HELPER(ltebr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].l.upper = env->fregs[f2].l.upper;
- return set_cc_nz_f32(env->fregs[f1].l.upper);
-}
-
-/* load and test 128-bit float */
-uint32_t HELPER(ltxbr)(uint32_t f1, uint32_t f2)
-{
- CPU_QuadU x;
-
- x.ll.upper = env->fregs[f2].ll;
- x.ll.lower = env->fregs[f2 + 2].ll;
- env->fregs[f1].ll = x.ll.upper;
- env->fregs[f1 + 2].ll = x.ll.lower;
- return set_cc_nz_f128(x.q);
-}
-
-/* load complement of 32-bit float */
-uint32_t HELPER(lcebr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].l.upper = float32_chs(env->fregs[f2].l.upper);
-
- return set_cc_nz_f32(env->fregs[f1].l.upper);
-}
-
-/* load complement of 64-bit float */
-uint32_t HELPER(lcdbr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].d = float64_chs(env->fregs[f2].d);
-
- return set_cc_nz_f64(env->fregs[f1].d);
-}
-
-/* load complement of 128-bit float */
-uint32_t HELPER(lcxbr)(uint32_t f1, uint32_t f2)
-{
- CPU_QuadU x1, x2;
-
- x2.ll.upper = env->fregs[f2].ll;
- x2.ll.lower = env->fregs[f2 + 2].ll;
- x1.q = float128_chs(x2.q);
- env->fregs[f1].ll = x1.ll.upper;
- env->fregs[f1 + 2].ll = x1.ll.lower;
- return set_cc_nz_f128(x1.q);
-}
-
-/* 32-bit FP addition RM */
-void HELPER(aeb)(uint32_t f1, uint32_t val)
-{
- float32 v1 = env->fregs[f1].l.upper;
- CPU_FloatU v2;
-
- v2.l = val;
- HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __func__,
- v1, f1, v2.f);
- env->fregs[f1].l.upper = float32_add(v1, v2.f, &env->fpu_status);
-}
-
-/* 32-bit FP division RM */
-void HELPER(deb)(uint32_t f1, uint32_t val)
-{
- float32 v1 = env->fregs[f1].l.upper;
- CPU_FloatU v2;
-
- v2.l = val;
- HELPER_LOG("%s: dividing 0x%d from f%d by 0x%d\n", __func__,
- v1, f1, v2.f);
- env->fregs[f1].l.upper = float32_div(v1, v2.f, &env->fpu_status);
-}
-
-/* 32-bit FP multiplication RM */
-void HELPER(meeb)(uint32_t f1, uint32_t val)
-{
- float32 v1 = env->fregs[f1].l.upper;
- CPU_FloatU v2;
-
- v2.l = val;
- HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __func__,
- v1, f1, v2.f);
- env->fregs[f1].l.upper = float32_mul(v1, v2.f, &env->fpu_status);
-}
-
-/* 32-bit FP compare RR */
-uint32_t HELPER(cebr)(uint32_t f1, uint32_t f2)
-{
- float32 v1 = env->fregs[f1].l.upper;
- float32 v2 = env->fregs[f2].l.upper;
-
- HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __func__,
- v1, f1, v2);
- return set_cc_f32(v1, v2);
-}
-
-/* 64-bit FP compare RR */
-uint32_t HELPER(cdbr)(uint32_t f1, uint32_t f2)
-{
- float64 v1 = env->fregs[f1].d;
- float64 v2 = env->fregs[f2].d;
-
- HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __func__,
- v1, f1, v2);
- return set_cc_f64(v1, v2);
-}
-
-/* 128-bit FP compare RR */
-uint32_t HELPER(cxbr)(uint32_t f1, uint32_t f2)
-{
- CPU_QuadU v1;
- CPU_QuadU v2;
-
- v1.ll.upper = env->fregs[f1].ll;
- v1.ll.lower = env->fregs[f1 + 2].ll;
- v2.ll.upper = env->fregs[f2].ll;
- v2.ll.lower = env->fregs[f2 + 2].ll;
-
- return float_comp_to_cc(float128_compare_quiet(v1.q, v2.q,
- &env->fpu_status));
-}
-
-/* 64-bit FP compare RM */
-uint32_t HELPER(cdb)(uint32_t f1, uint64_t a2)
-{
- float64 v1 = env->fregs[f1].d;
- CPU_DoubleU v2;
-
- v2.ll = ldq(a2);
- HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __func__, v1,
- f1, v2.d);
- return set_cc_f64(v1, v2.d);
-}
-
-/* 64-bit FP addition RM */
-uint32_t HELPER(adb)(uint32_t f1, uint64_t a2)
-{
- float64 v1 = env->fregs[f1].d;
- CPU_DoubleU v2;
-
- v2.ll = ldq(a2);
- HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __func__,
- v1, f1, v2.d);
- env->fregs[f1].d = v1 = float64_add(v1, v2.d, &env->fpu_status);
- return set_cc_nz_f64(v1);
-}
-
-/* 32-bit FP subtraction RM */
-void HELPER(seb)(uint32_t f1, uint32_t val)
-{
- float32 v1 = env->fregs[f1].l.upper;
- CPU_FloatU v2;
-
- v2.l = val;
- env->fregs[f1].l.upper = float32_sub(v1, v2.f, &env->fpu_status);
-}
-
-/* 64-bit FP subtraction RM */
-uint32_t HELPER(sdb)(uint32_t f1, uint64_t a2)
-{
- float64 v1 = env->fregs[f1].d;
- CPU_DoubleU v2;
-
- v2.ll = ldq(a2);
- env->fregs[f1].d = v1 = float64_sub(v1, v2.d, &env->fpu_status);
- return set_cc_nz_f64(v1);
-}
-
-/* 64-bit FP multiplication RM */
-void HELPER(mdb)(uint32_t f1, uint64_t a2)
-{
- float64 v1 = env->fregs[f1].d;
- CPU_DoubleU v2;
-
- v2.ll = ldq(a2);
- HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __func__,
- v1, f1, v2.d);
- env->fregs[f1].d = float64_mul(v1, v2.d, &env->fpu_status);
-}
-
-/* 64-bit FP division RM */
-void HELPER(ddb)(uint32_t f1, uint64_t a2)
-{
- float64 v1 = env->fregs[f1].d;
- CPU_DoubleU v2;
-
- v2.ll = ldq(a2);
- HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __func__,
- v1, f1, v2.d);
- env->fregs[f1].d = float64_div(v1, v2.d, &env->fpu_status);
-}
-
-static void set_round_mode(int m3)
-{
- switch (m3) {
- case 0:
- /* current mode */
- break;
- case 1:
- /* biased round no nearest */
- case 4:
- /* round to nearest */
- set_float_rounding_mode(float_round_nearest_even, &env->fpu_status);
- break;
- case 5:
- /* round to zero */
- set_float_rounding_mode(float_round_to_zero, &env->fpu_status);
- break;
- case 6:
- /* round to +inf */
- set_float_rounding_mode(float_round_up, &env->fpu_status);
- break;
- case 7:
- /* round to -inf */
- set_float_rounding_mode(float_round_down, &env->fpu_status);
- break;
- }
-}
-
-/* convert 32-bit float to 64-bit int */
-uint32_t HELPER(cgebr)(uint32_t r1, uint32_t f2, uint32_t m3)
-{
- float32 v2 = env->fregs[f2].l.upper;
-
- set_round_mode(m3);
- env->regs[r1] = float32_to_int64(v2, &env->fpu_status);
- return set_cc_nz_f32(v2);
-}
-
-/* convert 64-bit float to 64-bit int */
-uint32_t HELPER(cgdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
-{
- float64 v2 = env->fregs[f2].d;
-
- set_round_mode(m3);
- env->regs[r1] = float64_to_int64(v2, &env->fpu_status);
- return set_cc_nz_f64(v2);
-}
-
-/* convert 128-bit float to 64-bit int */
-uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
-{
- CPU_QuadU v2;
-
- v2.ll.upper = env->fregs[f2].ll;
- v2.ll.lower = env->fregs[f2 + 2].ll;
- set_round_mode(m3);
- env->regs[r1] = float128_to_int64(v2.q, &env->fpu_status);
- if (float128_is_any_nan(v2.q)) {
- return 3;
- } else if (float128_is_zero(v2.q)) {
- return 0;
- } else if (float128_is_neg(v2.q)) {
- return 1;
- } else {
- return 2;
- }
-}
-
-/* convert 32-bit float to 32-bit int */
-uint32_t HELPER(cfebr)(uint32_t r1, uint32_t f2, uint32_t m3)
-{
- float32 v2 = env->fregs[f2].l.upper;
-
- set_round_mode(m3);
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
- float32_to_int32(v2, &env->fpu_status);
- return set_cc_nz_f32(v2);
-}
-
-/* convert 64-bit float to 32-bit int */
-uint32_t HELPER(cfdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
-{
- float64 v2 = env->fregs[f2].d;
-
- set_round_mode(m3);
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
- float64_to_int32(v2, &env->fpu_status);
- return set_cc_nz_f64(v2);
-}
-
-/* convert 128-bit float to 32-bit int */
-uint32_t HELPER(cfxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
-{
- CPU_QuadU v2;
-
- v2.ll.upper = env->fregs[f2].ll;
- v2.ll.lower = env->fregs[f2 + 2].ll;
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
- float128_to_int32(v2.q, &env->fpu_status);
- return set_cc_nz_f128(v2.q);
-}
-
-/* load 32-bit FP zero */
-void HELPER(lzer)(uint32_t f1)
-{
- env->fregs[f1].l.upper = float32_zero;
-}
-
-/* load 64-bit FP zero */
-void HELPER(lzdr)(uint32_t f1)
-{
- env->fregs[f1].d = float64_zero;
-}
-
-/* load 128-bit FP zero */
-void HELPER(lzxr)(uint32_t f1)
-{
- CPU_QuadU x;
-
- x.q = float64_to_float128(float64_zero, &env->fpu_status);
- env->fregs[f1].ll = x.ll.upper;
- env->fregs[f1 + 1].ll = x.ll.lower;
-}
-
-/* 128-bit FP subtraction RR */
-uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
-{
- CPU_QuadU v1;
- CPU_QuadU v2;
- CPU_QuadU res;
-
- v1.ll.upper = env->fregs[f1].ll;
- v1.ll.lower = env->fregs[f1 + 2].ll;
- v2.ll.upper = env->fregs[f2].ll;
- v2.ll.lower = env->fregs[f2 + 2].ll;
- res.q = float128_sub(v1.q, v2.q, &env->fpu_status);
- env->fregs[f1].ll = res.ll.upper;
- env->fregs[f1 + 2].ll = res.ll.lower;
- return set_cc_nz_f128(res.q);
-}
-
-/* 128-bit FP addition RR */
-uint32_t HELPER(axbr)(uint32_t f1, uint32_t f2)
-{
- CPU_QuadU v1;
- CPU_QuadU v2;
- CPU_QuadU res;
-
- v1.ll.upper = env->fregs[f1].ll;
- v1.ll.lower = env->fregs[f1 + 2].ll;
- v2.ll.upper = env->fregs[f2].ll;
- v2.ll.lower = env->fregs[f2 + 2].ll;
- res.q = float128_add(v1.q, v2.q, &env->fpu_status);
- env->fregs[f1].ll = res.ll.upper;
- env->fregs[f1 + 2].ll = res.ll.lower;
- return set_cc_nz_f128(res.q);
-}
-
-/* 32-bit FP multiplication RR */
-void HELPER(meebr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].l.upper = float32_mul(env->fregs[f1].l.upper,
- env->fregs[f2].l.upper,
- &env->fpu_status);
-}
-
-/* 64-bit FP division RR */
-void HELPER(ddbr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].d = float64_div(env->fregs[f1].d, env->fregs[f2].d,
- &env->fpu_status);
-}
-
-/* 64-bit FP multiply and add RM */
-void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
-{
- CPU_DoubleU v2;
-
- HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __func__, f1, a2, f3);
- v2.ll = ldq(a2);
- env->fregs[f1].d = float64_add(env->fregs[f1].d,
- float64_mul(v2.d, env->fregs[f3].d,
- &env->fpu_status),
- &env->fpu_status);
-}
-
-/* 64-bit FP multiply and add RR */
-void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
-{
- HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
- env->fregs[f1].d = float64_add(float64_mul(env->fregs[f2].d,
- env->fregs[f3].d,
- &env->fpu_status),
- env->fregs[f1].d, &env->fpu_status);
-}
-
-/* 64-bit FP multiply and subtract RR */
-void HELPER(msdbr)(uint32_t f1, uint32_t f3, uint32_t f2)
-{
- HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
- env->fregs[f1].d = float64_sub(float64_mul(env->fregs[f2].d,
- env->fregs[f3].d,
- &env->fpu_status),
- env->fregs[f1].d, &env->fpu_status);
-}
-
-/* 32-bit FP multiply and add RR */
-void HELPER(maebr)(uint32_t f1, uint32_t f3, uint32_t f2)
-{
- env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
- float32_mul(env->fregs[f2].l.upper,
- env->fregs[f3].l.upper,
- &env->fpu_status),
- &env->fpu_status);
-}
-
-/* convert 32-bit float to 64-bit float */
-void HELPER(ldeb)(uint32_t f1, uint64_t a2)
-{
- uint32_t v2;
-
- v2 = ldl(a2);
- env->fregs[f1].d = float32_to_float64(v2,
- &env->fpu_status);
-}
-
-/* convert 64-bit float to 128-bit float */
-void HELPER(lxdb)(uint32_t f1, uint64_t a2)
-{
- CPU_DoubleU v2;
- CPU_QuadU v1;
-
- v2.ll = ldq(a2);
- v1.q = float64_to_float128(v2.d, &env->fpu_status);
- env->fregs[f1].ll = v1.ll.upper;
- env->fregs[f1 + 2].ll = v1.ll.lower;
-}
-
-/* test data class 32-bit */
-uint32_t HELPER(tceb)(uint32_t f1, uint64_t m2)
-{
- float32 v1 = env->fregs[f1].l.upper;
- int neg = float32_is_neg(v1);
- uint32_t cc = 0;
-
- HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, (long)v1, m2, neg);
- if ((float32_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
- (float32_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
- (float32_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
- (float32_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
- cc = 1;
- } else if (m2 & (1 << (9-neg))) {
- /* assume normalized number */
- cc = 1;
- }
-
- /* FIXME: denormalized? */
- return cc;
-}
-
-/* test data class 64-bit */
-uint32_t HELPER(tcdb)(uint32_t f1, uint64_t m2)
-{
- float64 v1 = env->fregs[f1].d;
- int neg = float64_is_neg(v1);
- uint32_t cc = 0;
-
- HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, v1, m2, neg);
- if ((float64_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
- (float64_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
- (float64_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
- (float64_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
- cc = 1;
- } else if (m2 & (1 << (9-neg))) {
- /* assume normalized number */
- cc = 1;
- }
- /* FIXME: denormalized? */
- return cc;
-}
-
-/* test data class 128-bit */
-uint32_t HELPER(tcxb)(uint32_t f1, uint64_t m2)
-{
- CPU_QuadU v1;
- uint32_t cc = 0;
- int neg;
-
- v1.ll.upper = env->fregs[f1].ll;
- v1.ll.lower = env->fregs[f1 + 2].ll;
-
- neg = float128_is_neg(v1.q);
- if ((float128_is_zero(v1.q) && (m2 & (1 << (11-neg)))) ||
- (float128_is_infinity(v1.q) && (m2 & (1 << (5-neg)))) ||
- (float128_is_any_nan(v1.q) && (m2 & (1 << (3-neg)))) ||
- (float128_is_signaling_nan(v1.q) && (m2 & (1 << (1-neg))))) {
- cc = 1;
- } else if (m2 & (1 << (9-neg))) {
- /* assume normalized number */
- cc = 1;
- }
- /* FIXME: denormalized? */
- return cc;
-}
-
/* find leftmost one */
uint32_t HELPER(flogr)(uint32_t r1, uint64_t v2)
{
@@ -1795,12 +999,6 @@ uint32_t HELPER(flogr)(uint32_t r1, uint64_t v2)
}
}
-/* square root 64-bit RR */
-void HELPER(sqdbr)(uint32_t f1, uint32_t f2)
-{
- env->fregs[f1].d = float64_sqrt(env->fregs[f2].d, &env->fpu_status);
-}
-
/* checksum */
void HELPER(cksm)(uint32_t r1, uint32_t r2)
{
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 1c1baf5..c370df3 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -667,16 +667,11 @@ static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2)
s->cc_op = CC_OP_LTGT_F32;
}
-static void set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
+static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
{
gen_op_update1_cc_i32(s, CC_OP_NZ_F32, v1);
}
-static inline void set_cc_nz_f64(DisasContext *s, TCGv_i64 v1)
-{
- gen_op_update1_cc_i64(s, CC_OP_NZ_F64, v1);
-}
-
/* CC value is in env->cc_op */
static inline void set_cc_static(DisasContext *s)
{
@@ -2235,7 +2230,7 @@ static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
tcg_temp_free_i32(tmp32);
tmp32 = load_freg32(r1);
- set_cc_nz_f32(s, tmp32);
+ gen_set_cc_nz_f32(s, tmp32);
tcg_temp_free_i32(tmp32);
break;
case 0xb: /* SEB R1,D2(X2,B2) [RXE] */
@@ -2248,7 +2243,7 @@ static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
tcg_temp_free_i32(tmp32);
tmp32 = load_freg32(r1);
- set_cc_nz_f32(s, tmp32);
+ gen_set_cc_nz_f32(s, tmp32);
tcg_temp_free_i32(tmp32);
break;
case 0xd: /* DEB R1,D2(X2,B2) [RXE] */
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-02 17:33 ` [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops Blue Swirl
@ 2012-09-04 18:42 ` Richard Henderson
2012-09-04 19:40 ` Blue Swirl
0 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2012-09-04 18:42 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel, Alexander Graf
On 09/02/2012 10:33 AM, Blue Swirl wrote:
> +/* fpu_helper.c */
> +uint32_t set_cc_f32(float32 v1, float32 v2);
> +uint32_t set_cc_f64(float64 v1, float64 v2);
> +uint32_t set_cc_nz_f32(float32 v);
> +uint32_t set_cc_nz_f64(float64 v);
> +
I think that the CC handling should stay together, regardless of FPU-ness.
These functions are quite small and can be usefully inlined by the compiler.
OTOH, this is much easier to do with my translate.c rewrite, so maybe I'll
just take responsibility for moving them back...
r~
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-04 18:42 ` Richard Henderson
@ 2012-09-04 19:40 ` Blue Swirl
2012-09-04 22:03 ` Richard Henderson
0 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-04 19:40 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Alexander Graf
On Tue, Sep 4, 2012 at 6:42 PM, Richard Henderson <rth@twiddle.net> wrote:
> On 09/02/2012 10:33 AM, Blue Swirl wrote:
>> +/* fpu_helper.c */
>> +uint32_t set_cc_f32(float32 v1, float32 v2);
>> +uint32_t set_cc_f64(float64 v1, float64 v2);
>> +uint32_t set_cc_nz_f32(float32 v);
>> +uint32_t set_cc_nz_f64(float64 v);
>> +
>
> I think that the CC handling should stay together, regardless of FPU-ness.
> These functions are quite small and can be usefully inlined by the compiler.
>
> OTOH, this is much easier to do with my translate.c rewrite, so maybe I'll
> just take responsibility for moving them back...
The problem is that these are used by some FPU ops as well as
condition code ops. Maybe it's better to move them to cpu.h as inline
functions?
It could be also possible to upgrade condition code functions to full
helpers, that could help implementing lazy condition code evaluation.
I noticed that the helpers don't use TCGv registers for register
access but instead the helpers access env->regs[] and env->fregs[]
directly, this probably would need to be changed too.
>
>
> r~
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-04 19:40 ` Blue Swirl
@ 2012-09-04 22:03 ` Richard Henderson
2012-09-05 3:46 ` Alexander Graf
0 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2012-09-04 22:03 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel, Alexander Graf
On 09/04/2012 12:40 PM, Blue Swirl wrote:
> On Tue, Sep 4, 2012 at 6:42 PM, Richard Henderson <rth@twiddle.net> wrote:
>> On 09/02/2012 10:33 AM, Blue Swirl wrote:
>>> +/* fpu_helper.c */
>>> +uint32_t set_cc_f32(float32 v1, float32 v2);
>>> +uint32_t set_cc_f64(float64 v1, float64 v2);
>>> +uint32_t set_cc_nz_f32(float32 v);
>>> +uint32_t set_cc_nz_f64(float64 v);
>>> +
>>
>> I think that the CC handling should stay together, regardless of FPU-ness.
>> These functions are quite small and can be usefully inlined by the compiler.
>>
>> OTOH, this is much easier to do with my translate.c rewrite, so maybe I'll
>> just take responsibility for moving them back...
>
> The problem is that these are used by some FPU ops as well as
> condition code ops. Maybe it's better to move them to cpu.h as inline
> functions?
Maybe...
> It could be also possible to upgrade condition code functions to full
> helpers, that could help implementing lazy condition code evaluation.
Done and ...
> I noticed that the helpers don't use TCGv registers for register
> access but instead the helpers access env->regs[] and env->fregs[]
> directly, this probably would need to be changed too.
done, in my rewrite.
Except for float128, where we can't return such by value inside TCG.
And, annoyingly, s390 float128 values are held in %fN/%fN+2, so the
values are not contiguous in memory. I momentarily considered passing
a pointer to %fN, letting the helper access f[0]/f[2], but in the end
I didn't consider that any better than just passing the integer N.
So after the rewrite, set_cc_nz_f32/64 are not referenced from the fp
helpers directly. We still reference set_cc_nz_f128 from ADXBR and SDXBR.
r~
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-04 22:03 ` Richard Henderson
@ 2012-09-05 3:46 ` Alexander Graf
2012-09-05 15:34 ` Richard Henderson
0 siblings, 1 reply; 64+ messages in thread
From: Alexander Graf @ 2012-09-05 3:46 UTC (permalink / raw)
To: Richard Henderson; +Cc: Blue Swirl, qemu-devel
On 04.09.2012, at 18:03, Richard Henderson wrote:
> On 09/04/2012 12:40 PM, Blue Swirl wrote:
>> On Tue, Sep 4, 2012 at 6:42 PM, Richard Henderson <rth@twiddle.net> wrote:
>>> On 09/02/2012 10:33 AM, Blue Swirl wrote:
>>>> +/* fpu_helper.c */
>>>> +uint32_t set_cc_f32(float32 v1, float32 v2);
>>>> +uint32_t set_cc_f64(float64 v1, float64 v2);
>>>> +uint32_t set_cc_nz_f32(float32 v);
>>>> +uint32_t set_cc_nz_f64(float64 v);
>>>> +
>>>
>>> I think that the CC handling should stay together, regardless of FPU-ness.
>>> These functions are quite small and can be usefully inlined by the compiler.
>>>
>>> OTOH, this is much easier to do with my translate.c rewrite, so maybe I'll
>>> just take responsibility for moving them back...
>>
>> The problem is that these are used by some FPU ops as well as
>> condition code ops. Maybe it's better to move them to cpu.h as inline
>> functions?
>
> Maybe...
>
>> It could be also possible to upgrade condition code functions to full
>> helpers, that could help implementing lazy condition code evaluation.
>
> Done and ...
>
>> I noticed that the helpers don't use TCGv registers for register
>> access but instead the helpers access env->regs[] and env->fregs[]
>> directly, this probably would need to be changed too.
>
> done, in my rewrite.
So that means your rewrite is based on this series and just fixes it up? Does that mean if I apply this patch, you will be all happy?
Alex
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-05 3:46 ` Alexander Graf
@ 2012-09-05 15:34 ` Richard Henderson
2012-09-06 3:38 ` Alexander Graf
2012-09-06 18:42 ` Alexander Graf
0 siblings, 2 replies; 64+ messages in thread
From: Richard Henderson @ 2012-09-05 15:34 UTC (permalink / raw)
To: Alexander Graf; +Cc: Blue Swirl, qemu-devel
On 09/04/2012 08:46 PM, Alexander Graf wrote:
> So that means your rewrite is based on this series and just fixes it up? Does that mean if I apply this patch, you will be all happy?
It is not (yet) based on this series. But I will be happy if you apply it, since it's easier for me to rebase off master than find an external tree.
r~
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-05 15:34 ` Richard Henderson
@ 2012-09-06 3:38 ` Alexander Graf
2012-09-06 18:42 ` Alexander Graf
1 sibling, 0 replies; 64+ messages in thread
From: Alexander Graf @ 2012-09-06 3:38 UTC (permalink / raw)
To: Richard Henderson; +Cc: Blue Swirl, qemu-devel
On 05.09.2012, at 11:34, Richard Henderson wrote:
> On 09/04/2012 08:46 PM, Alexander Graf wrote:
>> So that means your rewrite is based on this series and just fixes it up? Does that mean if I apply this patch, you will be all happy?
>
> It is not (yet) based on this series. But I will be happy if you apply it, since it's easier for me to rebase off master than find an external tree.
Ok, I need a bit more concentration that I can get now for that though and will hop on a reasonably long plane flight in a few hours. Will apply / review it afterwards, though I don't expect too many problems.
Thus you might be easier off to rebase your series early on on top of Blue's patch set.
Alex
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-05 15:34 ` Richard Henderson
2012-09-06 3:38 ` Alexander Graf
@ 2012-09-06 18:42 ` Alexander Graf
2012-09-06 20:29 ` Richard Henderson
1 sibling, 1 reply; 64+ messages in thread
From: Alexander Graf @ 2012-09-06 18:42 UTC (permalink / raw)
To: Richard Henderson; +Cc: Blue Swirl, qemu-devel
On 05.09.2012, at 11:34, Richard Henderson wrote:
> On 09/04/2012 08:46 PM, Alexander Graf wrote:
>> So that means your rewrite is based on this series and just fixes it up? Does that mean if I apply this patch, you will be all happy?
>
> It is not (yet) based on this series. But I will be happy if you apply it, since it's easier for me to rebase off master than find an external tree.
Richard, while at it, could you please check the s390x tcg target? Running any target on there seems to break in the TLB code for me. I'm mostly surprised by the env value. Why is that a 32-bit pointer?
agraf@s390t27:/home/agraf/git/qemu> gdb --args ./x86_64-softmmu/qemu-system-x86_64 -nographic
GNU gdb (GDB) SUSE (7.0-0.4.16)
Copyright (C) 2009 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law. Type "show copying"
and "show warranty" for details.
This GDB was configured as "s390x-suse-linux".
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>...
Reading symbols from /busu/home/agraf/git/qemu/x86_64-softmmu/qemu-system-x86_64...done.
(gdb)
(gdb) r
Starting program: /busu/home/agraf/git/qemu/x86_64-softmmu/qemu-system-x86_64 -nographic
Missing separate debuginfo for /usr/lib64/libgthread-2.0.so.0
Try: zypper install -C "debuginfo(build-id)=912d1dd1cc78c1a77aec3a03f332a4c3496f5f86"
Missing separate debuginfo for /usr/lib64/libglib-2.0.so.0
Try: zypper install -C "debuginfo(build-id)=954bad2ed93e5ef700ba03fcd4f6c00e7e0c9d30"
Missing separate debuginfo for /usr/lib64/libcurl.so.4
Try: zypper install -C "debuginfo(build-id)=05142779be2ae2320d2b0bb942826156ae5c5d81"
Missing separate debuginfo for /lib64/libncurses.so.5
Try: zypper install -C "debuginfo(build-id)=8091f2982d62f10a40de0e2cd7f2bf74a51f27dc"
Missing separate debuginfo for /lib64/libuuid.so.1
Try: zypper install -C "debuginfo(build-id)=13fbf62f145bc4386a0f4bff001f7dd01c8d78c2"
Missing separate debuginfo for /usr/lib64/libpng12.so.0
Try: zypper install -C "debuginfo(build-id)=0af6bdbd02f42fea039cf733c79c8573f509fca6"
Missing separate debuginfo for /usr/lib64/libjpeg.so.62
Try: zypper install -C "debuginfo(build-id)=af2dbf4b5dca2ceb485194bb67411269cb6375a5"
Missing separate debuginfo for /usr/lib64/libSDL-1.2.so.0
Try: zypper install -C "debuginfo(build-id)=56ac12212e5cc91d4fcc5ea1f68f7bd027587950"
[Thread debugging using libthread_db enabled]
Missing separate debuginfo for /usr/lib64/libX11.so.6
Try: zypper install -C "debuginfo(build-id)=043834a023c164696ce660041637a4f8b56e1f20"
Missing separate debuginfo for /lib64/libaio.so.1
Try: zypper install -C "debuginfo(build-id)=94043f928d23ab60fa78117484f77e1f27212fcc"
Missing separate debuginfo for /lib64/libz.so.1
Try: zypper install -C "debuginfo(build-id)=5340452e3b691d56fbd88258e8236f0baf6e7f54"
Missing separate debuginfo for /usr/lib64/libpcre.so.0
Try: zypper install -C "debuginfo(build-id)=dfef694ea1c5f6e5229a26bd1b7679a4b47b6b45"
Missing separate debuginfo for /usr/lib64/libidn.so.11
Try: zypper install -C "debuginfo(build-id)=5d726f3349ab522b5f19d6dcb86bca442a0826e4"
Missing separate debuginfo for /usr/lib64/libssl.so.0.9.8
Try: zypper install -C "debuginfo(build-id)=f2b46706fcbc46a3d2bc436e23fd61afc5c68042"
Missing separate debuginfo for /usr/lib64/libcrypto.so.0.9.8
Try: zypper install -C "debuginfo(build-id)=e8df586992c4aaa050278f62546b8bee2071a72f"
Missing separate debuginfo for /usr/lib64/libldap-2.4.so.2
Try: zypper install -C "debuginfo(build-id)=5b0599064e1c76fad7b3a3a9a9b4a1290a9f31a3"
Missing separate debuginfo for /usr/lib64/libgssapi_krb5.so.2
Try: zypper install -C "debuginfo(build-id)=76ad9b9a23735144169c1e5bc554f6b4ceea7a9e"
Missing separate debuginfo for /usr/lib64/libkrb5.so.3
Try: zypper install -C "debuginfo(build-id)=69277cfebb420879ae3a613f8c527bec87944723"
Missing separate debuginfo for /usr/lib64/libk5crypto.so.3
Try: zypper install -C "debuginfo(build-id)=93cc48f64e299f939fa169d714a0124cbab52976"
Missing separate debuginfo for /lib64/libcom_err.so.2
Try: zypper install -C "debuginfo(build-id)=09b7c836eb5edfad54802a9f9bea475f49758324"
Missing separate debuginfo for /lib64/libkeyutils.so.1
Try: zypper install -C "debuginfo(build-id)=454eb6d36012309dd468b31a37cdb58bf737ceaf"
Missing separate debuginfo for /usr/lib64/libXext.so.6
Try: zypper install -C "debuginfo(build-id)=1fecbb7e295db9aa8a87e904df04e64dc03a38d1"
Missing separate debuginfo for /usr/lib64/libXrandr.so.2
Try: zypper install -C "debuginfo(build-id)=8e8ab17f4153f6077fde8e44994ebe8667cfca6d"
Missing separate debuginfo for /usr/lib64/libXrender.so.1
Try: zypper install -C "debuginfo(build-id)=66994ad09a7123bc4aba4c05bf400d2b6bcf41ae"
Missing separate debuginfo for /usr/lib64/libxcb-xlib.so.0
Try: zypper install -C "debuginfo(build-id)=ee68d8a43e76db5e57e128bc147776c11399c40d"
Missing separate debuginfo for /usr/lib64/libxcb.so.1
Try: zypper install -C "debuginfo(build-id)=3ce6949599f374425a4b048ce63cbb30ab1ea7dd"
Missing separate debuginfo for /usr/lib64/libXau.so.6
Try: zypper install -C "debuginfo(build-id)=ba73feac91333c26c68ba1195a590f9ff83537c9"
Missing separate debuginfo for /usr/lib64/liblber-2.4.so.2
Try: zypper install -C "debuginfo(build-id)=56f332be7ff53c901a40fb882a5f0e7558abd4e3"
Missing separate debuginfo for /usr/lib64/libsasl2.so.2
Try: zypper install -C "debuginfo(build-id)=a2a0fd47f37abcb1ba316b2405fca1429083762b"
Missing separate debuginfo for /usr/lib64/libkrb5support.so.0
Try: zypper install -C "debuginfo(build-id)=f70fdaa77398afa48d84be4598a55251cdc57bda"
[New Thread 0x20003533910 (LWP 3712)]
[New Thread 0x2000bf35910 (LWP 3713)]
QEMU 1.2.50 monitor - type 'help' for more information
(qemu) QEMU 1.2.50 monitor - type 'help' for more information
(qemu)
Program received signal SIGSEGV, Segmentation fault.
[Switching to Thread 0x20003533910 (LWP 3712)]
helper_stl_mmu (env=0x80d1daf0, addr=28647, val=29360191, mmu_idx=55782644) at /home/agraf/git/qemu/softmmu_template.h:268
268 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
(gdb) q
A debugging session is active.
Inferior 1 [process 3709] will be killed.
Quit anyway? (y or n) y
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-06 18:42 ` Alexander Graf
@ 2012-09-06 20:29 ` Richard Henderson
2012-09-07 4:26 ` Alexander Graf
0 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2012-09-06 20:29 UTC (permalink / raw)
To: Alexander Graf; +Cc: Blue Swirl, qemu-devel
On 09/06/2012 11:42 AM, Alexander Graf wrote:
> Richard, while at it, could you please check the s390x tcg target?
> Running any target on there seems to break in the TLB code for me.
I did successfully run a simple linux-user test directly off blue's
patch set. It exercised a bit of fp and system calls (printf).
I don't have a system environment set up at the moment...
> I'm mostly surprised by the env value. Why is that a 32-bit pointer?
It depends on where objects get loaded in memory of course. I don't
think there's anything particularly surprising about an object loaded
into the load 32-bits.
That mmu_idx on the other hand... one begins to wonder if the debugger
is actually lying to you.
r~
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-06 20:29 ` Richard Henderson
@ 2012-09-07 4:26 ` Alexander Graf
2012-09-07 14:30 ` Andreas Färber
0 siblings, 1 reply; 64+ messages in thread
From: Alexander Graf @ 2012-09-07 4:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: Blue Swirl, qemu-devel
Quoting Richard Henderson <rth@twiddle.net>:
> On 09/06/2012 11:42 AM, Alexander Graf wrote:
>> Richard, while at it, could you please check the s390x tcg target?
>> Running any target on there seems to break in the TLB code for me.
>
> I did successfully run a simple linux-user test directly off blue's
> patch set. It exercised a bit of fp and system calls (printf).
>
> I don't have a system environment set up at the moment...
Ah, I am referring to s390x host code. Running qemu-system-x86_64 on
s390x is what breaks for me.
Alex
>
>> I'm mostly surprised by the env value. Why is that a 32-bit pointer?
>
> It depends on where objects get loaded in memory of course. I don't
> think there's anything particularly surprising about an object loaded
> into the load 32-bits.
>
> That mmu_idx on the other hand... one begins to wonder if the debugger
> is actually lying to you.
>
>
> r~
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-07 4:26 ` Alexander Graf
@ 2012-09-07 14:30 ` Andreas Färber
2012-09-07 14:42 ` Aurelien Jarno
0 siblings, 1 reply; 64+ messages in thread
From: Andreas Färber @ 2012-09-07 14:30 UTC (permalink / raw)
To: Alexander Graf; +Cc: Blue Swirl, qemu-devel, Richard Henderson
Am 07.09.2012 06:26, schrieb Alexander Graf:
> Quoting Richard Henderson <rth@twiddle.net>:
>
>> On 09/06/2012 11:42 AM, Alexander Graf wrote:
>>> Richard, while at it, could you please check the s390x tcg target?
>>> Running any target on there seems to break in the TLB code for me.
>>
>> I did successfully run a simple linux-user test directly off blue's
>> patch set. It exercised a bit of fp and system calls (printf).
>>
>> I don't have a system environment set up at the moment...
>
> Ah, I am referring to s390x host code. Running qemu-system-x86_64 on
> s390x is what breaks for me.
If, e.g., arm works on master that might rather point to tcg/s390x/
CONFIG_PASS_AREG0 mode.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops
2012-09-07 14:30 ` Andreas Färber
@ 2012-09-07 14:42 ` Aurelien Jarno
0 siblings, 0 replies; 64+ messages in thread
From: Aurelien Jarno @ 2012-09-07 14:42 UTC (permalink / raw)
To: Andreas Färber
Cc: Blue Swirl, Richard Henderson, Alexander Graf, qemu-devel
On Fri, Sep 07, 2012 at 04:30:51PM +0200, Andreas Färber wrote:
> Am 07.09.2012 06:26, schrieb Alexander Graf:
> > Quoting Richard Henderson <rth@twiddle.net>:
> >
> >> On 09/06/2012 11:42 AM, Alexander Graf wrote:
> >>> Richard, while at it, could you please check the s390x tcg target?
> >>> Running any target on there seems to break in the TLB code for me.
> >>
> >> I did successfully run a simple linux-user test directly off blue's
> >> patch set. It exercised a bit of fp and system calls (printf).
> >>
> >> I don't have a system environment set up at the moment...
> >
> > Ah, I am referring to s390x host code. Running qemu-system-x86_64 on
> > s390x is what breaks for me.
>
> If, e.g., arm works on master that might rather point to tcg/s390x/
> CONFIG_PASS_AREG0 mode.
>
This is likely the case. The register shift code in CONFIG_PASS_AREG0
case uses 3 registers for stores and 4 for loads. It should be the
reverse.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread
* [Qemu-devel] [PATCH 03/21] target-s390x: split condition code helpers
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 01/21] target-s390x: fix style Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 02/21] target-s390x: split FPU ops Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 04/21] target-s390x: split integer helpers Blue Swirl
` (18 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Move condition code helpers to cc_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
target-s390x/Makefile.objs | 3 +-
target-s390x/cc_helper.c | 551 ++++++++++++++++++++++++++++++++++++++++++++
target-s390x/cpu.h | 3 +
target-s390x/op_helper.c | 522 +-----------------------------------------
4 files changed, 557 insertions(+), 522 deletions(-)
create mode 100644 target-s390x/cc_helper.c
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index 23b3bd9..f9437d6 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -1,7 +1,8 @@
obj-y += translate.o op_helper.o helper.o cpu.o interrupt.o
-obj-y += fpu_helper.o
+obj-y += fpu_helper.o cc_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o
$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/fpu_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
+$(obj)/cc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c
new file mode 100644
index 0000000..2ac1659
--- /dev/null
+++ b/target-s390x/cc_helper.c
@@ -0,0 +1,551 @@
+/*
+ * S/390 condition code helper routines
+ *
+ * Copyright (c) 2009 Ulrich Hecht
+ * Copyright (c) 2009 Alexander Graf
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "dyngen-exec.h"
+#include "helper.h"
+
+/* #define DEBUG_HELPER */
+#ifdef DEBUG_HELPER
+#define HELPER_LOG(x...) qemu_log(x)
+#else
+#define HELPER_LOG(x...)
+#endif
+
+static inline uint32_t cc_calc_ltgt_32(CPUS390XState *env, int32_t src,
+ int32_t dst)
+{
+ if (src == dst) {
+ return 0;
+ } else if (src < dst) {
+ return 1;
+ } else {
+ return 2;
+ }
+}
+
+static inline uint32_t cc_calc_ltgt0_32(CPUS390XState *env, int32_t dst)
+{
+ return cc_calc_ltgt_32(env, dst, 0);
+}
+
+static inline uint32_t cc_calc_ltgt_64(CPUS390XState *env, int64_t src,
+ int64_t dst)
+{
+ if (src == dst) {
+ return 0;
+ } else if (src < dst) {
+ return 1;
+ } else {
+ return 2;
+ }
+}
+
+static inline uint32_t cc_calc_ltgt0_64(CPUS390XState *env, int64_t dst)
+{
+ return cc_calc_ltgt_64(env, dst, 0);
+}
+
+static inline uint32_t cc_calc_ltugtu_32(CPUS390XState *env, uint32_t src,
+ uint32_t dst)
+{
+ if (src == dst) {
+ return 0;
+ } else if (src < dst) {
+ return 1;
+ } else {
+ return 2;
+ }
+}
+
+static inline uint32_t cc_calc_ltugtu_64(CPUS390XState *env, uint64_t src,
+ uint64_t dst)
+{
+ if (src == dst) {
+ return 0;
+ } else if (src < dst) {
+ return 1;
+ } else {
+ return 2;
+ }
+}
+
+static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val,
+ uint32_t mask)
+{
+ uint16_t r = val & mask;
+
+ HELPER_LOG("%s: val 0x%x mask 0x%x\n", __func__, val, mask);
+ if (r == 0 || mask == 0) {
+ return 0;
+ } else if (r == mask) {
+ return 3;
+ } else {
+ return 1;
+ }
+}
+
+/* set condition code for test under mask */
+static inline uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val,
+ uint32_t mask)
+{
+ uint16_t r = val & mask;
+
+ HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __func__, val, mask, r);
+ if (r == 0 || mask == 0) {
+ return 0;
+ } else if (r == mask) {
+ return 3;
+ } else {
+ while (!(mask & 0x8000)) {
+ mask <<= 1;
+ val <<= 1;
+ }
+ if (val & 0x8000) {
+ return 2;
+ } else {
+ return 1;
+ }
+ }
+}
+
+static inline uint32_t cc_calc_nz(CPUS390XState *env, uint64_t dst)
+{
+ return !!dst;
+}
+
+static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1,
+ int64_t a2, int64_t ar)
+{
+ if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
+ return 3; /* overflow */
+ } else {
+ if (ar < 0) {
+ return 1;
+ } else if (ar > 0) {
+ return 2;
+ } else {
+ return 0;
+ }
+ }
+}
+
+static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1,
+ uint64_t a2, uint64_t ar)
+{
+ if (ar == 0) {
+ if (a1) {
+ return 2;
+ } else {
+ return 0;
+ }
+ } else {
+ if (ar < a1 || ar < a2) {
+ return 3;
+ } else {
+ return 1;
+ }
+ }
+}
+
+static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1,
+ int64_t a2, int64_t ar)
+{
+ if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
+ return 3; /* overflow */
+ } else {
+ if (ar < 0) {
+ return 1;
+ } else if (ar > 0) {
+ return 2;
+ } else {
+ return 0;
+ }
+ }
+}
+
+static inline uint32_t cc_calc_subu_64(CPUS390XState *env, uint64_t a1,
+ uint64_t a2, uint64_t ar)
+{
+ if (ar == 0) {
+ return 2;
+ } else {
+ if (a2 > a1) {
+ return 1;
+ } else {
+ return 3;
+ }
+ }
+}
+
+static inline uint32_t cc_calc_abs_64(CPUS390XState *env, int64_t dst)
+{
+ if ((uint64_t)dst == 0x8000000000000000ULL) {
+ return 3;
+ } else if (dst) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+static inline uint32_t cc_calc_nabs_64(CPUS390XState *env, int64_t dst)
+{
+ return !!dst;
+}
+
+static inline uint32_t cc_calc_comp_64(CPUS390XState *env, int64_t dst)
+{
+ if ((uint64_t)dst == 0x8000000000000000ULL) {
+ return 3;
+ } else if (dst < 0) {
+ return 1;
+ } else if (dst > 0) {
+ return 2;
+ } else {
+ return 0;
+ }
+}
+
+
+static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1,
+ int32_t a2, int32_t ar)
+{
+ if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
+ return 3; /* overflow */
+ } else {
+ if (ar < 0) {
+ return 1;
+ } else if (ar > 0) {
+ return 2;
+ } else {
+ return 0;
+ }
+ }
+}
+
+static inline uint32_t cc_calc_addu_32(CPUS390XState *env, uint32_t a1,
+ uint32_t a2, uint32_t ar)
+{
+ if (ar == 0) {
+ if (a1) {
+ return 2;
+ } else {
+ return 0;
+ }
+ } else {
+ if (ar < a1 || ar < a2) {
+ return 3;
+ } else {
+ return 1;
+ }
+ }
+}
+
+static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1,
+ int32_t a2, int32_t ar)
+{
+ if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
+ return 3; /* overflow */
+ } else {
+ if (ar < 0) {
+ return 1;
+ } else if (ar > 0) {
+ return 2;
+ } else {
+ return 0;
+ }
+ }
+}
+
+static inline uint32_t cc_calc_subu_32(CPUS390XState *env, uint32_t a1,
+ uint32_t a2, uint32_t ar)
+{
+ if (ar == 0) {
+ return 2;
+ } else {
+ if (a2 > a1) {
+ return 1;
+ } else {
+ return 3;
+ }
+ }
+}
+
+static inline uint32_t cc_calc_abs_32(CPUS390XState *env, int32_t dst)
+{
+ if ((uint32_t)dst == 0x80000000UL) {
+ return 3;
+ } else if (dst) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+static inline uint32_t cc_calc_nabs_32(CPUS390XState *env, int32_t dst)
+{
+ return !!dst;
+}
+
+static inline uint32_t cc_calc_comp_32(CPUS390XState *env, int32_t dst)
+{
+ if ((uint32_t)dst == 0x80000000UL) {
+ return 3;
+ } else if (dst < 0) {
+ return 1;
+ } else if (dst > 0) {
+ return 2;
+ } else {
+ return 0;
+ }
+}
+
+/* calculate condition code for insert character under mask insn */
+static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask,
+ uint32_t val)
+{
+ uint32_t cc;
+
+ HELPER_LOG("%s: mask 0x%x val %d\n", __func__, mask, val);
+ if (mask == 0xf) {
+ if (!val) {
+ return 0;
+ } else if (val & 0x80000000) {
+ return 1;
+ } else {
+ return 2;
+ }
+ }
+
+ if (!val || !mask) {
+ cc = 0;
+ } else {
+ while (mask != 1) {
+ mask >>= 1;
+ val >>= 8;
+ }
+ if (val & 0x80) {
+ cc = 1;
+ } else {
+ cc = 2;
+ }
+ }
+ return cc;
+}
+
+static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src,
+ uint64_t shift)
+{
+ uint64_t mask = ((1ULL << shift) - 1ULL) << (64 - shift);
+ uint64_t match, r;
+
+ /* check if the sign bit stays the same */
+ if (src & (1ULL << 63)) {
+ match = mask;
+ } else {
+ match = 0;
+ }
+
+ if ((src & mask) != match) {
+ /* overflow */
+ return 3;
+ }
+
+ r = ((src << shift) & ((1ULL << 63) - 1)) | (src & (1ULL << 63));
+
+ if ((int64_t)r == 0) {
+ return 0;
+ } else if ((int64_t)r < 0) {
+ return 1;
+ }
+
+ return 2;
+}
+
+
+static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
+ uint64_t src, uint64_t dst, uint64_t vr)
+{
+ uint32_t r = 0;
+
+ switch (cc_op) {
+ case CC_OP_CONST0:
+ case CC_OP_CONST1:
+ case CC_OP_CONST2:
+ case CC_OP_CONST3:
+ /* cc_op value _is_ cc */
+ r = cc_op;
+ break;
+ case CC_OP_LTGT0_32:
+ r = cc_calc_ltgt0_32(env, dst);
+ break;
+ case CC_OP_LTGT0_64:
+ r = cc_calc_ltgt0_64(env, dst);
+ break;
+ case CC_OP_LTGT_32:
+ r = cc_calc_ltgt_32(env, src, dst);
+ break;
+ case CC_OP_LTGT_64:
+ r = cc_calc_ltgt_64(env, src, dst);
+ break;
+ case CC_OP_LTUGTU_32:
+ r = cc_calc_ltugtu_32(env, src, dst);
+ break;
+ case CC_OP_LTUGTU_64:
+ r = cc_calc_ltugtu_64(env, src, dst);
+ break;
+ case CC_OP_TM_32:
+ r = cc_calc_tm_32(env, src, dst);
+ break;
+ case CC_OP_TM_64:
+ r = cc_calc_tm_64(env, src, dst);
+ break;
+ case CC_OP_NZ:
+ r = cc_calc_nz(env, dst);
+ break;
+ case CC_OP_ADD_64:
+ r = cc_calc_add_64(env, src, dst, vr);
+ break;
+ case CC_OP_ADDU_64:
+ r = cc_calc_addu_64(env, src, dst, vr);
+ break;
+ case CC_OP_SUB_64:
+ r = cc_calc_sub_64(env, src, dst, vr);
+ break;
+ case CC_OP_SUBU_64:
+ r = cc_calc_subu_64(env, src, dst, vr);
+ break;
+ case CC_OP_ABS_64:
+ r = cc_calc_abs_64(env, dst);
+ break;
+ case CC_OP_NABS_64:
+ r = cc_calc_nabs_64(env, dst);
+ break;
+ case CC_OP_COMP_64:
+ r = cc_calc_comp_64(env, dst);
+ break;
+
+ case CC_OP_ADD_32:
+ r = cc_calc_add_32(env, src, dst, vr);
+ break;
+ case CC_OP_ADDU_32:
+ r = cc_calc_addu_32(env, src, dst, vr);
+ break;
+ case CC_OP_SUB_32:
+ r = cc_calc_sub_32(env, src, dst, vr);
+ break;
+ case CC_OP_SUBU_32:
+ r = cc_calc_subu_32(env, src, dst, vr);
+ break;
+ case CC_OP_ABS_32:
+ r = cc_calc_abs_64(env, dst);
+ break;
+ case CC_OP_NABS_32:
+ r = cc_calc_nabs_64(env, dst);
+ break;
+ case CC_OP_COMP_32:
+ r = cc_calc_comp_32(env, dst);
+ break;
+
+ case CC_OP_ICM:
+ r = cc_calc_icm_32(env, src, dst);
+ break;
+ case CC_OP_SLAG:
+ r = cc_calc_slag(env, src, dst);
+ break;
+
+ case CC_OP_LTGT_F32:
+ r = set_cc_f32(src, dst);
+ break;
+ case CC_OP_LTGT_F64:
+ r = set_cc_f64(src, dst);
+ break;
+ case CC_OP_NZ_F32:
+ r = set_cc_nz_f32(dst);
+ break;
+ case CC_OP_NZ_F64:
+ r = set_cc_nz_f64(dst);
+ break;
+
+ default:
+ cpu_abort(env, "Unknown CC operation: %s\n", cc_name(cc_op));
+ }
+
+ HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__,
+ cc_name(cc_op), src, dst, vr, r);
+ return r;
+}
+
+uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
+ uint64_t vr)
+{
+ return do_calc_cc(env, cc_op, src, dst, vr);
+}
+
+uint32_t HELPER(calc_cc)(uint32_t cc_op, uint64_t src, uint64_t dst,
+ uint64_t vr)
+{
+ return do_calc_cc(env, cc_op, src, dst, vr);
+}
+
+/* insert psw mask and condition code into r1 */
+void HELPER(ipm)(uint32_t cc, uint32_t r1)
+{
+ uint64_t r = env->regs[r1];
+
+ r &= 0xffffffff00ffffffULL;
+ r |= (cc << 28) | ((env->psw.mask >> 40) & 0xf);
+ env->regs[r1] = r;
+ HELPER_LOG("%s: cc %d psw.mask 0x%lx r1 0x%lx\n", __func__,
+ cc, env->psw.mask, r);
+}
+
+#ifndef CONFIG_USER_ONLY
+void HELPER(load_psw)(uint64_t mask, uint64_t addr)
+{
+ load_psw(env, mask, addr);
+ cpu_loop_exit(env);
+}
+
+void HELPER(sacf)(uint64_t a1)
+{
+ HELPER_LOG("%s: %16" PRIx64 "\n", __func__, a1);
+
+ switch (a1 & 0xf00) {
+ case 0x000:
+ env->psw.mask &= ~PSW_MASK_ASC;
+ env->psw.mask |= PSW_ASC_PRIMARY;
+ break;
+ case 0x100:
+ env->psw.mask &= ~PSW_MASK_ASC;
+ env->psw.mask |= PSW_ASC_SECONDARY;
+ break;
+ case 0x300:
+ env->psw.mask &= ~PSW_MASK_ASC;
+ env->psw.mask |= PSW_ASC_HOME;
+ break;
+ default:
+ qemu_log("unknown sacf mode: %" PRIx64 "\n", a1);
+ program_interrupt(env, PGM_SPECIFICATION, 2);
+ break;
+ }
+}
+#endif
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index b4620c5..97fde5e 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -1005,4 +1005,7 @@ uint32_t set_cc_f64(float64 v1, float64 v2);
uint32_t set_cc_nz_f32(float32 v);
uint32_t set_cc_nz_f64(float64 v);
+/* op_helper.c */
+void program_interrupt(CPUS390XState *env, uint32_t code, int ilc);
+
#endif
diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
index 270bf14..eced890 100644
--- a/target-s390x/op_helper.c
+++ b/target-s390x/op_helper.c
@@ -779,18 +779,6 @@ uint32_t HELPER(icmh)(uint32_t r1, uint64_t address, uint32_t mask)
return cc;
}
-/* insert psw mask and condition code into r1 */
-void HELPER(ipm)(uint32_t cc, uint32_t r1)
-{
- uint64_t r = env->regs[r1];
-
- r &= 0xffffffff00ffffffULL;
- r |= (cc << 28) | ((env->psw.mask >> 40) & 0xf);
- env->regs[r1] = r;
- HELPER_LOG("%s: cc %d psw.mask 0x%lx r1 0x%lx\n", __func__,
- cc, env->psw.mask, r);
-}
-
/* load access registers r1 to r3 from memory at a2 */
void HELPER(lam)(uint32_t r1, uint64_t a2, uint32_t r3)
{
@@ -1038,483 +1026,6 @@ void HELPER(cksm)(uint32_t r1, uint32_t r2)
((uint32_t)cksm + (cksm >> 32));
}
-static inline uint32_t cc_calc_ltgt_32(CPUS390XState *env, int32_t src,
- int32_t dst)
-{
- if (src == dst) {
- return 0;
- } else if (src < dst) {
- return 1;
- } else {
- return 2;
- }
-}
-
-static inline uint32_t cc_calc_ltgt0_32(CPUS390XState *env, int32_t dst)
-{
- return cc_calc_ltgt_32(env, dst, 0);
-}
-
-static inline uint32_t cc_calc_ltgt_64(CPUS390XState *env, int64_t src,
- int64_t dst)
-{
- if (src == dst) {
- return 0;
- } else if (src < dst) {
- return 1;
- } else {
- return 2;
- }
-}
-
-static inline uint32_t cc_calc_ltgt0_64(CPUS390XState *env, int64_t dst)
-{
- return cc_calc_ltgt_64(env, dst, 0);
-}
-
-static inline uint32_t cc_calc_ltugtu_32(CPUS390XState *env, uint32_t src,
- uint32_t dst)
-{
- if (src == dst) {
- return 0;
- } else if (src < dst) {
- return 1;
- } else {
- return 2;
- }
-}
-
-static inline uint32_t cc_calc_ltugtu_64(CPUS390XState *env, uint64_t src,
- uint64_t dst)
-{
- if (src == dst) {
- return 0;
- } else if (src < dst) {
- return 1;
- } else {
- return 2;
- }
-}
-
-static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val,
- uint32_t mask)
-{
- uint16_t r = val & mask;
-
- HELPER_LOG("%s: val 0x%x mask 0x%x\n", __func__, val, mask);
- if (r == 0 || mask == 0) {
- return 0;
- } else if (r == mask) {
- return 3;
- } else {
- return 1;
- }
-}
-
-/* set condition code for test under mask */
-static inline uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val,
- uint32_t mask)
-{
- uint16_t r = val & mask;
-
- HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __func__, val, mask, r);
- if (r == 0 || mask == 0) {
- return 0;
- } else if (r == mask) {
- return 3;
- } else {
- while (!(mask & 0x8000)) {
- mask <<= 1;
- val <<= 1;
- }
- if (val & 0x8000) {
- return 2;
- } else {
- return 1;
- }
- }
-}
-
-static inline uint32_t cc_calc_nz(CPUS390XState *env, uint64_t dst)
-{
- return !!dst;
-}
-
-static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1,
- int64_t a2, int64_t ar)
-{
- if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
- return 3; /* overflow */
- } else {
- if (ar < 0) {
- return 1;
- } else if (ar > 0) {
- return 2;
- } else {
- return 0;
- }
- }
-}
-
-static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1,
- uint64_t a2, uint64_t ar)
-{
- if (ar == 0) {
- if (a1) {
- return 2;
- } else {
- return 0;
- }
- } else {
- if (ar < a1 || ar < a2) {
- return 3;
- } else {
- return 1;
- }
- }
-}
-
-static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1,
- int64_t a2, int64_t ar)
-{
- if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
- return 3; /* overflow */
- } else {
- if (ar < 0) {
- return 1;
- } else if (ar > 0) {
- return 2;
- } else {
- return 0;
- }
- }
-}
-
-static inline uint32_t cc_calc_subu_64(CPUS390XState *env, uint64_t a1,
- uint64_t a2, uint64_t ar)
-{
- if (ar == 0) {
- return 2;
- } else {
- if (a2 > a1) {
- return 1;
- } else {
- return 3;
- }
- }
-}
-
-static inline uint32_t cc_calc_abs_64(CPUS390XState *env, int64_t dst)
-{
- if ((uint64_t)dst == 0x8000000000000000ULL) {
- return 3;
- } else if (dst) {
- return 1;
- } else {
- return 0;
- }
-}
-
-static inline uint32_t cc_calc_nabs_64(CPUS390XState *env, int64_t dst)
-{
- return !!dst;
-}
-
-static inline uint32_t cc_calc_comp_64(CPUS390XState *env, int64_t dst)
-{
- if ((uint64_t)dst == 0x8000000000000000ULL) {
- return 3;
- } else if (dst < 0) {
- return 1;
- } else if (dst > 0) {
- return 2;
- } else {
- return 0;
- }
-}
-
-
-static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1,
- int32_t a2, int32_t ar)
-{
- if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
- return 3; /* overflow */
- } else {
- if (ar < 0) {
- return 1;
- } else if (ar > 0) {
- return 2;
- } else {
- return 0;
- }
- }
-}
-
-static inline uint32_t cc_calc_addu_32(CPUS390XState *env, uint32_t a1,
- uint32_t a2, uint32_t ar)
-{
- if (ar == 0) {
- if (a1) {
- return 2;
- } else {
- return 0;
- }
- } else {
- if (ar < a1 || ar < a2) {
- return 3;
- } else {
- return 1;
- }
- }
-}
-
-static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1,
- int32_t a2, int32_t ar)
-{
- if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
- return 3; /* overflow */
- } else {
- if (ar < 0) {
- return 1;
- } else if (ar > 0) {
- return 2;
- } else {
- return 0;
- }
- }
-}
-
-static inline uint32_t cc_calc_subu_32(CPUS390XState *env, uint32_t a1,
- uint32_t a2, uint32_t ar)
-{
- if (ar == 0) {
- return 2;
- } else {
- if (a2 > a1) {
- return 1;
- } else {
- return 3;
- }
- }
-}
-
-static inline uint32_t cc_calc_abs_32(CPUS390XState *env, int32_t dst)
-{
- if ((uint32_t)dst == 0x80000000UL) {
- return 3;
- } else if (dst) {
- return 1;
- } else {
- return 0;
- }
-}
-
-static inline uint32_t cc_calc_nabs_32(CPUS390XState *env, int32_t dst)
-{
- return !!dst;
-}
-
-static inline uint32_t cc_calc_comp_32(CPUS390XState *env, int32_t dst)
-{
- if ((uint32_t)dst == 0x80000000UL) {
- return 3;
- } else if (dst < 0) {
- return 1;
- } else if (dst > 0) {
- return 2;
- } else {
- return 0;
- }
-}
-
-/* calculate condition code for insert character under mask insn */
-static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask,
- uint32_t val)
-{
- uint32_t cc;
-
- HELPER_LOG("%s: mask 0x%x val %d\n", __func__, mask, val);
- if (mask == 0xf) {
- if (!val) {
- return 0;
- } else if (val & 0x80000000) {
- return 1;
- } else {
- return 2;
- }
- }
-
- if (!val || !mask) {
- cc = 0;
- } else {
- while (mask != 1) {
- mask >>= 1;
- val >>= 8;
- }
- if (val & 0x80) {
- cc = 1;
- } else {
- cc = 2;
- }
- }
- return cc;
-}
-
-static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src,
- uint64_t shift)
-{
- uint64_t mask = ((1ULL << shift) - 1ULL) << (64 - shift);
- uint64_t match, r;
-
- /* check if the sign bit stays the same */
- if (src & (1ULL << 63)) {
- match = mask;
- } else {
- match = 0;
- }
-
- if ((src & mask) != match) {
- /* overflow */
- return 3;
- }
-
- r = ((src << shift) & ((1ULL << 63) - 1)) | (src & (1ULL << 63));
-
- if ((int64_t)r == 0) {
- return 0;
- } else if ((int64_t)r < 0) {
- return 1;
- }
-
- return 2;
-}
-
-
-static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
- uint64_t src, uint64_t dst, uint64_t vr)
-{
- uint32_t r = 0;
-
- switch (cc_op) {
- case CC_OP_CONST0:
- case CC_OP_CONST1:
- case CC_OP_CONST2:
- case CC_OP_CONST3:
- /* cc_op value _is_ cc */
- r = cc_op;
- break;
- case CC_OP_LTGT0_32:
- r = cc_calc_ltgt0_32(env, dst);
- break;
- case CC_OP_LTGT0_64:
- r = cc_calc_ltgt0_64(env, dst);
- break;
- case CC_OP_LTGT_32:
- r = cc_calc_ltgt_32(env, src, dst);
- break;
- case CC_OP_LTGT_64:
- r = cc_calc_ltgt_64(env, src, dst);
- break;
- case CC_OP_LTUGTU_32:
- r = cc_calc_ltugtu_32(env, src, dst);
- break;
- case CC_OP_LTUGTU_64:
- r = cc_calc_ltugtu_64(env, src, dst);
- break;
- case CC_OP_TM_32:
- r = cc_calc_tm_32(env, src, dst);
- break;
- case CC_OP_TM_64:
- r = cc_calc_tm_64(env, src, dst);
- break;
- case CC_OP_NZ:
- r = cc_calc_nz(env, dst);
- break;
- case CC_OP_ADD_64:
- r = cc_calc_add_64(env, src, dst, vr);
- break;
- case CC_OP_ADDU_64:
- r = cc_calc_addu_64(env, src, dst, vr);
- break;
- case CC_OP_SUB_64:
- r = cc_calc_sub_64(env, src, dst, vr);
- break;
- case CC_OP_SUBU_64:
- r = cc_calc_subu_64(env, src, dst, vr);
- break;
- case CC_OP_ABS_64:
- r = cc_calc_abs_64(env, dst);
- break;
- case CC_OP_NABS_64:
- r = cc_calc_nabs_64(env, dst);
- break;
- case CC_OP_COMP_64:
- r = cc_calc_comp_64(env, dst);
- break;
-
- case CC_OP_ADD_32:
- r = cc_calc_add_32(env, src, dst, vr);
- break;
- case CC_OP_ADDU_32:
- r = cc_calc_addu_32(env, src, dst, vr);
- break;
- case CC_OP_SUB_32:
- r = cc_calc_sub_32(env, src, dst, vr);
- break;
- case CC_OP_SUBU_32:
- r = cc_calc_subu_32(env, src, dst, vr);
- break;
- case CC_OP_ABS_32:
- r = cc_calc_abs_64(env, dst);
- break;
- case CC_OP_NABS_32:
- r = cc_calc_nabs_64(env, dst);
- break;
- case CC_OP_COMP_32:
- r = cc_calc_comp_32(env, dst);
- break;
-
- case CC_OP_ICM:
- r = cc_calc_icm_32(env, src, dst);
- break;
- case CC_OP_SLAG:
- r = cc_calc_slag(env, src, dst);
- break;
-
- case CC_OP_LTGT_F32:
- r = set_cc_f32(src, dst);
- break;
- case CC_OP_LTGT_F64:
- r = set_cc_f64(src, dst);
- break;
- case CC_OP_NZ_F32:
- r = set_cc_nz_f32(dst);
- break;
- case CC_OP_NZ_F64:
- r = set_cc_nz_f64(dst);
- break;
-
- default:
- cpu_abort(env, "Unknown CC operation: %s\n", cc_name(cc_op));
- }
-
- HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__,
- cc_name(cc_op), src, dst, vr, r);
- return r;
-}
-
-uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
- uint64_t vr)
-{
- return do_calc_cc(env, cc_op, src, dst, vr);
-}
-
-uint32_t HELPER(calc_cc)(uint32_t cc_op, uint64_t src, uint64_t dst,
- uint64_t vr)
-{
- return do_calc_cc(env, cc_op, src, dst, vr);
-}
-
uint64_t HELPER(cvd)(int32_t bin)
{
/* positive 0 */
@@ -1594,14 +1105,7 @@ void HELPER(tr)(uint32_t len, uint64_t array, uint64_t trans)
}
#ifndef CONFIG_USER_ONLY
-
-void HELPER(load_psw)(uint64_t mask, uint64_t addr)
-{
- load_psw(env, mask, addr);
- cpu_loop_exit(env);
-}
-
-static void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
+void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
{
qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
@@ -2175,30 +1679,6 @@ uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
return cc;
}
-void HELPER(sacf)(uint64_t a1)
-{
- HELPER_LOG("%s: %16" PRIx64 "\n", __func__, a1);
-
- switch (a1 & 0xf00) {
- case 0x000:
- env->psw.mask &= ~PSW_MASK_ASC;
- env->psw.mask |= PSW_ASC_PRIMARY;
- break;
- case 0x100:
- env->psw.mask &= ~PSW_MASK_ASC;
- env->psw.mask |= PSW_ASC_SECONDARY;
- break;
- case 0x300:
- env->psw.mask &= ~PSW_MASK_ASC;
- env->psw.mask |= PSW_ASC_HOME;
- break;
- default:
- qemu_log("unknown sacf mode: %" PRIx64 "\n", a1);
- program_interrupt(env, PGM_SPECIFICATION, 2);
- break;
- }
-}
-
/* invalidate pte */
void HELPER(ipte)(uint64_t pte_addr, uint64_t vaddr)
{
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 04/21] target-s390x: split integer helpers
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (2 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 03/21] target-s390x: split condition code helpers Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 05/21] target-s390x: split memory access helpers Blue Swirl
` (17 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Move integer helpers to int_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
target-s390x/Makefile.objs | 3 +-
target-s390x/int_helper.c | 201 ++++++++++++++++++++++++++++++++++++++++++++
target-s390x/op_helper.c | 170 -------------------------------------
3 files changed, 203 insertions(+), 171 deletions(-)
create mode 100644 target-s390x/int_helper.c
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index f9437d6..e8f66e9 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -1,8 +1,9 @@
obj-y += translate.o op_helper.o helper.o cpu.o interrupt.o
-obj-y += fpu_helper.o cc_helper.o
+obj-y += int_helper.o fpu_helper.o cc_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o
$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
+$(obj)/int_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/fpu_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/cc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-s390x/int_helper.c b/target-s390x/int_helper.c
new file mode 100644
index 0000000..e2eeb07
--- /dev/null
+++ b/target-s390x/int_helper.c
@@ -0,0 +1,201 @@
+/*
+ * S/390 integer helper routines
+ *
+ * Copyright (c) 2009 Ulrich Hecht
+ * Copyright (c) 2009 Alexander Graf
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "dyngen-exec.h"
+#include "host-utils.h"
+#include "helper.h"
+
+/* #define DEBUG_HELPER */
+#ifdef DEBUG_HELPER
+#define HELPER_LOG(x...) qemu_log(x)
+#else
+#define HELPER_LOG(x...)
+#endif
+
+/* 64/64 -> 128 unsigned multiplication */
+void HELPER(mlg)(uint32_t r1, uint64_t v2)
+{
+#if HOST_LONG_BITS == 64 && defined(__GNUC__)
+ /* assuming 64-bit hosts have __uint128_t */
+ __uint128_t res = (__uint128_t)env->regs[r1 + 1];
+
+ res *= (__uint128_t)v2;
+ env->regs[r1] = (uint64_t)(res >> 64);
+ env->regs[r1 + 1] = (uint64_t)res;
+#else
+ mulu64(&env->regs[r1 + 1], &env->regs[r1], env->regs[r1 + 1], v2);
+#endif
+}
+
+/* 128 -> 64/64 unsigned division */
+void HELPER(dlg)(uint32_t r1, uint64_t v2)
+{
+ uint64_t divisor = v2;
+
+ if (!env->regs[r1]) {
+ /* 64 -> 64/64 case */
+ env->regs[r1] = env->regs[r1 + 1] % divisor;
+ env->regs[r1 + 1] = env->regs[r1 + 1] / divisor;
+ return;
+ } else {
+#if HOST_LONG_BITS == 64 && defined(__GNUC__)
+ /* assuming 64-bit hosts have __uint128_t */
+ __uint128_t dividend = (((__uint128_t)env->regs[r1]) << 64) |
+ (env->regs[r1 + 1]);
+ __uint128_t quotient = dividend / divisor;
+ __uint128_t remainder = dividend % divisor;
+
+ env->regs[r1 + 1] = quotient;
+ env->regs[r1] = remainder;
+#else
+ /* 32-bit hosts would need special wrapper functionality - just abort if
+ we encounter such a case; it's very unlikely anyways. */
+ cpu_abort(env, "128 -> 64/64 division not implemented\n");
+#endif
+ }
+}
+
+/* absolute value 32-bit */
+uint32_t HELPER(abs_i32)(int32_t val)
+{
+ if (val < 0) {
+ return -val;
+ } else {
+ return val;
+ }
+}
+
+/* negative absolute value 32-bit */
+int32_t HELPER(nabs_i32)(int32_t val)
+{
+ if (val < 0) {
+ return val;
+ } else {
+ return -val;
+ }
+}
+
+/* absolute value 64-bit */
+uint64_t HELPER(abs_i64)(int64_t val)
+{
+ HELPER_LOG("%s: val 0x%" PRIx64 "\n", __func__, val);
+
+ if (val < 0) {
+ return -val;
+ } else {
+ return val;
+ }
+}
+
+/* negative absolute value 64-bit */
+int64_t HELPER(nabs_i64)(int64_t val)
+{
+ if (val < 0) {
+ return val;
+ } else {
+ return -val;
+ }
+}
+
+/* add with carry 32-bit unsigned */
+uint32_t HELPER(addc_u32)(uint32_t cc, uint32_t v1, uint32_t v2)
+{
+ uint32_t res;
+
+ res = v1 + v2;
+ if (cc & 2) {
+ res++;
+ }
+
+ return res;
+}
+
+/* subtract unsigned v2 from v1 with borrow */
+uint32_t HELPER(slb)(uint32_t cc, uint32_t r1, uint32_t v2)
+{
+ uint32_t v1 = env->regs[r1];
+ uint32_t res = v1 + (~v2) + (cc >> 1);
+
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | res;
+ if (cc & 2) {
+ /* borrow */
+ return v1 ? 1 : 0;
+ } else {
+ return v1 ? 3 : 2;
+ }
+}
+
+/* subtract unsigned v2 from v1 with borrow */
+uint32_t HELPER(slbg)(uint32_t cc, uint32_t r1, uint64_t v1, uint64_t v2)
+{
+ uint64_t res = v1 + (~v2) + (cc >> 1);
+
+ env->regs[r1] = res;
+ if (cc & 2) {
+ /* borrow */
+ return v1 ? 1 : 0;
+ } else {
+ return v1 ? 3 : 2;
+ }
+}
+
+/* find leftmost one */
+uint32_t HELPER(flogr)(uint32_t r1, uint64_t v2)
+{
+ uint64_t res = 0;
+ uint64_t ov2 = v2;
+
+ while (!(v2 & 0x8000000000000000ULL) && v2) {
+ v2 <<= 1;
+ res++;
+ }
+
+ if (!v2) {
+ env->regs[r1] = 64;
+ env->regs[r1 + 1] = 0;
+ return 0;
+ } else {
+ env->regs[r1] = res;
+ env->regs[r1 + 1] = ov2 & ~(0x8000000000000000ULL >> res);
+ return 2;
+ }
+}
+
+uint64_t HELPER(cvd)(int32_t bin)
+{
+ /* positive 0 */
+ uint64_t dec = 0x0c;
+ int shift = 4;
+
+ if (bin < 0) {
+ bin = -bin;
+ dec = 0x0d;
+ }
+
+ for (shift = 4; (shift < 64) && bin; shift += 4) {
+ int current_number = bin % 10;
+
+ dec |= (current_number) << shift;
+ bin /= 10;
+ }
+
+ return dec;
+}
diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
index eced890..3b8b997 100644
--- a/target-s390x/op_helper.c
+++ b/target-s390x/op_helper.c
@@ -352,49 +352,6 @@ void HELPER(stcm)(uint32_t r1, uint32_t mask, uint64_t addr)
HELPER_LOG("\n");
}
-/* 64/64 -> 128 unsigned multiplication */
-void HELPER(mlg)(uint32_t r1, uint64_t v2)
-{
-#if HOST_LONG_BITS == 64 && defined(__GNUC__)
- /* assuming 64-bit hosts have __uint128_t */
- __uint128_t res = (__uint128_t)env->regs[r1 + 1];
-
- res *= (__uint128_t)v2;
- env->regs[r1] = (uint64_t)(res >> 64);
- env->regs[r1 + 1] = (uint64_t)res;
-#else
- mulu64(&env->regs[r1 + 1], &env->regs[r1], env->regs[r1 + 1], v2);
-#endif
-}
-
-/* 128 -> 64/64 unsigned division */
-void HELPER(dlg)(uint32_t r1, uint64_t v2)
-{
- uint64_t divisor = v2;
-
- if (!env->regs[r1]) {
- /* 64 -> 64/64 case */
- env->regs[r1] = env->regs[r1 + 1] % divisor;
- env->regs[r1 + 1] = env->regs[r1 + 1] / divisor;
- return;
- } else {
-#if HOST_LONG_BITS == 64 && defined(__GNUC__)
- /* assuming 64-bit hosts have __uint128_t */
- __uint128_t dividend = (((__uint128_t)env->regs[r1]) << 64) |
- (env->regs[r1 + 1]);
- __uint128_t quotient = dividend / divisor;
- __uint128_t remainder = dividend % divisor;
-
- env->regs[r1 + 1] = quotient;
- env->regs[r1] = remainder;
-#else
- /* 32-bit hosts would need special wrapper functionality - just abort if
- we encounter such a case; it's very unlikely anyways. */
- cpu_abort(env, "128 -> 64/64 division not implemented\n");
-#endif
- }
-}
-
static inline uint64_t get_address(int x2, int b2, int d2)
{
uint64_t r = d2;
@@ -677,61 +634,6 @@ uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
return cc;
}
-/* absolute value 32-bit */
-uint32_t HELPER(abs_i32)(int32_t val)
-{
- if (val < 0) {
- return -val;
- } else {
- return val;
- }
-}
-
-/* negative absolute value 32-bit */
-int32_t HELPER(nabs_i32)(int32_t val)
-{
- if (val < 0) {
- return val;
- } else {
- return -val;
- }
-}
-
-/* absolute value 64-bit */
-uint64_t HELPER(abs_i64)(int64_t val)
-{
- HELPER_LOG("%s: val 0x%" PRIx64 "\n", __func__, val);
-
- if (val < 0) {
- return -val;
- } else {
- return val;
- }
-}
-
-/* negative absolute value 64-bit */
-int64_t HELPER(nabs_i64)(int64_t val)
-{
- if (val < 0) {
- return val;
- } else {
- return -val;
- }
-}
-
-/* add with carry 32-bit unsigned */
-uint32_t HELPER(addc_u32)(uint32_t cc, uint32_t v1, uint32_t v2)
-{
- uint32_t res;
-
- res = v1 + v2;
- if (cc & 2) {
- res++;
- }
-
- return res;
-}
-
/* store character under mask high operates on the upper half of r1 */
void HELPER(stcmh)(uint32_t r1, uint64_t address, uint32_t mask)
{
@@ -936,57 +838,6 @@ uint32_t HELPER(clcle)(uint32_t r1, uint64_t a2, uint32_t r3)
return cc;
}
-/* subtract unsigned v2 from v1 with borrow */
-uint32_t HELPER(slb)(uint32_t cc, uint32_t r1, uint32_t v2)
-{
- uint32_t v1 = env->regs[r1];
- uint32_t res = v1 + (~v2) + (cc >> 1);
-
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | res;
- if (cc & 2) {
- /* borrow */
- return v1 ? 1 : 0;
- } else {
- return v1 ? 3 : 2;
- }
-}
-
-/* subtract unsigned v2 from v1 with borrow */
-uint32_t HELPER(slbg)(uint32_t cc, uint32_t r1, uint64_t v1, uint64_t v2)
-{
- uint64_t res = v1 + (~v2) + (cc >> 1);
-
- env->regs[r1] = res;
- if (cc & 2) {
- /* borrow */
- return v1 ? 1 : 0;
- } else {
- return v1 ? 3 : 2;
- }
-}
-
-/* find leftmost one */
-uint32_t HELPER(flogr)(uint32_t r1, uint64_t v2)
-{
- uint64_t res = 0;
- uint64_t ov2 = v2;
-
- while (!(v2 & 0x8000000000000000ULL) && v2) {
- v2 <<= 1;
- res++;
- }
-
- if (!v2) {
- env->regs[r1] = 64;
- env->regs[r1 + 1] = 0;
- return 0;
- } else {
- env->regs[r1] = res;
- env->regs[r1 + 1] = ov2 & ~(0x8000000000000000ULL >> res);
- return 2;
- }
-}
-
/* checksum */
void HELPER(cksm)(uint32_t r1, uint32_t r2)
{
@@ -1026,27 +877,6 @@ void HELPER(cksm)(uint32_t r1, uint32_t r2)
((uint32_t)cksm + (cksm >> 32));
}
-uint64_t HELPER(cvd)(int32_t bin)
-{
- /* positive 0 */
- uint64_t dec = 0x0c;
- int shift = 4;
-
- if (bin < 0) {
- bin = -bin;
- dec = 0x0d;
- }
-
- for (shift = 4; (shift < 64) && bin; shift += 4) {
- int current_number = bin % 10;
-
- dec |= (current_number) << shift;
- bin /= 10;
- }
-
- return dec;
-}
-
void HELPER(unpk)(uint32_t len, uint64_t dest, uint64_t src)
{
int len_dest = len >> 4;
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 05/21] target-s390x: split memory access helpers
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (3 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 04/21] target-s390x: split integer helpers Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-06 18:14 ` Alexander Graf
2012-09-02 17:33 ` [Qemu-devel] [PATCH 06/21] target-s390x: rename op_helper.c to misc_helper.c Blue Swirl
` (16 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Move memory access helpers to mem_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
target-s390x/Makefile.objs | 3 +-
target-s390x/mem_helper.c | 1190 ++++++++++++++++++++++++++++++++++++++++++++
target-s390x/op_helper.c | 1158 +------------------------------------------
3 files changed, 1194 insertions(+), 1157 deletions(-)
create mode 100644 target-s390x/mem_helper.c
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index e8f66e9..b9b3061 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -1,5 +1,5 @@
obj-y += translate.o op_helper.o helper.o cpu.o interrupt.o
-obj-y += int_helper.o fpu_helper.o cc_helper.o
+obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o
@@ -7,3 +7,4 @@ $(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/int_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/fpu_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/cc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
+$(obj)/mem_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
new file mode 100644
index 0000000..ba05e65
--- /dev/null
+++ b/target-s390x/mem_helper.c
@@ -0,0 +1,1190 @@
+/*
+ * S/390 memory access helper routines
+ *
+ * Copyright (c) 2009 Ulrich Hecht
+ * Copyright (c) 2009 Alexander Graf
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "dyngen-exec.h"
+#include "helper.h"
+
+/*****************************************************************************/
+/* Softmmu support */
+#if !defined(CONFIG_USER_ONLY)
+#include "softmmu_exec.h"
+
+#define MMUSUFFIX _mmu
+
+#define SHIFT 0
+#include "softmmu_template.h"
+
+#define SHIFT 1
+#include "softmmu_template.h"
+
+#define SHIFT 2
+#include "softmmu_template.h"
+
+#define SHIFT 3
+#include "softmmu_template.h"
+
+/* try to fill the TLB and return an exception if error. If retaddr is
+ NULL, it means that the function was called in C code (i.e. not
+ from generated code or from helper.c) */
+/* XXX: fix it to restore all registers */
+void tlb_fill(CPUS390XState *env1, target_ulong addr, int is_write, int mmu_idx,
+ uintptr_t retaddr)
+{
+ TranslationBlock *tb;
+ CPUS390XState *saved_env;
+ int ret;
+
+ saved_env = env;
+ env = env1;
+ ret = cpu_s390x_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ if (unlikely(ret != 0)) {
+ if (likely(retaddr)) {
+ /* now we have a real cpu fault */
+ tb = tb_find_pc(retaddr);
+ if (likely(tb)) {
+ /* the PC is inside the translated code. It means that we have
+ a virtual CPU fault */
+ cpu_restore_state(tb, env, retaddr);
+ }
+ }
+ cpu_loop_exit(env);
+ }
+ env = saved_env;
+}
+
+#endif
+
+/* #define DEBUG_HELPER */
+#ifdef DEBUG_HELPER
+#define HELPER_LOG(x...) qemu_log(x)
+#else
+#define HELPER_LOG(x...)
+#endif
+
+#ifndef CONFIG_USER_ONLY
+static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
+ uint8_t byte)
+{
+ target_phys_addr_t dest_phys;
+ target_phys_addr_t len = l;
+ void *dest_p;
+ uint64_t asc = env->psw.mask & PSW_MASK_ASC;
+ int flags;
+
+ if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
+ stb(dest, byte);
+ cpu_abort(env, "should never reach here");
+ }
+ dest_phys |= dest & ~TARGET_PAGE_MASK;
+
+ dest_p = cpu_physical_memory_map(dest_phys, &len, 1);
+
+ memset(dest_p, byte, len);
+
+ cpu_physical_memory_unmap(dest_p, 1, len, len);
+}
+
+static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
+ uint64_t src)
+{
+ target_phys_addr_t dest_phys;
+ target_phys_addr_t src_phys;
+ target_phys_addr_t len = l;
+ void *dest_p;
+ void *src_p;
+ uint64_t asc = env->psw.mask & PSW_MASK_ASC;
+ int flags;
+
+ if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
+ stb(dest, 0);
+ cpu_abort(env, "should never reach here");
+ }
+ dest_phys |= dest & ~TARGET_PAGE_MASK;
+
+ if (mmu_translate(env, src, 0, asc, &src_phys, &flags)) {
+ ldub(src);
+ cpu_abort(env, "should never reach here");
+ }
+ src_phys |= src & ~TARGET_PAGE_MASK;
+
+ dest_p = cpu_physical_memory_map(dest_phys, &len, 1);
+ src_p = cpu_physical_memory_map(src_phys, &len, 0);
+
+ memmove(dest_p, src_p, len);
+
+ cpu_physical_memory_unmap(dest_p, 1, len, len);
+ cpu_physical_memory_unmap(src_p, 0, len, len);
+}
+#endif
+
+/* and on array */
+uint32_t HELPER(nc)(uint32_t l, uint64_t dest, uint64_t src)
+{
+ int i;
+ unsigned char x;
+ uint32_t cc = 0;
+
+ HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
+ __func__, l, dest, src);
+ for (i = 0; i <= l; i++) {
+ x = ldub(dest + i) & ldub(src + i);
+ if (x) {
+ cc = 1;
+ }
+ stb(dest + i, x);
+ }
+ return cc;
+}
+
+/* xor on array */
+uint32_t HELPER(xc)(uint32_t l, uint64_t dest, uint64_t src)
+{
+ int i;
+ unsigned char x;
+ uint32_t cc = 0;
+
+ HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
+ __func__, l, dest, src);
+
+#ifndef CONFIG_USER_ONLY
+ /* xor with itself is the same as memset(0) */
+ if ((l > 32) && (src == dest) &&
+ (src & TARGET_PAGE_MASK) == ((src + l) & TARGET_PAGE_MASK)) {
+ mvc_fast_memset(env, l + 1, dest, 0);
+ return 0;
+ }
+#else
+ if (src == dest) {
+ memset(g2h(dest), 0, l + 1);
+ return 0;
+ }
+#endif
+
+ for (i = 0; i <= l; i++) {
+ x = ldub(dest + i) ^ ldub(src + i);
+ if (x) {
+ cc = 1;
+ }
+ stb(dest + i, x);
+ }
+ return cc;
+}
+
+/* or on array */
+uint32_t HELPER(oc)(uint32_t l, uint64_t dest, uint64_t src)
+{
+ int i;
+ unsigned char x;
+ uint32_t cc = 0;
+
+ HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
+ __func__, l, dest, src);
+ for (i = 0; i <= l; i++) {
+ x = ldub(dest + i) | ldub(src + i);
+ if (x) {
+ cc = 1;
+ }
+ stb(dest + i, x);
+ }
+ return cc;
+}
+
+/* memmove */
+void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
+{
+ int i = 0;
+ int x = 0;
+ uint32_t l_64 = (l + 1) / 8;
+
+ HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
+ __func__, l, dest, src);
+
+#ifndef CONFIG_USER_ONLY
+ if ((l > 32) &&
+ (src & TARGET_PAGE_MASK) == ((src + l) & TARGET_PAGE_MASK) &&
+ (dest & TARGET_PAGE_MASK) == ((dest + l) & TARGET_PAGE_MASK)) {
+ if (dest == (src + 1)) {
+ mvc_fast_memset(env, l + 1, dest, ldub(src));
+ return;
+ } else if ((src & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
+ mvc_fast_memmove(env, l + 1, dest, src);
+ return;
+ }
+ }
+#else
+ if (dest == (src + 1)) {
+ memset(g2h(dest), ldub(src), l + 1);
+ return;
+ } else {
+ memmove(g2h(dest), g2h(src), l + 1);
+ return;
+ }
+#endif
+
+ /* handle the parts that fit into 8-byte loads/stores */
+ if (dest != (src + 1)) {
+ for (i = 0; i < l_64; i++) {
+ stq(dest + x, ldq(src + x));
+ x += 8;
+ }
+ }
+
+ /* slow version crossing pages with byte accesses */
+ for (i = x; i <= l; i++) {
+ stb(dest + i, ldub(src + i));
+ }
+}
+
+/* compare unsigned byte arrays */
+uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
+{
+ int i;
+ unsigned char x, y;
+ uint32_t cc;
+
+ HELPER_LOG("%s l %d s1 %" PRIx64 " s2 %" PRIx64 "\n",
+ __func__, l, s1, s2);
+ for (i = 0; i <= l; i++) {
+ x = ldub(s1 + i);
+ y = ldub(s2 + i);
+ HELPER_LOG("%02x (%c)/%02x (%c) ", x, x, y, y);
+ if (x < y) {
+ cc = 1;
+ goto done;
+ } else if (x > y) {
+ cc = 2;
+ goto done;
+ }
+ }
+ cc = 0;
+ done:
+ HELPER_LOG("\n");
+ return cc;
+}
+
+/* compare logical under mask */
+uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
+{
+ uint8_t r, d;
+ uint32_t cc;
+
+ HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%" PRIx64 "\n", __func__, r1,
+ mask, addr);
+ cc = 0;
+ while (mask) {
+ if (mask & 8) {
+ d = ldub(addr);
+ r = (r1 & 0xff000000UL) >> 24;
+ HELPER_LOG("mask 0x%x %02x/%02x (0x%" PRIx64 ") ", mask, r, d,
+ addr);
+ if (r < d) {
+ cc = 1;
+ break;
+ } else if (r > d) {
+ cc = 2;
+ break;
+ }
+ addr++;
+ }
+ mask = (mask << 1) & 0xf;
+ r1 <<= 8;
+ }
+ HELPER_LOG("\n");
+ return cc;
+}
+
+/* store character under mask */
+void HELPER(stcm)(uint32_t r1, uint32_t mask, uint64_t addr)
+{
+ uint8_t r;
+
+ HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%lx\n", __func__, r1, mask,
+ addr);
+ while (mask) {
+ if (mask & 8) {
+ r = (r1 & 0xff000000UL) >> 24;
+ stb(addr, r);
+ HELPER_LOG("mask 0x%x %02x (0x%lx) ", mask, r, addr);
+ addr++;
+ }
+ mask = (mask << 1) & 0xf;
+ r1 <<= 8;
+ }
+ HELPER_LOG("\n");
+}
+
+static inline uint64_t get_address(int x2, int b2, int d2)
+{
+ uint64_t r = d2;
+
+ if (x2) {
+ r += env->regs[x2];
+ }
+
+ if (b2) {
+ r += env->regs[b2];
+ }
+
+ /* 31-Bit mode */
+ if (!(env->psw.mask & PSW_MASK_64)) {
+ r &= 0x7fffffff;
+ }
+
+ return r;
+}
+
+static inline uint64_t get_address_31fix(int reg)
+{
+ uint64_t r = env->regs[reg];
+
+ /* 31-Bit mode */
+ if (!(env->psw.mask & PSW_MASK_64)) {
+ r &= 0x7fffffff;
+ }
+
+ return r;
+}
+
+/* search string (c is byte to search, r2 is string, r1 end of string) */
+uint32_t HELPER(srst)(uint32_t c, uint32_t r1, uint32_t r2)
+{
+ uint64_t i;
+ uint32_t cc = 2;
+ uint64_t str = get_address_31fix(r2);
+ uint64_t end = get_address_31fix(r1);
+
+ HELPER_LOG("%s: c %d *r1 0x%" PRIx64 " *r2 0x%" PRIx64 "\n", __func__,
+ c, env->regs[r1], env->regs[r2]);
+
+ for (i = str; i != end; i++) {
+ if (ldub(i) == c) {
+ env->regs[r1] = i;
+ cc = 1;
+ break;
+ }
+ }
+
+ return cc;
+}
+
+/* unsigned string compare (c is string terminator) */
+uint32_t HELPER(clst)(uint32_t c, uint32_t r1, uint32_t r2)
+{
+ uint64_t s1 = get_address_31fix(r1);
+ uint64_t s2 = get_address_31fix(r2);
+ uint8_t v1, v2;
+ uint32_t cc;
+
+ c = c & 0xff;
+#ifdef CONFIG_USER_ONLY
+ if (!c) {
+ HELPER_LOG("%s: comparing '%s' and '%s'\n",
+ __func__, (char *)g2h(s1), (char *)g2h(s2));
+ }
+#endif
+ for (;;) {
+ v1 = ldub(s1);
+ v2 = ldub(s2);
+ if ((v1 == c || v2 == c) || (v1 != v2)) {
+ break;
+ }
+ s1++;
+ s2++;
+ }
+
+ if (v1 == v2) {
+ cc = 0;
+ } else {
+ cc = (v1 < v2) ? 1 : 2;
+ /* FIXME: 31-bit mode! */
+ env->regs[r1] = s1;
+ env->regs[r2] = s2;
+ }
+ return cc;
+}
+
+/* move page */
+void HELPER(mvpg)(uint64_t r0, uint64_t r1, uint64_t r2)
+{
+ /* XXX missing r0 handling */
+#ifdef CONFIG_USER_ONLY
+ int i;
+
+ for (i = 0; i < TARGET_PAGE_SIZE; i++) {
+ stb(r1 + i, ldub(r2 + i));
+ }
+#else
+ mvc_fast_memmove(env, TARGET_PAGE_SIZE, r1, r2);
+#endif
+}
+
+/* string copy (c is string terminator) */
+void HELPER(mvst)(uint32_t c, uint32_t r1, uint32_t r2)
+{
+ uint64_t dest = get_address_31fix(r1);
+ uint64_t src = get_address_31fix(r2);
+ uint8_t v;
+
+ c = c & 0xff;
+#ifdef CONFIG_USER_ONLY
+ if (!c) {
+ HELPER_LOG("%s: copy '%s' to 0x%lx\n", __func__, (char *)g2h(src),
+ dest);
+ }
+#endif
+ for (;;) {
+ v = ldub(src);
+ stb(dest, v);
+ if (v == c) {
+ break;
+ }
+ src++;
+ dest++;
+ }
+ env->regs[r1] = dest; /* FIXME: 31-bit mode! */
+}
+
+/* compare and swap 64-bit */
+uint32_t HELPER(csg)(uint32_t r1, uint64_t a2, uint32_t r3)
+{
+ /* FIXME: locking? */
+ uint32_t cc;
+ uint64_t v2 = ldq(a2);
+
+ if (env->regs[r1] == v2) {
+ cc = 0;
+ stq(a2, env->regs[r3]);
+ } else {
+ cc = 1;
+ env->regs[r1] = v2;
+ }
+ return cc;
+}
+
+/* compare double and swap 64-bit */
+uint32_t HELPER(cdsg)(uint32_t r1, uint64_t a2, uint32_t r3)
+{
+ /* FIXME: locking? */
+ uint32_t cc;
+ uint64_t v2_hi = ldq(a2);
+ uint64_t v2_lo = ldq(a2 + 8);
+ uint64_t v1_hi = env->regs[r1];
+ uint64_t v1_lo = env->regs[r1 + 1];
+
+ if ((v1_hi == v2_hi) && (v1_lo == v2_lo)) {
+ cc = 0;
+ stq(a2, env->regs[r3]);
+ stq(a2 + 8, env->regs[r3 + 1]);
+ } else {
+ cc = 1;
+ env->regs[r1] = v2_hi;
+ env->regs[r1 + 1] = v2_lo;
+ }
+
+ return cc;
+}
+
+/* compare and swap 32-bit */
+uint32_t HELPER(cs)(uint32_t r1, uint64_t a2, uint32_t r3)
+{
+ /* FIXME: locking? */
+ uint32_t cc;
+ uint32_t v2 = ldl(a2);
+
+ HELPER_LOG("%s: r1 %d a2 0x%lx r3 %d\n", __func__, r1, a2, r3);
+ if (((uint32_t)env->regs[r1]) == v2) {
+ cc = 0;
+ stl(a2, (uint32_t)env->regs[r3]);
+ } else {
+ cc = 1;
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | v2;
+ }
+ return cc;
+}
+
+static uint32_t helper_icm(uint32_t r1, uint64_t address, uint32_t mask)
+{
+ int pos = 24; /* top of the lower half of r1 */
+ uint64_t rmask = 0xff000000ULL;
+ uint8_t val = 0;
+ int ccd = 0;
+ uint32_t cc = 0;
+
+ while (mask) {
+ if (mask & 8) {
+ env->regs[r1] &= ~rmask;
+ val = ldub(address);
+ if ((val & 0x80) && !ccd) {
+ cc = 1;
+ }
+ ccd = 1;
+ if (val && cc == 0) {
+ cc = 2;
+ }
+ env->regs[r1] |= (uint64_t)val << pos;
+ address++;
+ }
+ mask = (mask << 1) & 0xf;
+ pos -= 8;
+ rmask >>= 8;
+ }
+
+ return cc;
+}
+
+/* execute instruction
+ this instruction executes an insn modified with the contents of r1
+ it does not change the executed instruction in memory
+ it does not change the program counter
+ in other words: tricky...
+ currently implemented by interpreting the cases it is most commonly used in
+*/
+uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
+{
+ uint16_t insn = lduw_code(addr);
+
+ HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr,
+ insn);
+ if ((insn & 0xf0ff) == 0xd000) {
+ uint32_t l, insn2, b1, b2, d1, d2;
+
+ l = v1 & 0xff;
+ insn2 = ldl_code(addr + 2);
+ b1 = (insn2 >> 28) & 0xf;
+ b2 = (insn2 >> 12) & 0xf;
+ d1 = (insn2 >> 16) & 0xfff;
+ d2 = insn2 & 0xfff;
+ switch (insn & 0xf00) {
+ case 0x200:
+ helper_mvc(l, get_address(0, b1, d1), get_address(0, b2, d2));
+ break;
+ case 0x500:
+ cc = helper_clc(l, get_address(0, b1, d1), get_address(0, b2, d2));
+ break;
+ case 0x700:
+ cc = helper_xc(l, get_address(0, b1, d1), get_address(0, b2, d2));
+ break;
+ case 0xc00:
+ helper_tr(l, get_address(0, b1, d1), get_address(0, b2, d2));
+ break;
+ default:
+ goto abort;
+ break;
+ }
+ } else if ((insn & 0xff00) == 0x0a00) {
+ /* supervisor call */
+ HELPER_LOG("%s: svc %ld via execute\n", __func__, (insn | v1) & 0xff);
+ env->psw.addr = ret - 4;
+ env->int_svc_code = (insn | v1) & 0xff;
+ env->int_svc_ilc = 4;
+ helper_exception(EXCP_SVC);
+ } else if ((insn & 0xff00) == 0xbf00) {
+ uint32_t insn2, r1, r3, b2, d2;
+
+ insn2 = ldl_code(addr + 2);
+ r1 = (insn2 >> 20) & 0xf;
+ r3 = (insn2 >> 16) & 0xf;
+ b2 = (insn2 >> 12) & 0xf;
+ d2 = insn2 & 0xfff;
+ cc = helper_icm(r1, get_address(0, b2, d2), r3);
+ } else {
+ abort:
+ cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n",
+ insn);
+ }
+ return cc;
+}
+
+/* store character under mask high operates on the upper half of r1 */
+void HELPER(stcmh)(uint32_t r1, uint64_t address, uint32_t mask)
+{
+ int pos = 56; /* top of the upper half of r1 */
+
+ while (mask) {
+ if (mask & 8) {
+ stb(address, (env->regs[r1] >> pos) & 0xff);
+ address++;
+ }
+ mask = (mask << 1) & 0xf;
+ pos -= 8;
+ }
+}
+
+/* insert character under mask high; same as icm, but operates on the
+ upper half of r1 */
+uint32_t HELPER(icmh)(uint32_t r1, uint64_t address, uint32_t mask)
+{
+ int pos = 56; /* top of the upper half of r1 */
+ uint64_t rmask = 0xff00000000000000ULL;
+ uint8_t val = 0;
+ int ccd = 0;
+ uint32_t cc = 0;
+
+ while (mask) {
+ if (mask & 8) {
+ env->regs[r1] &= ~rmask;
+ val = ldub(address);
+ if ((val & 0x80) && !ccd) {
+ cc = 1;
+ }
+ ccd = 1;
+ if (val && cc == 0) {
+ cc = 2;
+ }
+ env->regs[r1] |= (uint64_t)val << pos;
+ address++;
+ }
+ mask = (mask << 1) & 0xf;
+ pos -= 8;
+ rmask >>= 8;
+ }
+
+ return cc;
+}
+
+/* load access registers r1 to r3 from memory at a2 */
+void HELPER(lam)(uint32_t r1, uint64_t a2, uint32_t r3)
+{
+ int i;
+
+ for (i = r1;; i = (i + 1) % 16) {
+ env->aregs[i] = ldl(a2);
+ a2 += 4;
+
+ if (i == r3) {
+ break;
+ }
+ }
+}
+
+/* store access registers r1 to r3 in memory at a2 */
+void HELPER(stam)(uint32_t r1, uint64_t a2, uint32_t r3)
+{
+ int i;
+
+ for (i = r1;; i = (i + 1) % 16) {
+ stl(a2, env->aregs[i]);
+ a2 += 4;
+
+ if (i == r3) {
+ break;
+ }
+ }
+}
+
+/* move long */
+uint32_t HELPER(mvcl)(uint32_t r1, uint32_t r2)
+{
+ uint64_t destlen = env->regs[r1 + 1] & 0xffffff;
+ uint64_t dest = get_address_31fix(r1);
+ uint64_t srclen = env->regs[r2 + 1] & 0xffffff;
+ uint64_t src = get_address_31fix(r2);
+ uint8_t pad = src >> 24;
+ uint8_t v;
+ uint32_t cc;
+
+ if (destlen == srclen) {
+ cc = 0;
+ } else if (destlen < srclen) {
+ cc = 1;
+ } else {
+ cc = 2;
+ }
+
+ if (srclen > destlen) {
+ srclen = destlen;
+ }
+
+ for (; destlen && srclen; src++, dest++, destlen--, srclen--) {
+ v = ldub(src);
+ stb(dest, v);
+ }
+
+ for (; destlen; dest++, destlen--) {
+ stb(dest, pad);
+ }
+
+ env->regs[r1 + 1] = destlen;
+ /* can't use srclen here, we trunc'ed it */
+ env->regs[r2 + 1] -= src - env->regs[r2];
+ env->regs[r1] = dest;
+ env->regs[r2] = src;
+
+ return cc;
+}
+
+/* move long extended another memcopy insn with more bells and whistles */
+uint32_t HELPER(mvcle)(uint32_t r1, uint64_t a2, uint32_t r3)
+{
+ uint64_t destlen = env->regs[r1 + 1];
+ uint64_t dest = env->regs[r1];
+ uint64_t srclen = env->regs[r3 + 1];
+ uint64_t src = env->regs[r3];
+ uint8_t pad = a2 & 0xff;
+ uint8_t v;
+ uint32_t cc;
+
+ if (!(env->psw.mask & PSW_MASK_64)) {
+ destlen = (uint32_t)destlen;
+ srclen = (uint32_t)srclen;
+ dest &= 0x7fffffff;
+ src &= 0x7fffffff;
+ }
+
+ if (destlen == srclen) {
+ cc = 0;
+ } else if (destlen < srclen) {
+ cc = 1;
+ } else {
+ cc = 2;
+ }
+
+ if (srclen > destlen) {
+ srclen = destlen;
+ }
+
+ for (; destlen && srclen; src++, dest++, destlen--, srclen--) {
+ v = ldub(src);
+ stb(dest, v);
+ }
+
+ for (; destlen; dest++, destlen--) {
+ stb(dest, pad);
+ }
+
+ env->regs[r1 + 1] = destlen;
+ /* can't use srclen here, we trunc'ed it */
+ /* FIXME: 31-bit mode! */
+ env->regs[r3 + 1] -= src - env->regs[r3];
+ env->regs[r1] = dest;
+ env->regs[r3] = src;
+
+ return cc;
+}
+
+/* compare logical long extended memcompare insn with padding */
+uint32_t HELPER(clcle)(uint32_t r1, uint64_t a2, uint32_t r3)
+{
+ uint64_t destlen = env->regs[r1 + 1];
+ uint64_t dest = get_address_31fix(r1);
+ uint64_t srclen = env->regs[r3 + 1];
+ uint64_t src = get_address_31fix(r3);
+ uint8_t pad = a2 & 0xff;
+ uint8_t v1 = 0, v2 = 0;
+ uint32_t cc = 0;
+
+ if (!(destlen || srclen)) {
+ return cc;
+ }
+
+ if (srclen > destlen) {
+ srclen = destlen;
+ }
+
+ for (; destlen || srclen; src++, dest++, destlen--, srclen--) {
+ v1 = srclen ? ldub(src) : pad;
+ v2 = destlen ? ldub(dest) : pad;
+ if (v1 != v2) {
+ cc = (v1 < v2) ? 1 : 2;
+ break;
+ }
+ }
+
+ env->regs[r1 + 1] = destlen;
+ /* can't use srclen here, we trunc'ed it */
+ env->regs[r3 + 1] -= src - env->regs[r3];
+ env->regs[r1] = dest;
+ env->regs[r3] = src;
+
+ return cc;
+}
+
+/* checksum */
+void HELPER(cksm)(uint32_t r1, uint32_t r2)
+{
+ uint64_t src = get_address_31fix(r2);
+ uint64_t src_len = env->regs[(r2 + 1) & 15];
+ uint64_t cksm = (uint32_t)env->regs[r1];
+
+ while (src_len >= 4) {
+ cksm += ldl(src);
+
+ /* move to next word */
+ src_len -= 4;
+ src += 4;
+ }
+
+ switch (src_len) {
+ case 0:
+ break;
+ case 1:
+ cksm += ldub(src) << 24;
+ break;
+ case 2:
+ cksm += lduw(src) << 16;
+ break;
+ case 3:
+ cksm += lduw(src) << 16;
+ cksm += ldub(src + 2) << 8;
+ break;
+ }
+
+ /* indicate we've processed everything */
+ env->regs[r2] = src + src_len;
+ env->regs[(r2 + 1) & 15] = 0;
+
+ /* store result */
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
+ ((uint32_t)cksm + (cksm >> 32));
+}
+
+void HELPER(unpk)(uint32_t len, uint64_t dest, uint64_t src)
+{
+ int len_dest = len >> 4;
+ int len_src = len & 0xf;
+ uint8_t b;
+ int second_nibble = 0;
+
+ dest += len_dest;
+ src += len_src;
+
+ /* last byte is special, it only flips the nibbles */
+ b = ldub(src);
+ stb(dest, (b << 4) | (b >> 4));
+ src--;
+ len_src--;
+
+ /* now pad every nibble with 0xf0 */
+
+ while (len_dest > 0) {
+ uint8_t cur_byte = 0;
+
+ if (len_src > 0) {
+ cur_byte = ldub(src);
+ }
+
+ len_dest--;
+ dest--;
+
+ /* only advance one nibble at a time */
+ if (second_nibble) {
+ cur_byte >>= 4;
+ len_src--;
+ src--;
+ }
+ second_nibble = !second_nibble;
+
+ /* digit */
+ cur_byte = (cur_byte & 0xf);
+ /* zone bits */
+ cur_byte |= 0xf0;
+
+ stb(dest, cur_byte);
+ }
+}
+
+void HELPER(tr)(uint32_t len, uint64_t array, uint64_t trans)
+{
+ int i;
+
+ for (i = 0; i <= len; i++) {
+ uint8_t byte = ldub(array + i);
+ uint8_t new_byte = ldub(trans + byte);
+
+ stb(array + i, new_byte);
+ }
+}
+
+#if !defined(CONFIG_USER_ONLY)
+void HELPER(lctlg)(uint32_t r1, uint64_t a2, uint32_t r3)
+{
+ int i;
+ uint64_t src = a2;
+
+ for (i = r1;; i = (i + 1) % 16) {
+ env->cregs[i] = ldq(src);
+ HELPER_LOG("load ctl %d from 0x%" PRIx64 " == 0x%" PRIx64 "\n",
+ i, src, env->cregs[i]);
+ src += sizeof(uint64_t);
+
+ if (i == r3) {
+ break;
+ }
+ }
+
+ tlb_flush(env, 1);
+}
+
+void HELPER(lctl)(uint32_t r1, uint64_t a2, uint32_t r3)
+{
+ int i;
+ uint64_t src = a2;
+
+ for (i = r1;; i = (i + 1) % 16) {
+ env->cregs[i] = (env->cregs[i] & 0xFFFFFFFF00000000ULL) | ldl(src);
+ src += sizeof(uint32_t);
+
+ if (i == r3) {
+ break;
+ }
+ }
+
+ tlb_flush(env, 1);
+}
+
+void HELPER(stctg)(uint32_t r1, uint64_t a2, uint32_t r3)
+{
+ int i;
+ uint64_t dest = a2;
+
+ for (i = r1;; i = (i + 1) % 16) {
+ stq(dest, env->cregs[i]);
+ dest += sizeof(uint64_t);
+
+ if (i == r3) {
+ break;
+ }
+ }
+}
+
+void HELPER(stctl)(uint32_t r1, uint64_t a2, uint32_t r3)
+{
+ int i;
+ uint64_t dest = a2;
+
+ for (i = r1;; i = (i + 1) % 16) {
+ stl(dest, env->cregs[i]);
+ dest += sizeof(uint32_t);
+
+ if (i == r3) {
+ break;
+ }
+ }
+}
+
+uint32_t HELPER(tprot)(uint64_t a1, uint64_t a2)
+{
+ /* XXX implement */
+
+ return 0;
+}
+
+/* insert storage key extended */
+uint64_t HELPER(iske)(uint64_t r2)
+{
+ uint64_t addr = get_address(0, 0, r2);
+
+ if (addr > ram_size) {
+ return 0;
+ }
+
+ return env->storage_keys[addr / TARGET_PAGE_SIZE];
+}
+
+/* set storage key extended */
+void HELPER(sske)(uint32_t r1, uint64_t r2)
+{
+ uint64_t addr = get_address(0, 0, r2);
+
+ if (addr > ram_size) {
+ return;
+ }
+
+ env->storage_keys[addr / TARGET_PAGE_SIZE] = r1;
+}
+
+/* reset reference bit extended */
+uint32_t HELPER(rrbe)(uint32_t r1, uint64_t r2)
+{
+ uint8_t re;
+ uint8_t key;
+
+ if (r2 > ram_size) {
+ return 0;
+ }
+
+ key = env->storage_keys[r2 / TARGET_PAGE_SIZE];
+ re = key & (SK_R | SK_C);
+ env->storage_keys[r2 / TARGET_PAGE_SIZE] = (key & ~SK_R);
+
+ /*
+ * cc
+ *
+ * 0 Reference bit zero; change bit zero
+ * 1 Reference bit zero; change bit one
+ * 2 Reference bit one; change bit zero
+ * 3 Reference bit one; change bit one
+ */
+
+ return re >> 1;
+}
+
+/* compare and swap and purge */
+uint32_t HELPER(csp)(uint32_t r1, uint32_t r2)
+{
+ uint32_t cc;
+ uint32_t o1 = env->regs[r1];
+ uint64_t a2 = get_address_31fix(r2) & ~3ULL;
+ uint32_t o2 = ldl(a2);
+
+ if (o1 == o2) {
+ stl(a2, env->regs[(r1 + 1) & 15]);
+ if (env->regs[r2] & 0x3) {
+ /* flush TLB / ALB */
+ tlb_flush(env, 1);
+ }
+ cc = 0;
+ } else {
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | o2;
+ cc = 1;
+ }
+
+ return cc;
+}
+
+static uint32_t mvc_asc(int64_t l, uint64_t a1, uint64_t mode1, uint64_t a2,
+ uint64_t mode2)
+{
+ target_ulong src, dest;
+ int flags, cc = 0, i;
+
+ if (!l) {
+ return 0;
+ } else if (l > 256) {
+ /* max 256 */
+ l = 256;
+ cc = 3;
+ }
+
+ if (mmu_translate(env, a1 & TARGET_PAGE_MASK, 1, mode1, &dest, &flags)) {
+ cpu_loop_exit(env);
+ }
+ dest |= a1 & ~TARGET_PAGE_MASK;
+
+ if (mmu_translate(env, a2 & TARGET_PAGE_MASK, 0, mode2, &src, &flags)) {
+ cpu_loop_exit(env);
+ }
+ src |= a2 & ~TARGET_PAGE_MASK;
+
+ /* XXX replace w/ memcpy */
+ for (i = 0; i < l; i++) {
+ /* XXX be more clever */
+ if ((((dest + i) & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) ||
+ (((src + i) & TARGET_PAGE_MASK) != (src & TARGET_PAGE_MASK))) {
+ mvc_asc(l - i, a1 + i, mode1, a2 + i, mode2);
+ break;
+ }
+ stb_phys(dest + i, ldub_phys(src + i));
+ }
+
+ return cc;
+}
+
+uint32_t HELPER(mvcs)(uint64_t l, uint64_t a1, uint64_t a2)
+{
+ HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
+ __func__, l, a1, a2);
+
+ return mvc_asc(l, a1, PSW_ASC_SECONDARY, a2, PSW_ASC_PRIMARY);
+}
+
+uint32_t HELPER(mvcp)(uint64_t l, uint64_t a1, uint64_t a2)
+{
+ HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
+ __func__, l, a1, a2);
+
+ return mvc_asc(l, a1, PSW_ASC_PRIMARY, a2, PSW_ASC_SECONDARY);
+}
+
+/* invalidate pte */
+void HELPER(ipte)(uint64_t pte_addr, uint64_t vaddr)
+{
+ uint64_t page = vaddr & TARGET_PAGE_MASK;
+ uint64_t pte = 0;
+
+ /* XXX broadcast to other CPUs */
+
+ /* XXX Linux is nice enough to give us the exact pte address.
+ According to spec we'd have to find it out ourselves */
+ /* XXX Linux is fine with overwriting the pte, the spec requires
+ us to only set the invalid bit */
+ stq_phys(pte_addr, pte | _PAGE_INVALID);
+
+ /* XXX we exploit the fact that Linux passes the exact virtual
+ address here - it's not obliged to! */
+ tlb_flush_page(env, page);
+
+ /* XXX 31-bit hack */
+ if (page & 0x80000000) {
+ tlb_flush_page(env, page & ~0x80000000);
+ } else {
+ tlb_flush_page(env, page | 0x80000000);
+ }
+}
+
+/* flush local tlb */
+void HELPER(ptlb)(void)
+{
+ tlb_flush(env, 1);
+}
+
+/* store using real address */
+void HELPER(stura)(uint64_t addr, uint32_t v1)
+{
+ stw_phys(get_address(0, 0, addr), v1);
+}
+
+/* load real address */
+uint32_t HELPER(lra)(uint64_t addr, uint32_t r1)
+{
+ uint32_t cc = 0;
+ int old_exc = env->exception_index;
+ uint64_t asc = env->psw.mask & PSW_MASK_ASC;
+ uint64_t ret;
+ int flags;
+
+ /* XXX incomplete - has more corner cases */
+ if (!(env->psw.mask & PSW_MASK_64) && (addr >> 32)) {
+ program_interrupt(env, PGM_SPECIAL_OP, 2);
+ }
+
+ env->exception_index = old_exc;
+ if (mmu_translate(env, addr, 0, asc, &ret, &flags)) {
+ cc = 3;
+ }
+ if (env->exception_index == EXCP_PGM) {
+ ret = env->int_pgm_code | 0x80000000;
+ } else {
+ ret |= addr & ~TARGET_PAGE_MASK;
+ }
+ env->exception_index = old_exc;
+
+ if (!(env->psw.mask & PSW_MASK_64)) {
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
+ (ret & 0xffffffffULL);
+ } else {
+ env->regs[r1] = ret;
+ }
+
+ return cc;
+}
+
+#endif
diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
index 3b8b997..3f8d482 100644
--- a/target-s390x/op_helper.c
+++ b/target-s390x/op_helper.c
@@ -32,57 +32,11 @@
#endif
#if !defined(CONFIG_USER_ONLY)
-#include "sysemu.h"
+#include "softmmu_exec.h"
#endif
-/*****************************************************************************/
-/* Softmmu support */
#if !defined(CONFIG_USER_ONLY)
-#include "softmmu_exec.h"
-
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "softmmu_template.h"
-
-#define SHIFT 1
-#include "softmmu_template.h"
-
-#define SHIFT 2
-#include "softmmu_template.h"
-
-#define SHIFT 3
-#include "softmmu_template.h"
-
-/* try to fill the TLB and return an exception if error. If retaddr is
- NULL, it means that the function was called in C code (i.e. not
- from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUS390XState *env1, target_ulong addr, int is_write, int mmu_idx,
- uintptr_t retaddr)
-{
- TranslationBlock *tb;
- CPUS390XState *saved_env;
- int ret;
-
- saved_env = env;
- env = env1;
- ret = cpu_s390x_handle_mmu_fault(env, addr, is_write, mmu_idx);
- if (unlikely(ret != 0)) {
- if (likely(retaddr)) {
- /* now we have a real cpu fault */
- tb = tb_find_pc(retaddr);
- if (likely(tb)) {
- /* the PC is inside the translated code. It means that we have
- a virtual CPU fault */
- cpu_restore_state(tb, env, retaddr);
- }
- }
- cpu_loop_exit(env);
- }
- env = saved_env;
-}
-
+#include "sysemu.h"
#endif
/* #define DEBUG_HELPER */
@@ -101,840 +55,6 @@ void HELPER(exception)(uint32_t excp)
}
#ifndef CONFIG_USER_ONLY
-static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
- uint8_t byte)
-{
- target_phys_addr_t dest_phys;
- target_phys_addr_t len = l;
- void *dest_p;
- uint64_t asc = env->psw.mask & PSW_MASK_ASC;
- int flags;
-
- if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
- stb(dest, byte);
- cpu_abort(env, "should never reach here");
- }
- dest_phys |= dest & ~TARGET_PAGE_MASK;
-
- dest_p = cpu_physical_memory_map(dest_phys, &len, 1);
-
- memset(dest_p, byte, len);
-
- cpu_physical_memory_unmap(dest_p, 1, len, len);
-}
-
-static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
- uint64_t src)
-{
- target_phys_addr_t dest_phys;
- target_phys_addr_t src_phys;
- target_phys_addr_t len = l;
- void *dest_p;
- void *src_p;
- uint64_t asc = env->psw.mask & PSW_MASK_ASC;
- int flags;
-
- if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
- stb(dest, 0);
- cpu_abort(env, "should never reach here");
- }
- dest_phys |= dest & ~TARGET_PAGE_MASK;
-
- if (mmu_translate(env, src, 0, asc, &src_phys, &flags)) {
- ldub(src);
- cpu_abort(env, "should never reach here");
- }
- src_phys |= src & ~TARGET_PAGE_MASK;
-
- dest_p = cpu_physical_memory_map(dest_phys, &len, 1);
- src_p = cpu_physical_memory_map(src_phys, &len, 0);
-
- memmove(dest_p, src_p, len);
-
- cpu_physical_memory_unmap(dest_p, 1, len, len);
- cpu_physical_memory_unmap(src_p, 0, len, len);
-}
-#endif
-
-/* and on array */
-uint32_t HELPER(nc)(uint32_t l, uint64_t dest, uint64_t src)
-{
- int i;
- unsigned char x;
- uint32_t cc = 0;
-
- HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
- __func__, l, dest, src);
- for (i = 0; i <= l; i++) {
- x = ldub(dest + i) & ldub(src + i);
- if (x) {
- cc = 1;
- }
- stb(dest + i, x);
- }
- return cc;
-}
-
-/* xor on array */
-uint32_t HELPER(xc)(uint32_t l, uint64_t dest, uint64_t src)
-{
- int i;
- unsigned char x;
- uint32_t cc = 0;
-
- HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
- __func__, l, dest, src);
-
-#ifndef CONFIG_USER_ONLY
- /* xor with itself is the same as memset(0) */
- if ((l > 32) && (src == dest) &&
- (src & TARGET_PAGE_MASK) == ((src + l) & TARGET_PAGE_MASK)) {
- mvc_fast_memset(env, l + 1, dest, 0);
- return 0;
- }
-#else
- if (src == dest) {
- memset(g2h(dest), 0, l + 1);
- return 0;
- }
-#endif
-
- for (i = 0; i <= l; i++) {
- x = ldub(dest + i) ^ ldub(src + i);
- if (x) {
- cc = 1;
- }
- stb(dest + i, x);
- }
- return cc;
-}
-
-/* or on array */
-uint32_t HELPER(oc)(uint32_t l, uint64_t dest, uint64_t src)
-{
- int i;
- unsigned char x;
- uint32_t cc = 0;
-
- HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
- __func__, l, dest, src);
- for (i = 0; i <= l; i++) {
- x = ldub(dest + i) | ldub(src + i);
- if (x) {
- cc = 1;
- }
- stb(dest + i, x);
- }
- return cc;
-}
-
-/* memmove */
-void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
-{
- int i = 0;
- int x = 0;
- uint32_t l_64 = (l + 1) / 8;
-
- HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
- __func__, l, dest, src);
-
-#ifndef CONFIG_USER_ONLY
- if ((l > 32) &&
- (src & TARGET_PAGE_MASK) == ((src + l) & TARGET_PAGE_MASK) &&
- (dest & TARGET_PAGE_MASK) == ((dest + l) & TARGET_PAGE_MASK)) {
- if (dest == (src + 1)) {
- mvc_fast_memset(env, l + 1, dest, ldub(src));
- return;
- } else if ((src & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
- mvc_fast_memmove(env, l + 1, dest, src);
- return;
- }
- }
-#else
- if (dest == (src + 1)) {
- memset(g2h(dest), ldub(src), l + 1);
- return;
- } else {
- memmove(g2h(dest), g2h(src), l + 1);
- return;
- }
-#endif
-
- /* handle the parts that fit into 8-byte loads/stores */
- if (dest != (src + 1)) {
- for (i = 0; i < l_64; i++) {
- stq(dest + x, ldq(src + x));
- x += 8;
- }
- }
-
- /* slow version crossing pages with byte accesses */
- for (i = x; i <= l; i++) {
- stb(dest + i, ldub(src + i));
- }
-}
-
-/* compare unsigned byte arrays */
-uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
-{
- int i;
- unsigned char x, y;
- uint32_t cc;
-
- HELPER_LOG("%s l %d s1 %" PRIx64 " s2 %" PRIx64 "\n",
- __func__, l, s1, s2);
- for (i = 0; i <= l; i++) {
- x = ldub(s1 + i);
- y = ldub(s2 + i);
- HELPER_LOG("%02x (%c)/%02x (%c) ", x, x, y, y);
- if (x < y) {
- cc = 1;
- goto done;
- } else if (x > y) {
- cc = 2;
- goto done;
- }
- }
- cc = 0;
- done:
- HELPER_LOG("\n");
- return cc;
-}
-
-/* compare logical under mask */
-uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
-{
- uint8_t r, d;
- uint32_t cc;
-
- HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%" PRIx64 "\n", __func__, r1,
- mask, addr);
- cc = 0;
- while (mask) {
- if (mask & 8) {
- d = ldub(addr);
- r = (r1 & 0xff000000UL) >> 24;
- HELPER_LOG("mask 0x%x %02x/%02x (0x%" PRIx64 ") ", mask, r, d,
- addr);
- if (r < d) {
- cc = 1;
- break;
- } else if (r > d) {
- cc = 2;
- break;
- }
- addr++;
- }
- mask = (mask << 1) & 0xf;
- r1 <<= 8;
- }
- HELPER_LOG("\n");
- return cc;
-}
-
-/* store character under mask */
-void HELPER(stcm)(uint32_t r1, uint32_t mask, uint64_t addr)
-{
- uint8_t r;
-
- HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%lx\n", __func__, r1, mask,
- addr);
- while (mask) {
- if (mask & 8) {
- r = (r1 & 0xff000000UL) >> 24;
- stb(addr, r);
- HELPER_LOG("mask 0x%x %02x (0x%lx) ", mask, r, addr);
- addr++;
- }
- mask = (mask << 1) & 0xf;
- r1 <<= 8;
- }
- HELPER_LOG("\n");
-}
-
-static inline uint64_t get_address(int x2, int b2, int d2)
-{
- uint64_t r = d2;
-
- if (x2) {
- r += env->regs[x2];
- }
-
- if (b2) {
- r += env->regs[b2];
- }
-
- /* 31-Bit mode */
- if (!(env->psw.mask & PSW_MASK_64)) {
- r &= 0x7fffffff;
- }
-
- return r;
-}
-
-static inline uint64_t get_address_31fix(int reg)
-{
- uint64_t r = env->regs[reg];
-
- /* 31-Bit mode */
- if (!(env->psw.mask & PSW_MASK_64)) {
- r &= 0x7fffffff;
- }
-
- return r;
-}
-
-/* search string (c is byte to search, r2 is string, r1 end of string) */
-uint32_t HELPER(srst)(uint32_t c, uint32_t r1, uint32_t r2)
-{
- uint64_t i;
- uint32_t cc = 2;
- uint64_t str = get_address_31fix(r2);
- uint64_t end = get_address_31fix(r1);
-
- HELPER_LOG("%s: c %d *r1 0x%" PRIx64 " *r2 0x%" PRIx64 "\n", __func__,
- c, env->regs[r1], env->regs[r2]);
-
- for (i = str; i != end; i++) {
- if (ldub(i) == c) {
- env->regs[r1] = i;
- cc = 1;
- break;
- }
- }
-
- return cc;
-}
-
-/* unsigned string compare (c is string terminator) */
-uint32_t HELPER(clst)(uint32_t c, uint32_t r1, uint32_t r2)
-{
- uint64_t s1 = get_address_31fix(r1);
- uint64_t s2 = get_address_31fix(r2);
- uint8_t v1, v2;
- uint32_t cc;
-
- c = c & 0xff;
-#ifdef CONFIG_USER_ONLY
- if (!c) {
- HELPER_LOG("%s: comparing '%s' and '%s'\n",
- __func__, (char *)g2h(s1), (char *)g2h(s2));
- }
-#endif
- for (;;) {
- v1 = ldub(s1);
- v2 = ldub(s2);
- if ((v1 == c || v2 == c) || (v1 != v2)) {
- break;
- }
- s1++;
- s2++;
- }
-
- if (v1 == v2) {
- cc = 0;
- } else {
- cc = (v1 < v2) ? 1 : 2;
- /* FIXME: 31-bit mode! */
- env->regs[r1] = s1;
- env->regs[r2] = s2;
- }
- return cc;
-}
-
-/* move page */
-void HELPER(mvpg)(uint64_t r0, uint64_t r1, uint64_t r2)
-{
- /* XXX missing r0 handling */
-#ifdef CONFIG_USER_ONLY
- int i;
-
- for (i = 0; i < TARGET_PAGE_SIZE; i++) {
- stb(r1 + i, ldub(r2 + i));
- }
-#else
- mvc_fast_memmove(env, TARGET_PAGE_SIZE, r1, r2);
-#endif
-}
-
-/* string copy (c is string terminator) */
-void HELPER(mvst)(uint32_t c, uint32_t r1, uint32_t r2)
-{
- uint64_t dest = get_address_31fix(r1);
- uint64_t src = get_address_31fix(r2);
- uint8_t v;
-
- c = c & 0xff;
-#ifdef CONFIG_USER_ONLY
- if (!c) {
- HELPER_LOG("%s: copy '%s' to 0x%lx\n", __func__, (char *)g2h(src),
- dest);
- }
-#endif
- for (;;) {
- v = ldub(src);
- stb(dest, v);
- if (v == c) {
- break;
- }
- src++;
- dest++;
- }
- env->regs[r1] = dest; /* FIXME: 31-bit mode! */
-}
-
-/* compare and swap 64-bit */
-uint32_t HELPER(csg)(uint32_t r1, uint64_t a2, uint32_t r3)
-{
- /* FIXME: locking? */
- uint32_t cc;
- uint64_t v2 = ldq(a2);
-
- if (env->regs[r1] == v2) {
- cc = 0;
- stq(a2, env->regs[r3]);
- } else {
- cc = 1;
- env->regs[r1] = v2;
- }
- return cc;
-}
-
-/* compare double and swap 64-bit */
-uint32_t HELPER(cdsg)(uint32_t r1, uint64_t a2, uint32_t r3)
-{
- /* FIXME: locking? */
- uint32_t cc;
- uint64_t v2_hi = ldq(a2);
- uint64_t v2_lo = ldq(a2 + 8);
- uint64_t v1_hi = env->regs[r1];
- uint64_t v1_lo = env->regs[r1 + 1];
-
- if ((v1_hi == v2_hi) && (v1_lo == v2_lo)) {
- cc = 0;
- stq(a2, env->regs[r3]);
- stq(a2 + 8, env->regs[r3 + 1]);
- } else {
- cc = 1;
- env->regs[r1] = v2_hi;
- env->regs[r1 + 1] = v2_lo;
- }
-
- return cc;
-}
-
-/* compare and swap 32-bit */
-uint32_t HELPER(cs)(uint32_t r1, uint64_t a2, uint32_t r3)
-{
- /* FIXME: locking? */
- uint32_t cc;
- uint32_t v2 = ldl(a2);
-
- HELPER_LOG("%s: r1 %d a2 0x%lx r3 %d\n", __func__, r1, a2, r3);
- if (((uint32_t)env->regs[r1]) == v2) {
- cc = 0;
- stl(a2, (uint32_t)env->regs[r3]);
- } else {
- cc = 1;
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | v2;
- }
- return cc;
-}
-
-static uint32_t helper_icm(uint32_t r1, uint64_t address, uint32_t mask)
-{
- int pos = 24; /* top of the lower half of r1 */
- uint64_t rmask = 0xff000000ULL;
- uint8_t val = 0;
- int ccd = 0;
- uint32_t cc = 0;
-
- while (mask) {
- if (mask & 8) {
- env->regs[r1] &= ~rmask;
- val = ldub(address);
- if ((val & 0x80) && !ccd) {
- cc = 1;
- }
- ccd = 1;
- if (val && cc == 0) {
- cc = 2;
- }
- env->regs[r1] |= (uint64_t)val << pos;
- address++;
- }
- mask = (mask << 1) & 0xf;
- pos -= 8;
- rmask >>= 8;
- }
-
- return cc;
-}
-
-/* execute instruction
- this instruction executes an insn modified with the contents of r1
- it does not change the executed instruction in memory
- it does not change the program counter
- in other words: tricky...
- currently implemented by interpreting the cases it is most commonly used in
-*/
-uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
-{
- uint16_t insn = lduw_code(addr);
-
- HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr,
- insn);
- if ((insn & 0xf0ff) == 0xd000) {
- uint32_t l, insn2, b1, b2, d1, d2;
-
- l = v1 & 0xff;
- insn2 = ldl_code(addr + 2);
- b1 = (insn2 >> 28) & 0xf;
- b2 = (insn2 >> 12) & 0xf;
- d1 = (insn2 >> 16) & 0xfff;
- d2 = insn2 & 0xfff;
- switch (insn & 0xf00) {
- case 0x200:
- helper_mvc(l, get_address(0, b1, d1), get_address(0, b2, d2));
- break;
- case 0x500:
- cc = helper_clc(l, get_address(0, b1, d1), get_address(0, b2, d2));
- break;
- case 0x700:
- cc = helper_xc(l, get_address(0, b1, d1), get_address(0, b2, d2));
- break;
- case 0xc00:
- helper_tr(l, get_address(0, b1, d1), get_address(0, b2, d2));
- break;
- default:
- goto abort;
- break;
- }
- } else if ((insn & 0xff00) == 0x0a00) {
- /* supervisor call */
- HELPER_LOG("%s: svc %ld via execute\n", __func__, (insn | v1) & 0xff);
- env->psw.addr = ret - 4;
- env->int_svc_code = (insn | v1) & 0xff;
- env->int_svc_ilc = 4;
- helper_exception(EXCP_SVC);
- } else if ((insn & 0xff00) == 0xbf00) {
- uint32_t insn2, r1, r3, b2, d2;
-
- insn2 = ldl_code(addr + 2);
- r1 = (insn2 >> 20) & 0xf;
- r3 = (insn2 >> 16) & 0xf;
- b2 = (insn2 >> 12) & 0xf;
- d2 = insn2 & 0xfff;
- cc = helper_icm(r1, get_address(0, b2, d2), r3);
- } else {
- abort:
- cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n",
- insn);
- }
- return cc;
-}
-
-/* store character under mask high operates on the upper half of r1 */
-void HELPER(stcmh)(uint32_t r1, uint64_t address, uint32_t mask)
-{
- int pos = 56; /* top of the upper half of r1 */
-
- while (mask) {
- if (mask & 8) {
- stb(address, (env->regs[r1] >> pos) & 0xff);
- address++;
- }
- mask = (mask << 1) & 0xf;
- pos -= 8;
- }
-}
-
-/* insert character under mask high; same as icm, but operates on the
- upper half of r1 */
-uint32_t HELPER(icmh)(uint32_t r1, uint64_t address, uint32_t mask)
-{
- int pos = 56; /* top of the upper half of r1 */
- uint64_t rmask = 0xff00000000000000ULL;
- uint8_t val = 0;
- int ccd = 0;
- uint32_t cc = 0;
-
- while (mask) {
- if (mask & 8) {
- env->regs[r1] &= ~rmask;
- val = ldub(address);
- if ((val & 0x80) && !ccd) {
- cc = 1;
- }
- ccd = 1;
- if (val && cc == 0) {
- cc = 2;
- }
- env->regs[r1] |= (uint64_t)val << pos;
- address++;
- }
- mask = (mask << 1) & 0xf;
- pos -= 8;
- rmask >>= 8;
- }
-
- return cc;
-}
-
-/* load access registers r1 to r3 from memory at a2 */
-void HELPER(lam)(uint32_t r1, uint64_t a2, uint32_t r3)
-{
- int i;
-
- for (i = r1;; i = (i + 1) % 16) {
- env->aregs[i] = ldl(a2);
- a2 += 4;
-
- if (i == r3) {
- break;
- }
- }
-}
-
-/* store access registers r1 to r3 in memory at a2 */
-void HELPER(stam)(uint32_t r1, uint64_t a2, uint32_t r3)
-{
- int i;
-
- for (i = r1;; i = (i + 1) % 16) {
- stl(a2, env->aregs[i]);
- a2 += 4;
-
- if (i == r3) {
- break;
- }
- }
-}
-
-/* move long */
-uint32_t HELPER(mvcl)(uint32_t r1, uint32_t r2)
-{
- uint64_t destlen = env->regs[r1 + 1] & 0xffffff;
- uint64_t dest = get_address_31fix(r1);
- uint64_t srclen = env->regs[r2 + 1] & 0xffffff;
- uint64_t src = get_address_31fix(r2);
- uint8_t pad = src >> 24;
- uint8_t v;
- uint32_t cc;
-
- if (destlen == srclen) {
- cc = 0;
- } else if (destlen < srclen) {
- cc = 1;
- } else {
- cc = 2;
- }
-
- if (srclen > destlen) {
- srclen = destlen;
- }
-
- for (; destlen && srclen; src++, dest++, destlen--, srclen--) {
- v = ldub(src);
- stb(dest, v);
- }
-
- for (; destlen; dest++, destlen--) {
- stb(dest, pad);
- }
-
- env->regs[r1 + 1] = destlen;
- /* can't use srclen here, we trunc'ed it */
- env->regs[r2 + 1] -= src - env->regs[r2];
- env->regs[r1] = dest;
- env->regs[r2] = src;
-
- return cc;
-}
-
-/* move long extended another memcopy insn with more bells and whistles */
-uint32_t HELPER(mvcle)(uint32_t r1, uint64_t a2, uint32_t r3)
-{
- uint64_t destlen = env->regs[r1 + 1];
- uint64_t dest = env->regs[r1];
- uint64_t srclen = env->regs[r3 + 1];
- uint64_t src = env->regs[r3];
- uint8_t pad = a2 & 0xff;
- uint8_t v;
- uint32_t cc;
-
- if (!(env->psw.mask & PSW_MASK_64)) {
- destlen = (uint32_t)destlen;
- srclen = (uint32_t)srclen;
- dest &= 0x7fffffff;
- src &= 0x7fffffff;
- }
-
- if (destlen == srclen) {
- cc = 0;
- } else if (destlen < srclen) {
- cc = 1;
- } else {
- cc = 2;
- }
-
- if (srclen > destlen) {
- srclen = destlen;
- }
-
- for (; destlen && srclen; src++, dest++, destlen--, srclen--) {
- v = ldub(src);
- stb(dest, v);
- }
-
- for (; destlen; dest++, destlen--) {
- stb(dest, pad);
- }
-
- env->regs[r1 + 1] = destlen;
- /* can't use srclen here, we trunc'ed it */
- /* FIXME: 31-bit mode! */
- env->regs[r3 + 1] -= src - env->regs[r3];
- env->regs[r1] = dest;
- env->regs[r3] = src;
-
- return cc;
-}
-
-/* compare logical long extended memcompare insn with padding */
-uint32_t HELPER(clcle)(uint32_t r1, uint64_t a2, uint32_t r3)
-{
- uint64_t destlen = env->regs[r1 + 1];
- uint64_t dest = get_address_31fix(r1);
- uint64_t srclen = env->regs[r3 + 1];
- uint64_t src = get_address_31fix(r3);
- uint8_t pad = a2 & 0xff;
- uint8_t v1 = 0, v2 = 0;
- uint32_t cc = 0;
-
- if (!(destlen || srclen)) {
- return cc;
- }
-
- if (srclen > destlen) {
- srclen = destlen;
- }
-
- for (; destlen || srclen; src++, dest++, destlen--, srclen--) {
- v1 = srclen ? ldub(src) : pad;
- v2 = destlen ? ldub(dest) : pad;
- if (v1 != v2) {
- cc = (v1 < v2) ? 1 : 2;
- break;
- }
- }
-
- env->regs[r1 + 1] = destlen;
- /* can't use srclen here, we trunc'ed it */
- env->regs[r3 + 1] -= src - env->regs[r3];
- env->regs[r1] = dest;
- env->regs[r3] = src;
-
- return cc;
-}
-
-/* checksum */
-void HELPER(cksm)(uint32_t r1, uint32_t r2)
-{
- uint64_t src = get_address_31fix(r2);
- uint64_t src_len = env->regs[(r2 + 1) & 15];
- uint64_t cksm = (uint32_t)env->regs[r1];
-
- while (src_len >= 4) {
- cksm += ldl(src);
-
- /* move to next word */
- src_len -= 4;
- src += 4;
- }
-
- switch (src_len) {
- case 0:
- break;
- case 1:
- cksm += ldub(src) << 24;
- break;
- case 2:
- cksm += lduw(src) << 16;
- break;
- case 3:
- cksm += lduw(src) << 16;
- cksm += ldub(src + 2) << 8;
- break;
- }
-
- /* indicate we've processed everything */
- env->regs[r2] = src + src_len;
- env->regs[(r2 + 1) & 15] = 0;
-
- /* store result */
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
- ((uint32_t)cksm + (cksm >> 32));
-}
-
-void HELPER(unpk)(uint32_t len, uint64_t dest, uint64_t src)
-{
- int len_dest = len >> 4;
- int len_src = len & 0xf;
- uint8_t b;
- int second_nibble = 0;
-
- dest += len_dest;
- src += len_src;
-
- /* last byte is special, it only flips the nibbles */
- b = ldub(src);
- stb(dest, (b << 4) | (b >> 4));
- src--;
- len_src--;
-
- /* now pad every nibble with 0xf0 */
-
- while (len_dest > 0) {
- uint8_t cur_byte = 0;
-
- if (len_src > 0) {
- cur_byte = ldub(src);
- }
-
- len_dest--;
- dest--;
-
- /* only advance one nibble at a time */
- if (second_nibble) {
- cur_byte >>= 4;
- len_src--;
- src--;
- }
- second_nibble = !second_nibble;
-
- /* digit */
- cur_byte = (cur_byte & 0xf);
- /* zone bits */
- cur_byte |= 0xf0;
-
- stb(dest, cur_byte);
- }
-}
-
-void HELPER(tr)(uint32_t len, uint64_t array, uint64_t trans)
-{
- int i;
-
- for (i = 0; i <= len; i++) {
- uint8_t byte = ldub(array + i);
- uint8_t new_byte = ldub(trans + byte);
-
- stb(array + i, new_byte);
- }
-}
-
-#ifndef CONFIG_USER_ONLY
void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
{
qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
@@ -1267,206 +387,6 @@ uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
return cc;
}
-void HELPER(lctlg)(uint32_t r1, uint64_t a2, uint32_t r3)
-{
- int i;
- uint64_t src = a2;
-
- for (i = r1;; i = (i + 1) % 16) {
- env->cregs[i] = ldq(src);
- HELPER_LOG("load ctl %d from 0x%" PRIx64 " == 0x%" PRIx64 "\n",
- i, src, env->cregs[i]);
- src += sizeof(uint64_t);
-
- if (i == r3) {
- break;
- }
- }
-
- tlb_flush(env, 1);
-}
-
-void HELPER(lctl)(uint32_t r1, uint64_t a2, uint32_t r3)
-{
- int i;
- uint64_t src = a2;
-
- for (i = r1;; i = (i + 1) % 16) {
- env->cregs[i] = (env->cregs[i] & 0xFFFFFFFF00000000ULL) | ldl(src);
- src += sizeof(uint32_t);
-
- if (i == r3) {
- break;
- }
- }
-
- tlb_flush(env, 1);
-}
-
-void HELPER(stctg)(uint32_t r1, uint64_t a2, uint32_t r3)
-{
- int i;
- uint64_t dest = a2;
-
- for (i = r1;; i = (i + 1) % 16) {
- stq(dest, env->cregs[i]);
- dest += sizeof(uint64_t);
-
- if (i == r3) {
- break;
- }
- }
-}
-
-void HELPER(stctl)(uint32_t r1, uint64_t a2, uint32_t r3)
-{
- int i;
- uint64_t dest = a2;
-
- for (i = r1;; i = (i + 1) % 16) {
- stl(dest, env->cregs[i]);
- dest += sizeof(uint32_t);
-
- if (i == r3) {
- break;
- }
- }
-}
-
-uint32_t HELPER(tprot)(uint64_t a1, uint64_t a2)
-{
- /* XXX implement */
-
- return 0;
-}
-
-/* insert storage key extended */
-uint64_t HELPER(iske)(uint64_t r2)
-{
- uint64_t addr = get_address(0, 0, r2);
-
- if (addr > ram_size) {
- return 0;
- }
-
- return env->storage_keys[addr / TARGET_PAGE_SIZE];
-}
-
-/* set storage key extended */
-void HELPER(sske)(uint32_t r1, uint64_t r2)
-{
- uint64_t addr = get_address(0, 0, r2);
-
- if (addr > ram_size) {
- return;
- }
-
- env->storage_keys[addr / TARGET_PAGE_SIZE] = r1;
-}
-
-/* reset reference bit extended */
-uint32_t HELPER(rrbe)(uint32_t r1, uint64_t r2)
-{
- uint8_t re;
- uint8_t key;
-
- if (r2 > ram_size) {
- return 0;
- }
-
- key = env->storage_keys[r2 / TARGET_PAGE_SIZE];
- re = key & (SK_R | SK_C);
- env->storage_keys[r2 / TARGET_PAGE_SIZE] = (key & ~SK_R);
-
- /*
- * cc
- *
- * 0 Reference bit zero; change bit zero
- * 1 Reference bit zero; change bit one
- * 2 Reference bit one; change bit zero
- * 3 Reference bit one; change bit one
- */
-
- return re >> 1;
-}
-
-/* compare and swap and purge */
-uint32_t HELPER(csp)(uint32_t r1, uint32_t r2)
-{
- uint32_t cc;
- uint32_t o1 = env->regs[r1];
- uint64_t a2 = get_address_31fix(r2) & ~3ULL;
- uint32_t o2 = ldl(a2);
-
- if (o1 == o2) {
- stl(a2, env->regs[(r1 + 1) & 15]);
- if (env->regs[r2] & 0x3) {
- /* flush TLB / ALB */
- tlb_flush(env, 1);
- }
- cc = 0;
- } else {
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | o2;
- cc = 1;
- }
-
- return cc;
-}
-
-static uint32_t mvc_asc(int64_t l, uint64_t a1, uint64_t mode1, uint64_t a2,
- uint64_t mode2)
-{
- target_ulong src, dest;
- int flags, cc = 0, i;
-
- if (!l) {
- return 0;
- } else if (l > 256) {
- /* max 256 */
- l = 256;
- cc = 3;
- }
-
- if (mmu_translate(env, a1 & TARGET_PAGE_MASK, 1, mode1, &dest, &flags)) {
- cpu_loop_exit(env);
- }
- dest |= a1 & ~TARGET_PAGE_MASK;
-
- if (mmu_translate(env, a2 & TARGET_PAGE_MASK, 0, mode2, &src, &flags)) {
- cpu_loop_exit(env);
- }
- src |= a2 & ~TARGET_PAGE_MASK;
-
- /* XXX replace w/ memcpy */
- for (i = 0; i < l; i++) {
- /* XXX be more clever */
- if ((((dest + i) & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) ||
- (((src + i) & TARGET_PAGE_MASK) != (src & TARGET_PAGE_MASK))) {
- mvc_asc(l - i, a1 + i, mode1, a2 + i, mode2);
- break;
- }
- stb_phys(dest + i, ldub_phys(src + i));
- }
-
- return cc;
-}
-
-uint32_t HELPER(mvcs)(uint64_t l, uint64_t a1, uint64_t a2)
-{
- HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
- __func__, l, a1, a2);
-
- return mvc_asc(l, a1, PSW_ASC_SECONDARY, a2, PSW_ASC_PRIMARY);
-}
-
-uint32_t HELPER(mvcp)(uint64_t l, uint64_t a1, uint64_t a2)
-{
- HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
- __func__, l, a1, a2);
-
- return mvc_asc(l, a1, PSW_ASC_PRIMARY, a2, PSW_ASC_SECONDARY);
-}
-
uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
{
int cc = 0;
@@ -1508,78 +428,4 @@ uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
return cc;
}
-
-/* invalidate pte */
-void HELPER(ipte)(uint64_t pte_addr, uint64_t vaddr)
-{
- uint64_t page = vaddr & TARGET_PAGE_MASK;
- uint64_t pte = 0;
-
- /* XXX broadcast to other CPUs */
-
- /* XXX Linux is nice enough to give us the exact pte address.
- According to spec we'd have to find it out ourselves */
- /* XXX Linux is fine with overwriting the pte, the spec requires
- us to only set the invalid bit */
- stq_phys(pte_addr, pte | _PAGE_INVALID);
-
- /* XXX we exploit the fact that Linux passes the exact virtual
- address here - it's not obliged to! */
- tlb_flush_page(env, page);
-
- /* XXX 31-bit hack */
- if (page & 0x80000000) {
- tlb_flush_page(env, page & ~0x80000000);
- } else {
- tlb_flush_page(env, page | 0x80000000);
- }
-}
-
-/* flush local tlb */
-void HELPER(ptlb)(void)
-{
- tlb_flush(env, 1);
-}
-
-/* store using real address */
-void HELPER(stura)(uint64_t addr, uint32_t v1)
-{
- stw_phys(get_address(0, 0, addr), v1);
-}
-
-/* load real address */
-uint32_t HELPER(lra)(uint64_t addr, uint32_t r1)
-{
- uint32_t cc = 0;
- int old_exc = env->exception_index;
- uint64_t asc = env->psw.mask & PSW_MASK_ASC;
- uint64_t ret;
- int flags;
-
- /* XXX incomplete - has more corner cases */
- if (!(env->psw.mask & PSW_MASK_64) && (addr >> 32)) {
- program_interrupt(env, PGM_SPECIAL_OP, 2);
- }
-
- env->exception_index = old_exc;
- if (mmu_translate(env, addr, 0, asc, &ret, &flags)) {
- cc = 3;
- }
- if (env->exception_index == EXCP_PGM) {
- ret = env->int_pgm_code | 0x80000000;
- } else {
- ret |= addr & ~TARGET_PAGE_MASK;
- }
- env->exception_index = old_exc;
-
- if (!(env->psw.mask & PSW_MASK_64)) {
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
- (ret & 0xffffffffULL);
- } else {
- env->regs[r1] = ret;
- }
-
- return cc;
-}
-
#endif
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 05/21] target-s390x: split memory access helpers
2012-09-02 17:33 ` [Qemu-devel] [PATCH 05/21] target-s390x: split memory access helpers Blue Swirl
@ 2012-09-06 18:14 ` Alexander Graf
0 siblings, 0 replies; 64+ messages in thread
From: Alexander Graf @ 2012-09-06 18:14 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel
On 02.09.2012, at 13:33, Blue Swirl wrote:
> Move memory access helpers to mem_helper.c.
>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> ---
> target-s390x/Makefile.objs | 3 +-
> target-s390x/mem_helper.c | 1190 ++++++++++++++++++++++++++++++++++++++++++++
> target-s390x/op_helper.c | 1158 +------------------------------------------
> 3 files changed, 1194 insertions(+), 1157 deletions(-)
> create mode 100644 target-s390x/mem_helper.c
>
> diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
> index e8f66e9..b9b3061 100644
> --- a/target-s390x/Makefile.objs
> +++ b/target-s390x/Makefile.objs
> @@ -1,5 +1,5 @@
> obj-y += translate.o op_helper.o helper.o cpu.o interrupt.o
> -obj-y += int_helper.o fpu_helper.o cc_helper.o
> +obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o
> obj-$(CONFIG_SOFTMMU) += machine.o
> obj-$(CONFIG_KVM) += kvm.o
>
> @@ -7,3 +7,4 @@ $(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> $(obj)/int_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> $(obj)/fpu_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> $(obj)/cc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> +$(obj)/mem_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> new file mode 100644
> index 0000000..ba05e65
> --- /dev/null
> +++ b/target-s390x/mem_helper.c
> @@ -0,0 +1,1190 @@
> +/*
> + * S/390 memory access helper routines
> + *
> + * Copyright (c) 2009 Ulrich Hecht
> + * Copyright (c) 2009 Alexander Graf
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "cpu.h"
> +#include "dyngen-exec.h"
> +#include "helper.h"
> +
> +/*****************************************************************************/
> +/* Softmmu support */
> +#if !defined(CONFIG_USER_ONLY)
> +#include "softmmu_exec.h"
> +
> +#define MMUSUFFIX _mmu
> +
> +#define SHIFT 0
> +#include "softmmu_template.h"
> +
> +#define SHIFT 1
> +#include "softmmu_template.h"
> +
> +#define SHIFT 2
> +#include "softmmu_template.h"
> +
> +#define SHIFT 3
> +#include "softmmu_template.h"
> +
> +/* try to fill the TLB and return an exception if error. If retaddr is
> + NULL, it means that the function was called in C code (i.e. not
> + from generated code or from helper.c) */
> +/* XXX: fix it to restore all registers */
> +void tlb_fill(CPUS390XState *env1, target_ulong addr, int is_write, int mmu_idx,
> + uintptr_t retaddr)
> +{
> + TranslationBlock *tb;
> + CPUS390XState *saved_env;
> + int ret;
> +
> + saved_env = env;
> + env = env1;
> + ret = cpu_s390x_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + if (unlikely(ret != 0)) {
> + if (likely(retaddr)) {
> + /* now we have a real cpu fault */
> + tb = tb_find_pc(retaddr);
> + if (likely(tb)) {
> + /* the PC is inside the translated code. It means that we have
> + a virtual CPU fault */
> + cpu_restore_state(tb, env, retaddr);
> + }
> + }
> + cpu_loop_exit(env);
> + }
> + env = saved_env;
> +}
> +
> +#endif
> +
> +/* #define DEBUG_HELPER */
> +#ifdef DEBUG_HELPER
> +#define HELPER_LOG(x...) qemu_log(x)
> +#else
> +#define HELPER_LOG(x...)
> +#endif
> +
> +#ifndef CONFIG_USER_ONLY
> +static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
> + uint8_t byte)
> +{
> + target_phys_addr_t dest_phys;
> + target_phys_addr_t len = l;
> + void *dest_p;
> + uint64_t asc = env->psw.mask & PSW_MASK_ASC;
> + int flags;
> +
> + if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
> + stb(dest, byte);
> + cpu_abort(env, "should never reach here");
> + }
> + dest_phys |= dest & ~TARGET_PAGE_MASK;
> +
> + dest_p = cpu_physical_memory_map(dest_phys, &len, 1);
> +
> + memset(dest_p, byte, len);
> +
> + cpu_physical_memory_unmap(dest_p, 1, len, len);
> +}
> +
> +static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
> + uint64_t src)
> +{
> + target_phys_addr_t dest_phys;
> + target_phys_addr_t src_phys;
> + target_phys_addr_t len = l;
> + void *dest_p;
> + void *src_p;
> + uint64_t asc = env->psw.mask & PSW_MASK_ASC;
> + int flags;
> +
> + if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
> + stb(dest, 0);
> + cpu_abort(env, "should never reach here");
> + }
> + dest_phys |= dest & ~TARGET_PAGE_MASK;
> +
> + if (mmu_translate(env, src, 0, asc, &src_phys, &flags)) {
> + ldub(src);
> + cpu_abort(env, "should never reach here");
> + }
> + src_phys |= src & ~TARGET_PAGE_MASK;
> +
> + dest_p = cpu_physical_memory_map(dest_phys, &len, 1);
> + src_p = cpu_physical_memory_map(src_phys, &len, 0);
> +
> + memmove(dest_p, src_p, len);
> +
> + cpu_physical_memory_unmap(dest_p, 1, len, len);
> + cpu_physical_memory_unmap(src_p, 0, len, len);
> +}
> +#endif
> +
> +/* and on array */
> +uint32_t HELPER(nc)(uint32_t l, uint64_t dest, uint64_t src)
> +{
> + int i;
> + unsigned char x;
> + uint32_t cc = 0;
> +
> + HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
> + __func__, l, dest, src);
> + for (i = 0; i <= l; i++) {
> + x = ldub(dest + i) & ldub(src + i);
> + if (x) {
> + cc = 1;
> + }
> + stb(dest + i, x);
> + }
> + return cc;
> +}
> +
> +/* xor on array */
> +uint32_t HELPER(xc)(uint32_t l, uint64_t dest, uint64_t src)
> +{
> + int i;
> + unsigned char x;
> + uint32_t cc = 0;
> +
> + HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
> + __func__, l, dest, src);
> +
> +#ifndef CONFIG_USER_ONLY
> + /* xor with itself is the same as memset(0) */
> + if ((l > 32) && (src == dest) &&
> + (src & TARGET_PAGE_MASK) == ((src + l) & TARGET_PAGE_MASK)) {
> + mvc_fast_memset(env, l + 1, dest, 0);
> + return 0;
> + }
> +#else
> + if (src == dest) {
> + memset(g2h(dest), 0, l + 1);
> + return 0;
> + }
> +#endif
> +
> + for (i = 0; i <= l; i++) {
> + x = ldub(dest + i) ^ ldub(src + i);
> + if (x) {
> + cc = 1;
> + }
> + stb(dest + i, x);
> + }
> + return cc;
> +}
> +
> +/* or on array */
> +uint32_t HELPER(oc)(uint32_t l, uint64_t dest, uint64_t src)
> +{
> + int i;
> + unsigned char x;
> + uint32_t cc = 0;
> +
> + HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
> + __func__, l, dest, src);
> + for (i = 0; i <= l; i++) {
> + x = ldub(dest + i) | ldub(src + i);
> + if (x) {
> + cc = 1;
> + }
> + stb(dest + i, x);
> + }
> + return cc;
> +}
> +
> +/* memmove */
> +void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
> +{
> + int i = 0;
> + int x = 0;
> + uint32_t l_64 = (l + 1) / 8;
> +
> + HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
> + __func__, l, dest, src);
> +
> +#ifndef CONFIG_USER_ONLY
> + if ((l > 32) &&
> + (src & TARGET_PAGE_MASK) == ((src + l) & TARGET_PAGE_MASK) &&
> + (dest & TARGET_PAGE_MASK) == ((dest + l) & TARGET_PAGE_MASK)) {
> + if (dest == (src + 1)) {
> + mvc_fast_memset(env, l + 1, dest, ldub(src));
> + return;
> + } else if ((src & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
> + mvc_fast_memmove(env, l + 1, dest, src);
> + return;
> + }
> + }
> +#else
> + if (dest == (src + 1)) {
> + memset(g2h(dest), ldub(src), l + 1);
> + return;
> + } else {
> + memmove(g2h(dest), g2h(src), l + 1);
> + return;
> + }
> +#endif
> +
> + /* handle the parts that fit into 8-byte loads/stores */
> + if (dest != (src + 1)) {
> + for (i = 0; i < l_64; i++) {
> + stq(dest + x, ldq(src + x));
> + x += 8;
> + }
> + }
> +
> + /* slow version crossing pages with byte accesses */
> + for (i = x; i <= l; i++) {
> + stb(dest + i, ldub(src + i));
> + }
> +}
> +
> +/* compare unsigned byte arrays */
> +uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
> +{
> + int i;
> + unsigned char x, y;
> + uint32_t cc;
> +
> + HELPER_LOG("%s l %d s1 %" PRIx64 " s2 %" PRIx64 "\n",
> + __func__, l, s1, s2);
> + for (i = 0; i <= l; i++) {
> + x = ldub(s1 + i);
> + y = ldub(s2 + i);
> + HELPER_LOG("%02x (%c)/%02x (%c) ", x, x, y, y);
> + if (x < y) {
> + cc = 1;
> + goto done;
> + } else if (x > y) {
> + cc = 2;
> + goto done;
> + }
> + }
> + cc = 0;
> + done:
> + HELPER_LOG("\n");
> + return cc;
> +}
> +
> +/* compare logical under mask */
> +uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
> +{
> + uint8_t r, d;
> + uint32_t cc;
> +
> + HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%" PRIx64 "\n", __func__, r1,
> + mask, addr);
> + cc = 0;
> + while (mask) {
> + if (mask & 8) {
> + d = ldub(addr);
> + r = (r1 & 0xff000000UL) >> 24;
> + HELPER_LOG("mask 0x%x %02x/%02x (0x%" PRIx64 ") ", mask, r, d,
> + addr);
> + if (r < d) {
> + cc = 1;
> + break;
> + } else if (r > d) {
> + cc = 2;
> + break;
> + }
> + addr++;
> + }
> + mask = (mask << 1) & 0xf;
> + r1 <<= 8;
> + }
> + HELPER_LOG("\n");
> + return cc;
> +}
> +
> +/* store character under mask */
> +void HELPER(stcm)(uint32_t r1, uint32_t mask, uint64_t addr)
> +{
> + uint8_t r;
> +
> + HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%lx\n", __func__, r1, mask,
> + addr);
> + while (mask) {
> + if (mask & 8) {
> + r = (r1 & 0xff000000UL) >> 24;
> + stb(addr, r);
> + HELPER_LOG("mask 0x%x %02x (0x%lx) ", mask, r, addr);
> + addr++;
> + }
> + mask = (mask << 1) & 0xf;
> + r1 <<= 8;
> + }
> + HELPER_LOG("\n");
> +}
> +
> +static inline uint64_t get_address(int x2, int b2, int d2)
> +{
> + uint64_t r = d2;
> +
> + if (x2) {
> + r += env->regs[x2];
> + }
> +
> + if (b2) {
> + r += env->regs[b2];
> + }
> +
> + /* 31-Bit mode */
> + if (!(env->psw.mask & PSW_MASK_64)) {
> + r &= 0x7fffffff;
> + }
> +
> + return r;
> +}
> +
> +static inline uint64_t get_address_31fix(int reg)
> +{
> + uint64_t r = env->regs[reg];
> +
> + /* 31-Bit mode */
> + if (!(env->psw.mask & PSW_MASK_64)) {
> + r &= 0x7fffffff;
> + }
> +
> + return r;
> +}
> +
> +/* search string (c is byte to search, r2 is string, r1 end of string) */
> +uint32_t HELPER(srst)(uint32_t c, uint32_t r1, uint32_t r2)
> +{
> + uint64_t i;
> + uint32_t cc = 2;
> + uint64_t str = get_address_31fix(r2);
> + uint64_t end = get_address_31fix(r1);
> +
> + HELPER_LOG("%s: c %d *r1 0x%" PRIx64 " *r2 0x%" PRIx64 "\n", __func__,
> + c, env->regs[r1], env->regs[r2]);
> +
> + for (i = str; i != end; i++) {
> + if (ldub(i) == c) {
> + env->regs[r1] = i;
> + cc = 1;
> + break;
> + }
> + }
> +
> + return cc;
> +}
> +
> +/* unsigned string compare (c is string terminator) */
> +uint32_t HELPER(clst)(uint32_t c, uint32_t r1, uint32_t r2)
> +{
> + uint64_t s1 = get_address_31fix(r1);
> + uint64_t s2 = get_address_31fix(r2);
> + uint8_t v1, v2;
> + uint32_t cc;
> +
> + c = c & 0xff;
> +#ifdef CONFIG_USER_ONLY
> + if (!c) {
> + HELPER_LOG("%s: comparing '%s' and '%s'\n",
> + __func__, (char *)g2h(s1), (char *)g2h(s2));
> + }
> +#endif
> + for (;;) {
> + v1 = ldub(s1);
> + v2 = ldub(s2);
> + if ((v1 == c || v2 == c) || (v1 != v2)) {
> + break;
> + }
> + s1++;
> + s2++;
> + }
> +
> + if (v1 == v2) {
> + cc = 0;
> + } else {
> + cc = (v1 < v2) ? 1 : 2;
> + /* FIXME: 31-bit mode! */
> + env->regs[r1] = s1;
> + env->regs[r2] = s2;
> + }
> + return cc;
> +}
> +
> +/* move page */
> +void HELPER(mvpg)(uint64_t r0, uint64_t r1, uint64_t r2)
> +{
> + /* XXX missing r0 handling */
> +#ifdef CONFIG_USER_ONLY
> + int i;
> +
> + for (i = 0; i < TARGET_PAGE_SIZE; i++) {
> + stb(r1 + i, ldub(r2 + i));
> + }
> +#else
> + mvc_fast_memmove(env, TARGET_PAGE_SIZE, r1, r2);
> +#endif
> +}
> +
> +/* string copy (c is string terminator) */
> +void HELPER(mvst)(uint32_t c, uint32_t r1, uint32_t r2)
> +{
> + uint64_t dest = get_address_31fix(r1);
> + uint64_t src = get_address_31fix(r2);
> + uint8_t v;
> +
> + c = c & 0xff;
> +#ifdef CONFIG_USER_ONLY
> + if (!c) {
> + HELPER_LOG("%s: copy '%s' to 0x%lx\n", __func__, (char *)g2h(src),
> + dest);
> + }
> +#endif
> + for (;;) {
> + v = ldub(src);
> + stb(dest, v);
> + if (v == c) {
> + break;
> + }
> + src++;
> + dest++;
> + }
> + env->regs[r1] = dest; /* FIXME: 31-bit mode! */
> +}
> +
> +/* compare and swap 64-bit */
> +uint32_t HELPER(csg)(uint32_t r1, uint64_t a2, uint32_t r3)
> +{
> + /* FIXME: locking? */
> + uint32_t cc;
> + uint64_t v2 = ldq(a2);
> +
> + if (env->regs[r1] == v2) {
> + cc = 0;
> + stq(a2, env->regs[r3]);
> + } else {
> + cc = 1;
> + env->regs[r1] = v2;
> + }
> + return cc;
> +}
> +
> +/* compare double and swap 64-bit */
> +uint32_t HELPER(cdsg)(uint32_t r1, uint64_t a2, uint32_t r3)
> +{
> + /* FIXME: locking? */
> + uint32_t cc;
> + uint64_t v2_hi = ldq(a2);
> + uint64_t v2_lo = ldq(a2 + 8);
> + uint64_t v1_hi = env->regs[r1];
> + uint64_t v1_lo = env->regs[r1 + 1];
> +
> + if ((v1_hi == v2_hi) && (v1_lo == v2_lo)) {
> + cc = 0;
> + stq(a2, env->regs[r3]);
> + stq(a2 + 8, env->regs[r3 + 1]);
> + } else {
> + cc = 1;
> + env->regs[r1] = v2_hi;
> + env->regs[r1 + 1] = v2_lo;
> + }
> +
> + return cc;
> +}
> +
> +/* compare and swap 32-bit */
> +uint32_t HELPER(cs)(uint32_t r1, uint64_t a2, uint32_t r3)
> +{
> + /* FIXME: locking? */
> + uint32_t cc;
> + uint32_t v2 = ldl(a2);
> +
> + HELPER_LOG("%s: r1 %d a2 0x%lx r3 %d\n", __func__, r1, a2, r3);
> + if (((uint32_t)env->regs[r1]) == v2) {
> + cc = 0;
> + stl(a2, (uint32_t)env->regs[r3]);
> + } else {
> + cc = 1;
> + env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | v2;
> + }
> + return cc;
> +}
> +
> +static uint32_t helper_icm(uint32_t r1, uint64_t address, uint32_t mask)
> +{
> + int pos = 24; /* top of the lower half of r1 */
> + uint64_t rmask = 0xff000000ULL;
> + uint8_t val = 0;
> + int ccd = 0;
> + uint32_t cc = 0;
> +
> + while (mask) {
> + if (mask & 8) {
> + env->regs[r1] &= ~rmask;
> + val = ldub(address);
> + if ((val & 0x80) && !ccd) {
> + cc = 1;
> + }
> + ccd = 1;
> + if (val && cc == 0) {
> + cc = 2;
> + }
> + env->regs[r1] |= (uint64_t)val << pos;
> + address++;
> + }
> + mask = (mask << 1) & 0xf;
> + pos -= 8;
> + rmask >>= 8;
> + }
> +
> + return cc;
> +}
> +
> +/* execute instruction
> + this instruction executes an insn modified with the contents of r1
> + it does not change the executed instruction in memory
> + it does not change the program counter
> + in other words: tricky...
> + currently implemented by interpreting the cases it is most commonly used in
> +*/
> +uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
> +{
> + uint16_t insn = lduw_code(addr);
> +
> + HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr,
> + insn);
> + if ((insn & 0xf0ff) == 0xd000) {
> + uint32_t l, insn2, b1, b2, d1, d2;
> +
> + l = v1 & 0xff;
> + insn2 = ldl_code(addr + 2);
> + b1 = (insn2 >> 28) & 0xf;
> + b2 = (insn2 >> 12) & 0xf;
> + d1 = (insn2 >> 16) & 0xfff;
> + d2 = insn2 & 0xfff;
> + switch (insn & 0xf00) {
> + case 0x200:
> + helper_mvc(l, get_address(0, b1, d1), get_address(0, b2, d2));
> + break;
> + case 0x500:
> + cc = helper_clc(l, get_address(0, b1, d1), get_address(0, b2, d2));
> + break;
> + case 0x700:
> + cc = helper_xc(l, get_address(0, b1, d1), get_address(0, b2, d2));
> + break;
> + case 0xc00:
> + helper_tr(l, get_address(0, b1, d1), get_address(0, b2, d2));
> + break;
> + default:
> + goto abort;
> + break;
> + }
> + } else if ((insn & 0xff00) == 0x0a00) {
> + /* supervisor call */
> + HELPER_LOG("%s: svc %ld via execute\n", __func__, (insn | v1) & 0xff);
> + env->psw.addr = ret - 4;
> + env->int_svc_code = (insn | v1) & 0xff;
> + env->int_svc_ilc = 4;
> + helper_exception(EXCP_SVC);
> + } else if ((insn & 0xff00) == 0xbf00) {
> + uint32_t insn2, r1, r3, b2, d2;
> +
> + insn2 = ldl_code(addr + 2);
> + r1 = (insn2 >> 20) & 0xf;
> + r3 = (insn2 >> 16) & 0xf;
> + b2 = (insn2 >> 12) & 0xf;
> + d2 = insn2 & 0xfff;
> + cc = helper_icm(r1, get_address(0, b2, d2), r3);
> + } else {
> + abort:
> + cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n",
> + insn);
> + }
> + return cc;
> +}
> +
> +/* store character under mask high operates on the upper half of r1 */
> +void HELPER(stcmh)(uint32_t r1, uint64_t address, uint32_t mask)
> +{
> + int pos = 56; /* top of the upper half of r1 */
> +
> + while (mask) {
> + if (mask & 8) {
> + stb(address, (env->regs[r1] >> pos) & 0xff);
> + address++;
> + }
> + mask = (mask << 1) & 0xf;
> + pos -= 8;
> + }
> +}
> +
> +/* insert character under mask high; same as icm, but operates on the
> + upper half of r1 */
> +uint32_t HELPER(icmh)(uint32_t r1, uint64_t address, uint32_t mask)
> +{
> + int pos = 56; /* top of the upper half of r1 */
> + uint64_t rmask = 0xff00000000000000ULL;
> + uint8_t val = 0;
> + int ccd = 0;
> + uint32_t cc = 0;
> +
> + while (mask) {
> + if (mask & 8) {
> + env->regs[r1] &= ~rmask;
> + val = ldub(address);
> + if ((val & 0x80) && !ccd) {
> + cc = 1;
> + }
> + ccd = 1;
> + if (val && cc == 0) {
> + cc = 2;
> + }
> + env->regs[r1] |= (uint64_t)val << pos;
> + address++;
> + }
> + mask = (mask << 1) & 0xf;
> + pos -= 8;
> + rmask >>= 8;
> + }
> +
> + return cc;
> +}
> +
> +/* load access registers r1 to r3 from memory at a2 */
> +void HELPER(lam)(uint32_t r1, uint64_t a2, uint32_t r3)
> +{
> + int i;
> +
> + for (i = r1;; i = (i + 1) % 16) {
> + env->aregs[i] = ldl(a2);
> + a2 += 4;
> +
> + if (i == r3) {
> + break;
> + }
> + }
> +}
> +
> +/* store access registers r1 to r3 in memory at a2 */
> +void HELPER(stam)(uint32_t r1, uint64_t a2, uint32_t r3)
> +{
> + int i;
> +
> + for (i = r1;; i = (i + 1) % 16) {
> + stl(a2, env->aregs[i]);
> + a2 += 4;
> +
> + if (i == r3) {
> + break;
> + }
> + }
> +}
> +
> +/* move long */
> +uint32_t HELPER(mvcl)(uint32_t r1, uint32_t r2)
> +{
> + uint64_t destlen = env->regs[r1 + 1] & 0xffffff;
> + uint64_t dest = get_address_31fix(r1);
> + uint64_t srclen = env->regs[r2 + 1] & 0xffffff;
> + uint64_t src = get_address_31fix(r2);
> + uint8_t pad = src >> 24;
> + uint8_t v;
> + uint32_t cc;
> +
> + if (destlen == srclen) {
> + cc = 0;
> + } else if (destlen < srclen) {
> + cc = 1;
> + } else {
> + cc = 2;
> + }
> +
> + if (srclen > destlen) {
> + srclen = destlen;
> + }
> +
> + for (; destlen && srclen; src++, dest++, destlen--, srclen--) {
> + v = ldub(src);
> + stb(dest, v);
> + }
> +
> + for (; destlen; dest++, destlen--) {
> + stb(dest, pad);
> + }
> +
> + env->regs[r1 + 1] = destlen;
> + /* can't use srclen here, we trunc'ed it */
> + env->regs[r2 + 1] -= src - env->regs[r2];
> + env->regs[r1] = dest;
> + env->regs[r2] = src;
> +
> + return cc;
> +}
> +
> +/* move long extended another memcopy insn with more bells and whistles */
> +uint32_t HELPER(mvcle)(uint32_t r1, uint64_t a2, uint32_t r3)
> +{
> + uint64_t destlen = env->regs[r1 + 1];
> + uint64_t dest = env->regs[r1];
> + uint64_t srclen = env->regs[r3 + 1];
> + uint64_t src = env->regs[r3];
> + uint8_t pad = a2 & 0xff;
> + uint8_t v;
> + uint32_t cc;
> +
> + if (!(env->psw.mask & PSW_MASK_64)) {
> + destlen = (uint32_t)destlen;
> + srclen = (uint32_t)srclen;
> + dest &= 0x7fffffff;
> + src &= 0x7fffffff;
> + }
> +
> + if (destlen == srclen) {
> + cc = 0;
> + } else if (destlen < srclen) {
> + cc = 1;
> + } else {
> + cc = 2;
> + }
> +
> + if (srclen > destlen) {
> + srclen = destlen;
> + }
> +
> + for (; destlen && srclen; src++, dest++, destlen--, srclen--) {
> + v = ldub(src);
> + stb(dest, v);
> + }
> +
> + for (; destlen; dest++, destlen--) {
> + stb(dest, pad);
> + }
> +
> + env->regs[r1 + 1] = destlen;
> + /* can't use srclen here, we trunc'ed it */
> + /* FIXME: 31-bit mode! */
> + env->regs[r3 + 1] -= src - env->regs[r3];
> + env->regs[r1] = dest;
> + env->regs[r3] = src;
> +
> + return cc;
> +}
> +
> +/* compare logical long extended memcompare insn with padding */
> +uint32_t HELPER(clcle)(uint32_t r1, uint64_t a2, uint32_t r3)
> +{
> + uint64_t destlen = env->regs[r1 + 1];
> + uint64_t dest = get_address_31fix(r1);
> + uint64_t srclen = env->regs[r3 + 1];
> + uint64_t src = get_address_31fix(r3);
> + uint8_t pad = a2 & 0xff;
> + uint8_t v1 = 0, v2 = 0;
> + uint32_t cc = 0;
> +
> + if (!(destlen || srclen)) {
> + return cc;
> + }
> +
> + if (srclen > destlen) {
> + srclen = destlen;
> + }
> +
> + for (; destlen || srclen; src++, dest++, destlen--, srclen--) {
> + v1 = srclen ? ldub(src) : pad;
> + v2 = destlen ? ldub(dest) : pad;
> + if (v1 != v2) {
> + cc = (v1 < v2) ? 1 : 2;
> + break;
> + }
> + }
> +
> + env->regs[r1 + 1] = destlen;
> + /* can't use srclen here, we trunc'ed it */
> + env->regs[r3 + 1] -= src - env->regs[r3];
> + env->regs[r1] = dest;
> + env->regs[r3] = src;
> +
> + return cc;
> +}
> +
> +/* checksum */
> +void HELPER(cksm)(uint32_t r1, uint32_t r2)
> +{
> + uint64_t src = get_address_31fix(r2);
> + uint64_t src_len = env->regs[(r2 + 1) & 15];
> + uint64_t cksm = (uint32_t)env->regs[r1];
> +
> + while (src_len >= 4) {
> + cksm += ldl(src);
> +
> + /* move to next word */
> + src_len -= 4;
> + src += 4;
> + }
> +
> + switch (src_len) {
> + case 0:
> + break;
> + case 1:
> + cksm += ldub(src) << 24;
> + break;
> + case 2:
> + cksm += lduw(src) << 16;
> + break;
> + case 3:
> + cksm += lduw(src) << 16;
> + cksm += ldub(src + 2) << 8;
> + break;
> + }
> +
> + /* indicate we've processed everything */
> + env->regs[r2] = src + src_len;
> + env->regs[(r2 + 1) & 15] = 0;
> +
> + /* store result */
> + env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
> + ((uint32_t)cksm + (cksm >> 32));
> +}
> +
> +void HELPER(unpk)(uint32_t len, uint64_t dest, uint64_t src)
> +{
> + int len_dest = len >> 4;
> + int len_src = len & 0xf;
> + uint8_t b;
> + int second_nibble = 0;
> +
> + dest += len_dest;
> + src += len_src;
> +
> + /* last byte is special, it only flips the nibbles */
> + b = ldub(src);
> + stb(dest, (b << 4) | (b >> 4));
> + src--;
> + len_src--;
> +
> + /* now pad every nibble with 0xf0 */
> +
> + while (len_dest > 0) {
> + uint8_t cur_byte = 0;
> +
> + if (len_src > 0) {
> + cur_byte = ldub(src);
> + }
> +
> + len_dest--;
> + dest--;
> +
> + /* only advance one nibble at a time */
> + if (second_nibble) {
> + cur_byte >>= 4;
> + len_src--;
> + src--;
> + }
> + second_nibble = !second_nibble;
> +
> + /* digit */
> + cur_byte = (cur_byte & 0xf);
> + /* zone bits */
> + cur_byte |= 0xf0;
> +
> + stb(dest, cur_byte);
> + }
> +}
> +
> +void HELPER(tr)(uint32_t len, uint64_t array, uint64_t trans)
> +{
> + int i;
> +
> + for (i = 0; i <= len; i++) {
> + uint8_t byte = ldub(array + i);
> + uint8_t new_byte = ldub(trans + byte);
> +
> + stb(array + i, new_byte);
> + }
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +void HELPER(lctlg)(uint32_t r1, uint64_t a2, uint32_t r3)
> +{
> + int i;
> + uint64_t src = a2;
> +
> + for (i = r1;; i = (i + 1) % 16) {
> + env->cregs[i] = ldq(src);
> + HELPER_LOG("load ctl %d from 0x%" PRIx64 " == 0x%" PRIx64 "\n",
> + i, src, env->cregs[i]);
> + src += sizeof(uint64_t);
> +
> + if (i == r3) {
> + break;
> + }
> + }
> +
> + tlb_flush(env, 1);
> +}
> +
> +void HELPER(lctl)(uint32_t r1, uint64_t a2, uint32_t r3)
> +{
> + int i;
> + uint64_t src = a2;
> +
> + for (i = r1;; i = (i + 1) % 16) {
> + env->cregs[i] = (env->cregs[i] & 0xFFFFFFFF00000000ULL) | ldl(src);
> + src += sizeof(uint32_t);
> +
> + if (i == r3) {
> + break;
> + }
> + }
> +
> + tlb_flush(env, 1);
> +}
> +
> +void HELPER(stctg)(uint32_t r1, uint64_t a2, uint32_t r3)
> +{
> + int i;
> + uint64_t dest = a2;
> +
> + for (i = r1;; i = (i + 1) % 16) {
> + stq(dest, env->cregs[i]);
> + dest += sizeof(uint64_t);
> +
> + if (i == r3) {
> + break;
> + }
> + }
> +}
> +
> +void HELPER(stctl)(uint32_t r1, uint64_t a2, uint32_t r3)
> +{
> + int i;
> + uint64_t dest = a2;
> +
> + for (i = r1;; i = (i + 1) % 16) {
> + stl(dest, env->cregs[i]);
> + dest += sizeof(uint32_t);
> +
> + if (i == r3) {
> + break;
> + }
> + }
> +}
> +
> +uint32_t HELPER(tprot)(uint64_t a1, uint64_t a2)
> +{
> + /* XXX implement */
> +
> + return 0;
> +}
> +
> +/* insert storage key extended */
> +uint64_t HELPER(iske)(uint64_t r2)
> +{
> + uint64_t addr = get_address(0, 0, r2);
> +
> + if (addr > ram_size) {
> + return 0;
> + }
> +
> + return env->storage_keys[addr / TARGET_PAGE_SIZE];
> +}
> +
> +/* set storage key extended */
> +void HELPER(sske)(uint32_t r1, uint64_t r2)
> +{
> + uint64_t addr = get_address(0, 0, r2);
> +
> + if (addr > ram_size) {
> + return;
> + }
> +
> + env->storage_keys[addr / TARGET_PAGE_SIZE] = r1;
> +}
> +
> +/* reset reference bit extended */
> +uint32_t HELPER(rrbe)(uint32_t r1, uint64_t r2)
> +{
> + uint8_t re;
> + uint8_t key;
> +
> + if (r2 > ram_size) {
> + return 0;
> + }
> +
> + key = env->storage_keys[r2 / TARGET_PAGE_SIZE];
> + re = key & (SK_R | SK_C);
> + env->storage_keys[r2 / TARGET_PAGE_SIZE] = (key & ~SK_R);
> +
> + /*
> + * cc
> + *
> + * 0 Reference bit zero; change bit zero
> + * 1 Reference bit zero; change bit one
> + * 2 Reference bit one; change bit zero
> + * 3 Reference bit one; change bit one
> + */
> +
> + return re >> 1;
> +}
> +
> +/* compare and swap and purge */
> +uint32_t HELPER(csp)(uint32_t r1, uint32_t r2)
> +{
> + uint32_t cc;
> + uint32_t o1 = env->regs[r1];
> + uint64_t a2 = get_address_31fix(r2) & ~3ULL;
> + uint32_t o2 = ldl(a2);
> +
> + if (o1 == o2) {
> + stl(a2, env->regs[(r1 + 1) & 15]);
> + if (env->regs[r2] & 0x3) {
> + /* flush TLB / ALB */
> + tlb_flush(env, 1);
> + }
> + cc = 0;
> + } else {
> + env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | o2;
> + cc = 1;
> + }
> +
> + return cc;
> +}
> +
> +static uint32_t mvc_asc(int64_t l, uint64_t a1, uint64_t mode1, uint64_t a2,
> + uint64_t mode2)
> +{
> + target_ulong src, dest;
> + int flags, cc = 0, i;
> +
> + if (!l) {
> + return 0;
> + } else if (l > 256) {
> + /* max 256 */
> + l = 256;
> + cc = 3;
> + }
> +
> + if (mmu_translate(env, a1 & TARGET_PAGE_MASK, 1, mode1, &dest, &flags)) {
> + cpu_loop_exit(env);
> + }
> + dest |= a1 & ~TARGET_PAGE_MASK;
> +
> + if (mmu_translate(env, a2 & TARGET_PAGE_MASK, 0, mode2, &src, &flags)) {
> + cpu_loop_exit(env);
> + }
> + src |= a2 & ~TARGET_PAGE_MASK;
> +
> + /* XXX replace w/ memcpy */
> + for (i = 0; i < l; i++) {
> + /* XXX be more clever */
> + if ((((dest + i) & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) ||
> + (((src + i) & TARGET_PAGE_MASK) != (src & TARGET_PAGE_MASK))) {
> + mvc_asc(l - i, a1 + i, mode1, a2 + i, mode2);
> + break;
> + }
> + stb_phys(dest + i, ldub_phys(src + i));
> + }
> +
> + return cc;
> +}
> +
> +uint32_t HELPER(mvcs)(uint64_t l, uint64_t a1, uint64_t a2)
> +{
> + HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
> + __func__, l, a1, a2);
> +
> + return mvc_asc(l, a1, PSW_ASC_SECONDARY, a2, PSW_ASC_PRIMARY);
> +}
> +
> +uint32_t HELPER(mvcp)(uint64_t l, uint64_t a1, uint64_t a2)
> +{
> + HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
> + __func__, l, a1, a2);
> +
> + return mvc_asc(l, a1, PSW_ASC_PRIMARY, a2, PSW_ASC_SECONDARY);
> +}
> +
> +/* invalidate pte */
> +void HELPER(ipte)(uint64_t pte_addr, uint64_t vaddr)
> +{
> + uint64_t page = vaddr & TARGET_PAGE_MASK;
> + uint64_t pte = 0;
> +
> + /* XXX broadcast to other CPUs */
> +
> + /* XXX Linux is nice enough to give us the exact pte address.
> + According to spec we'd have to find it out ourselves */
> + /* XXX Linux is fine with overwriting the pte, the spec requires
> + us to only set the invalid bit */
> + stq_phys(pte_addr, pte | _PAGE_INVALID);
> +
> + /* XXX we exploit the fact that Linux passes the exact virtual
> + address here - it's not obliged to! */
> + tlb_flush_page(env, page);
> +
> + /* XXX 31-bit hack */
> + if (page & 0x80000000) {
> + tlb_flush_page(env, page & ~0x80000000);
> + } else {
> + tlb_flush_page(env, page | 0x80000000);
> + }
> +}
> +
> +/* flush local tlb */
> +void HELPER(ptlb)(void)
> +{
> + tlb_flush(env, 1);
> +}
> +
> +/* store using real address */
> +void HELPER(stura)(uint64_t addr, uint32_t v1)
> +{
> + stw_phys(get_address(0, 0, addr), v1);
> +}
> +
> +/* load real address */
> +uint32_t HELPER(lra)(uint64_t addr, uint32_t r1)
> +{
> + uint32_t cc = 0;
> + int old_exc = env->exception_index;
> + uint64_t asc = env->psw.mask & PSW_MASK_ASC;
> + uint64_t ret;
> + int flags;
> +
> + /* XXX incomplete - has more corner cases */
> + if (!(env->psw.mask & PSW_MASK_64) && (addr >> 32)) {
> + program_interrupt(env, PGM_SPECIAL_OP, 2);
> + }
> +
> + env->exception_index = old_exc;
> + if (mmu_translate(env, addr, 0, asc, &ret, &flags)) {
> + cc = 3;
> + }
> + if (env->exception_index == EXCP_PGM) {
> + ret = env->int_pgm_code | 0x80000000;
> + } else {
> + ret |= addr & ~TARGET_PAGE_MASK;
> + }
> + env->exception_index = old_exc;
> +
> + if (!(env->psw.mask & PSW_MASK_64)) {
> + env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
> + (ret & 0xffffffffULL);
> + } else {
> + env->regs[r1] = ret;
> + }
> +
> + return cc;
> +}
> +
> +#endif
> diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
> index 3b8b997..3f8d482 100644
> --- a/target-s390x/op_helper.c
> +++ b/target-s390x/op_helper.c
> @@ -32,57 +32,11 @@
> #endif
>
> #if !defined(CONFIG_USER_ONLY)
> -#include "sysemu.h"
> +#include "softmmu_exec.h"
> #endif
>
> -/*****************************************************************************/
> -/* Softmmu support */
> #if !defined(CONFIG_USER_ONLY)
Let me fold those 2 #ifdef's together for you :).
Alex
^ permalink raw reply [flat|nested] 64+ messages in thread
* [Qemu-devel] [PATCH 06/21] target-s390x: rename op_helper.c to misc_helper.c
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (4 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 05/21] target-s390x: split memory access helpers Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 07/21] target-s390x: avoid AREG0 for FPU helpers Blue Swirl
` (15 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Now op_helper.c contains miscellaneous helpers, rename
it to misc_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
target-s390x/Makefile.objs | 6 +-
target-s390x/cpu.h | 2 +-
target-s390x/misc_helper.c | 431 ++++++++++++++++++++++++++++++++++++++++++++
target-s390x/op_helper.c | 431 --------------------------------------------
4 files changed, 435 insertions(+), 435 deletions(-)
create mode 100644 target-s390x/misc_helper.c
delete mode 100644 target-s390x/op_helper.c
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index b9b3061..a87d26f 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -1,10 +1,10 @@
-obj-y += translate.o op_helper.o helper.o cpu.o interrupt.o
-obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o
+obj-y += translate.o helper.o cpu.o interrupt.o
+obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o misc_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/int_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/fpu_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/cc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/mem_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
+$(obj)/misc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 97fde5e..0ccb551 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -1005,7 +1005,7 @@ uint32_t set_cc_f64(float64 v1, float64 v2);
uint32_t set_cc_nz_f32(float32 v);
uint32_t set_cc_nz_f64(float64 v);
-/* op_helper.c */
+/* misc_helper.c */
void program_interrupt(CPUS390XState *env, uint32_t code, int ilc);
#endif
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
new file mode 100644
index 0000000..4869674
--- /dev/null
+++ b/target-s390x/misc_helper.c
@@ -0,0 +1,431 @@
+/*
+ * S/390 misc helper routines
+ *
+ * Copyright (c) 2009 Ulrich Hecht
+ * Copyright (c) 2009 Alexander Graf
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "memory.h"
+#include "cputlb.h"
+#include "dyngen-exec.h"
+#include "host-utils.h"
+#include "helper.h"
+#include <string.h>
+#include "kvm.h"
+#include "qemu-timer.h"
+#ifdef CONFIG_KVM
+#include <linux/kvm.h>
+#endif
+
+#if !defined(CONFIG_USER_ONLY)
+#include "softmmu_exec.h"
+#endif
+
+#if !defined(CONFIG_USER_ONLY)
+#include "sysemu.h"
+#endif
+
+/* #define DEBUG_HELPER */
+#ifdef DEBUG_HELPER
+#define HELPER_LOG(x...) qemu_log(x)
+#else
+#define HELPER_LOG(x...)
+#endif
+
+/* raise an exception */
+void HELPER(exception)(uint32_t excp)
+{
+ HELPER_LOG("%s: exception %d\n", __func__, excp);
+ env->exception_index = excp;
+ cpu_loop_exit(env);
+}
+
+#ifndef CONFIG_USER_ONLY
+void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
+{
+ qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
+
+ if (kvm_enabled()) {
+#ifdef CONFIG_KVM
+ kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code);
+#endif
+ } else {
+ env->int_pgm_code = code;
+ env->int_pgm_ilc = ilc;
+ env->exception_index = EXCP_PGM;
+ cpu_loop_exit(env);
+ }
+}
+
+/*
+ * ret < 0 indicates program check, ret = 0, 1, 2, 3 -> cc
+ */
+int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
+{
+ int r = 0;
+ int shift = 0;
+
+#ifdef DEBUG_HELPER
+ printf("sclp(0x%x, 0x%" PRIx64 ")\n", sccb, code);
+#endif
+
+ /* basic checks */
+ if (!memory_region_is_ram(phys_page_find(sccb >> TARGET_PAGE_BITS)->mr)) {
+ return -PGM_ADDRESSING;
+ }
+ if (sccb & ~0x7ffffff8ul) {
+ return -PGM_SPECIFICATION;
+ }
+
+ switch (code) {
+ case SCLP_CMDW_READ_SCP_INFO:
+ case SCLP_CMDW_READ_SCP_INFO_FORCED:
+ while ((ram_size >> (20 + shift)) > 65535) {
+ shift++;
+ }
+ stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
+ stb_phys(sccb + SCP_INCREMENT, 1 << shift);
+ stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
+
+ s390_sclp_extint(sccb & ~3);
+ break;
+ default:
+#ifdef DEBUG_HELPER
+ printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
+#endif
+ r = 3;
+ break;
+ }
+
+ return r;
+}
+
+/* SCLP service call */
+uint32_t HELPER(servc)(uint32_t r1, uint64_t r2)
+{
+ int r;
+
+ r = sclp_service_call(env, r1, r2);
+ if (r < 0) {
+ program_interrupt(env, -r, 4);
+ return 0;
+ }
+ return r;
+}
+
+/* DIAG */
+uint64_t HELPER(diag)(uint32_t num, uint64_t mem, uint64_t code)
+{
+ uint64_t r;
+
+ switch (num) {
+ case 0x500:
+ /* KVM hypercall */
+ r = s390_virtio_hypercall(env, mem, code);
+ break;
+ case 0x44:
+ /* yield */
+ r = 0;
+ break;
+ case 0x308:
+ /* ipl */
+ r = 0;
+ break;
+ default:
+ r = -1;
+ break;
+ }
+
+ if (r) {
+ program_interrupt(env, PGM_OPERATION, ILC_LATER_INC);
+ }
+
+ return r;
+}
+
+/* Store CPU ID */
+void HELPER(stidp)(uint64_t a1)
+{
+ stq(a1, env->cpu_num);
+}
+
+/* Set Prefix */
+void HELPER(spx)(uint64_t a1)
+{
+ uint32_t prefix;
+
+ prefix = ldl(a1);
+ env->psa = prefix & 0xfffff000;
+ qemu_log("prefix: %#x\n", prefix);
+ tlb_flush_page(env, 0);
+ tlb_flush_page(env, TARGET_PAGE_SIZE);
+}
+
+/* Set Clock */
+uint32_t HELPER(sck)(uint64_t a1)
+{
+ /* XXX not implemented - is it necessary? */
+
+ return 0;
+}
+
+static inline uint64_t clock_value(CPUS390XState *env)
+{
+ uint64_t time;
+
+ time = env->tod_offset +
+ time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
+
+ return time;
+}
+
+/* Store Clock */
+uint32_t HELPER(stck)(uint64_t a1)
+{
+ stq(a1, clock_value(env));
+
+ return 0;
+}
+
+/* Store Clock Extended */
+uint32_t HELPER(stcke)(uint64_t a1)
+{
+ stb(a1, 0);
+ /* basically the same value as stck */
+ stq(a1 + 1, clock_value(env) | env->cpu_num);
+ /* more fine grained than stck */
+ stq(a1 + 9, 0);
+ /* XXX programmable fields */
+ stw(a1 + 17, 0);
+
+ return 0;
+}
+
+/* Set Clock Comparator */
+void HELPER(sckc)(uint64_t a1)
+{
+ uint64_t time = ldq(a1);
+
+ if (time == -1ULL) {
+ return;
+ }
+
+ /* difference between now and then */
+ time -= clock_value(env);
+ /* nanoseconds */
+ time = (time * 125) >> 9;
+
+ qemu_mod_timer(env->tod_timer, qemu_get_clock_ns(vm_clock) + time);
+}
+
+/* Store Clock Comparator */
+void HELPER(stckc)(uint64_t a1)
+{
+ /* XXX implement */
+ stq(a1, 0);
+}
+
+/* Set CPU Timer */
+void HELPER(spt)(uint64_t a1)
+{
+ uint64_t time = ldq(a1);
+
+ if (time == -1ULL) {
+ return;
+ }
+
+ /* nanoseconds */
+ time = (time * 125) >> 9;
+
+ qemu_mod_timer(env->cpu_timer, qemu_get_clock_ns(vm_clock) + time);
+}
+
+/* Store CPU Timer */
+void HELPER(stpt)(uint64_t a1)
+{
+ /* XXX implement */
+ stq(a1, 0);
+}
+
+/* Store System Information */
+uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
+{
+ int cc = 0;
+ int sel1, sel2;
+
+ if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
+ ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) {
+ /* valid function code, invalid reserved bits */
+ program_interrupt(env, PGM_SPECIFICATION, 2);
+ }
+
+ sel1 = r0 & STSI_R0_SEL1_MASK;
+ sel2 = r1 & STSI_R1_SEL2_MASK;
+
+ /* XXX: spec exception if sysib is not 4k-aligned */
+
+ switch (r0 & STSI_LEVEL_MASK) {
+ case STSI_LEVEL_1:
+ if ((sel1 == 1) && (sel2 == 1)) {
+ /* Basic Machine Configuration */
+ struct sysib_111 sysib;
+
+ memset(&sysib, 0, sizeof(sysib));
+ ebcdic_put(sysib.manuf, "QEMU ", 16);
+ /* same as machine type number in STORE CPU ID */
+ ebcdic_put(sysib.type, "QEMU", 4);
+ /* same as model number in STORE CPU ID */
+ ebcdic_put(sysib.model, "QEMU ", 16);
+ ebcdic_put(sysib.sequence, "QEMU ", 16);
+ ebcdic_put(sysib.plant, "QEMU", 4);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
+ } else if ((sel1 == 2) && (sel2 == 1)) {
+ /* Basic Machine CPU */
+ struct sysib_121 sysib;
+
+ memset(&sysib, 0, sizeof(sysib));
+ /* XXX make different for different CPUs? */
+ ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
+ ebcdic_put(sysib.plant, "QEMU", 4);
+ stw_p(&sysib.cpu_addr, env->cpu_num);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
+ } else if ((sel1 == 2) && (sel2 == 2)) {
+ /* Basic Machine CPUs */
+ struct sysib_122 sysib;
+
+ memset(&sysib, 0, sizeof(sysib));
+ stl_p(&sysib.capability, 0x443afc29);
+ /* XXX change when SMP comes */
+ stw_p(&sysib.total_cpus, 1);
+ stw_p(&sysib.active_cpus, 1);
+ stw_p(&sysib.standby_cpus, 0);
+ stw_p(&sysib.reserved_cpus, 0);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
+ } else {
+ cc = 3;
+ }
+ break;
+ case STSI_LEVEL_2:
+ {
+ if ((sel1 == 2) && (sel2 == 1)) {
+ /* LPAR CPU */
+ struct sysib_221 sysib;
+
+ memset(&sysib, 0, sizeof(sysib));
+ /* XXX make different for different CPUs? */
+ ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
+ ebcdic_put(sysib.plant, "QEMU", 4);
+ stw_p(&sysib.cpu_addr, env->cpu_num);
+ stw_p(&sysib.cpu_id, 0);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
+ } else if ((sel1 == 2) && (sel2 == 2)) {
+ /* LPAR CPUs */
+ struct sysib_222 sysib;
+
+ memset(&sysib, 0, sizeof(sysib));
+ stw_p(&sysib.lpar_num, 0);
+ sysib.lcpuc = 0;
+ /* XXX change when SMP comes */
+ stw_p(&sysib.total_cpus, 1);
+ stw_p(&sysib.conf_cpus, 1);
+ stw_p(&sysib.standby_cpus, 0);
+ stw_p(&sysib.reserved_cpus, 0);
+ ebcdic_put(sysib.name, "QEMU ", 8);
+ stl_p(&sysib.caf, 1000);
+ stw_p(&sysib.dedicated_cpus, 0);
+ stw_p(&sysib.shared_cpus, 0);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
+ } else {
+ cc = 3;
+ }
+ break;
+ }
+ case STSI_LEVEL_3:
+ {
+ if ((sel1 == 2) && (sel2 == 2)) {
+ /* VM CPUs */
+ struct sysib_322 sysib;
+
+ memset(&sysib, 0, sizeof(sysib));
+ sysib.count = 1;
+ /* XXX change when SMP comes */
+ stw_p(&sysib.vm[0].total_cpus, 1);
+ stw_p(&sysib.vm[0].conf_cpus, 1);
+ stw_p(&sysib.vm[0].standby_cpus, 0);
+ stw_p(&sysib.vm[0].reserved_cpus, 0);
+ ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
+ stl_p(&sysib.vm[0].caf, 1000);
+ ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
+ } else {
+ cc = 3;
+ }
+ break;
+ }
+ case STSI_LEVEL_CURRENT:
+ env->regs[0] = STSI_LEVEL_3;
+ break;
+ default:
+ cc = 3;
+ break;
+ }
+
+ return cc;
+}
+
+uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
+{
+ int cc = 0;
+
+ HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
+ __func__, order_code, r1, cpu_addr);
+
+ /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
+ as parameter (input). Status (output) is always R1. */
+
+ switch (order_code) {
+ case SIGP_SET_ARCH:
+ /* switch arch */
+ break;
+ case SIGP_SENSE:
+ /* enumerate CPU status */
+ if (cpu_addr) {
+ /* XXX implement when SMP comes */
+ return 3;
+ }
+ env->regs[r1] &= 0xffffffff00000000ULL;
+ cc = 1;
+ break;
+#if !defined(CONFIG_USER_ONLY)
+ case SIGP_RESTART:
+ qemu_system_reset_request();
+ cpu_loop_exit(env);
+ break;
+ case SIGP_STOP:
+ qemu_system_shutdown_request();
+ cpu_loop_exit(env);
+ break;
+#endif
+ default:
+ /* unknown sigp */
+ fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
+ cc = 3;
+ }
+
+ return cc;
+}
+#endif
diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
deleted file mode 100644
index 3f8d482..0000000
--- a/target-s390x/op_helper.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * S/390 helper routines
- *
- * Copyright (c) 2009 Ulrich Hecht
- * Copyright (c) 2009 Alexander Graf
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "cpu.h"
-#include "memory.h"
-#include "cputlb.h"
-#include "dyngen-exec.h"
-#include "host-utils.h"
-#include "helper.h"
-#include <string.h>
-#include "kvm.h"
-#include "qemu-timer.h"
-#ifdef CONFIG_KVM
-#include <linux/kvm.h>
-#endif
-
-#if !defined(CONFIG_USER_ONLY)
-#include "softmmu_exec.h"
-#endif
-
-#if !defined(CONFIG_USER_ONLY)
-#include "sysemu.h"
-#endif
-
-/* #define DEBUG_HELPER */
-#ifdef DEBUG_HELPER
-#define HELPER_LOG(x...) qemu_log(x)
-#else
-#define HELPER_LOG(x...)
-#endif
-
-/* raise an exception */
-void HELPER(exception)(uint32_t excp)
-{
- HELPER_LOG("%s: exception %d\n", __func__, excp);
- env->exception_index = excp;
- cpu_loop_exit(env);
-}
-
-#ifndef CONFIG_USER_ONLY
-void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
-{
- qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
-
- if (kvm_enabled()) {
-#ifdef CONFIG_KVM
- kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code);
-#endif
- } else {
- env->int_pgm_code = code;
- env->int_pgm_ilc = ilc;
- env->exception_index = EXCP_PGM;
- cpu_loop_exit(env);
- }
-}
-
-/*
- * ret < 0 indicates program check, ret = 0, 1, 2, 3 -> cc
- */
-int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
-{
- int r = 0;
- int shift = 0;
-
-#ifdef DEBUG_HELPER
- printf("sclp(0x%x, 0x%" PRIx64 ")\n", sccb, code);
-#endif
-
- /* basic checks */
- if (!memory_region_is_ram(phys_page_find(sccb >> TARGET_PAGE_BITS)->mr)) {
- return -PGM_ADDRESSING;
- }
- if (sccb & ~0x7ffffff8ul) {
- return -PGM_SPECIFICATION;
- }
-
- switch (code) {
- case SCLP_CMDW_READ_SCP_INFO:
- case SCLP_CMDW_READ_SCP_INFO_FORCED:
- while ((ram_size >> (20 + shift)) > 65535) {
- shift++;
- }
- stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
- stb_phys(sccb + SCP_INCREMENT, 1 << shift);
- stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
-
- s390_sclp_extint(sccb & ~3);
- break;
- default:
-#ifdef DEBUG_HELPER
- printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
-#endif
- r = 3;
- break;
- }
-
- return r;
-}
-
-/* SCLP service call */
-uint32_t HELPER(servc)(uint32_t r1, uint64_t r2)
-{
- int r;
-
- r = sclp_service_call(env, r1, r2);
- if (r < 0) {
- program_interrupt(env, -r, 4);
- return 0;
- }
- return r;
-}
-
-/* DIAG */
-uint64_t HELPER(diag)(uint32_t num, uint64_t mem, uint64_t code)
-{
- uint64_t r;
-
- switch (num) {
- case 0x500:
- /* KVM hypercall */
- r = s390_virtio_hypercall(env, mem, code);
- break;
- case 0x44:
- /* yield */
- r = 0;
- break;
- case 0x308:
- /* ipl */
- r = 0;
- break;
- default:
- r = -1;
- break;
- }
-
- if (r) {
- program_interrupt(env, PGM_OPERATION, ILC_LATER_INC);
- }
-
- return r;
-}
-
-/* Store CPU ID */
-void HELPER(stidp)(uint64_t a1)
-{
- stq(a1, env->cpu_num);
-}
-
-/* Set Prefix */
-void HELPER(spx)(uint64_t a1)
-{
- uint32_t prefix;
-
- prefix = ldl(a1);
- env->psa = prefix & 0xfffff000;
- qemu_log("prefix: %#x\n", prefix);
- tlb_flush_page(env, 0);
- tlb_flush_page(env, TARGET_PAGE_SIZE);
-}
-
-/* Set Clock */
-uint32_t HELPER(sck)(uint64_t a1)
-{
- /* XXX not implemented - is it necessary? */
-
- return 0;
-}
-
-static inline uint64_t clock_value(CPUS390XState *env)
-{
- uint64_t time;
-
- time = env->tod_offset +
- time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
-
- return time;
-}
-
-/* Store Clock */
-uint32_t HELPER(stck)(uint64_t a1)
-{
- stq(a1, clock_value(env));
-
- return 0;
-}
-
-/* Store Clock Extended */
-uint32_t HELPER(stcke)(uint64_t a1)
-{
- stb(a1, 0);
- /* basically the same value as stck */
- stq(a1 + 1, clock_value(env) | env->cpu_num);
- /* more fine grained than stck */
- stq(a1 + 9, 0);
- /* XXX programmable fields */
- stw(a1 + 17, 0);
-
- return 0;
-}
-
-/* Set Clock Comparator */
-void HELPER(sckc)(uint64_t a1)
-{
- uint64_t time = ldq(a1);
-
- if (time == -1ULL) {
- return;
- }
-
- /* difference between now and then */
- time -= clock_value(env);
- /* nanoseconds */
- time = (time * 125) >> 9;
-
- qemu_mod_timer(env->tod_timer, qemu_get_clock_ns(vm_clock) + time);
-}
-
-/* Store Clock Comparator */
-void HELPER(stckc)(uint64_t a1)
-{
- /* XXX implement */
- stq(a1, 0);
-}
-
-/* Set CPU Timer */
-void HELPER(spt)(uint64_t a1)
-{
- uint64_t time = ldq(a1);
-
- if (time == -1ULL) {
- return;
- }
-
- /* nanoseconds */
- time = (time * 125) >> 9;
-
- qemu_mod_timer(env->cpu_timer, qemu_get_clock_ns(vm_clock) + time);
-}
-
-/* Store CPU Timer */
-void HELPER(stpt)(uint64_t a1)
-{
- /* XXX implement */
- stq(a1, 0);
-}
-
-/* Store System Information */
-uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
-{
- int cc = 0;
- int sel1, sel2;
-
- if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
- ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) {
- /* valid function code, invalid reserved bits */
- program_interrupt(env, PGM_SPECIFICATION, 2);
- }
-
- sel1 = r0 & STSI_R0_SEL1_MASK;
- sel2 = r1 & STSI_R1_SEL2_MASK;
-
- /* XXX: spec exception if sysib is not 4k-aligned */
-
- switch (r0 & STSI_LEVEL_MASK) {
- case STSI_LEVEL_1:
- if ((sel1 == 1) && (sel2 == 1)) {
- /* Basic Machine Configuration */
- struct sysib_111 sysib;
-
- memset(&sysib, 0, sizeof(sysib));
- ebcdic_put(sysib.manuf, "QEMU ", 16);
- /* same as machine type number in STORE CPU ID */
- ebcdic_put(sysib.type, "QEMU", 4);
- /* same as model number in STORE CPU ID */
- ebcdic_put(sysib.model, "QEMU ", 16);
- ebcdic_put(sysib.sequence, "QEMU ", 16);
- ebcdic_put(sysib.plant, "QEMU", 4);
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
- } else if ((sel1 == 2) && (sel2 == 1)) {
- /* Basic Machine CPU */
- struct sysib_121 sysib;
-
- memset(&sysib, 0, sizeof(sysib));
- /* XXX make different for different CPUs? */
- ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
- ebcdic_put(sysib.plant, "QEMU", 4);
- stw_p(&sysib.cpu_addr, env->cpu_num);
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
- } else if ((sel1 == 2) && (sel2 == 2)) {
- /* Basic Machine CPUs */
- struct sysib_122 sysib;
-
- memset(&sysib, 0, sizeof(sysib));
- stl_p(&sysib.capability, 0x443afc29);
- /* XXX change when SMP comes */
- stw_p(&sysib.total_cpus, 1);
- stw_p(&sysib.active_cpus, 1);
- stw_p(&sysib.standby_cpus, 0);
- stw_p(&sysib.reserved_cpus, 0);
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
- } else {
- cc = 3;
- }
- break;
- case STSI_LEVEL_2:
- {
- if ((sel1 == 2) && (sel2 == 1)) {
- /* LPAR CPU */
- struct sysib_221 sysib;
-
- memset(&sysib, 0, sizeof(sysib));
- /* XXX make different for different CPUs? */
- ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
- ebcdic_put(sysib.plant, "QEMU", 4);
- stw_p(&sysib.cpu_addr, env->cpu_num);
- stw_p(&sysib.cpu_id, 0);
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
- } else if ((sel1 == 2) && (sel2 == 2)) {
- /* LPAR CPUs */
- struct sysib_222 sysib;
-
- memset(&sysib, 0, sizeof(sysib));
- stw_p(&sysib.lpar_num, 0);
- sysib.lcpuc = 0;
- /* XXX change when SMP comes */
- stw_p(&sysib.total_cpus, 1);
- stw_p(&sysib.conf_cpus, 1);
- stw_p(&sysib.standby_cpus, 0);
- stw_p(&sysib.reserved_cpus, 0);
- ebcdic_put(sysib.name, "QEMU ", 8);
- stl_p(&sysib.caf, 1000);
- stw_p(&sysib.dedicated_cpus, 0);
- stw_p(&sysib.shared_cpus, 0);
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
- } else {
- cc = 3;
- }
- break;
- }
- case STSI_LEVEL_3:
- {
- if ((sel1 == 2) && (sel2 == 2)) {
- /* VM CPUs */
- struct sysib_322 sysib;
-
- memset(&sysib, 0, sizeof(sysib));
- sysib.count = 1;
- /* XXX change when SMP comes */
- stw_p(&sysib.vm[0].total_cpus, 1);
- stw_p(&sysib.vm[0].conf_cpus, 1);
- stw_p(&sysib.vm[0].standby_cpus, 0);
- stw_p(&sysib.vm[0].reserved_cpus, 0);
- ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
- stl_p(&sysib.vm[0].caf, 1000);
- ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
- } else {
- cc = 3;
- }
- break;
- }
- case STSI_LEVEL_CURRENT:
- env->regs[0] = STSI_LEVEL_3;
- break;
- default:
- cc = 3;
- break;
- }
-
- return cc;
-}
-
-uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
-{
- int cc = 0;
-
- HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
- __func__, order_code, r1, cpu_addr);
-
- /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
- as parameter (input). Status (output) is always R1. */
-
- switch (order_code) {
- case SIGP_SET_ARCH:
- /* switch arch */
- break;
- case SIGP_SENSE:
- /* enumerate CPU status */
- if (cpu_addr) {
- /* XXX implement when SMP comes */
- return 3;
- }
- env->regs[r1] &= 0xffffffff00000000ULL;
- cc = 1;
- break;
-#if !defined(CONFIG_USER_ONLY)
- case SIGP_RESTART:
- qemu_system_reset_request();
- cpu_loop_exit(env);
- break;
- case SIGP_STOP:
- qemu_system_shutdown_request();
- cpu_loop_exit(env);
- break;
-#endif
- default:
- /* unknown sigp */
- fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
- cc = 3;
- }
-
- return cc;
-}
-#endif
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 07/21] target-s390x: avoid AREG0 for FPU helpers
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (5 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 06/21] target-s390x: rename op_helper.c to misc_helper.c Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 08/21] target-s390x: avoid AREG0 for integer helpers Blue Swirl
` (14 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Make FPU helpers take a parameter for CPUState instead
of relying on global env.
Introduce temporary wrappers for FPU load and store ops.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
target-s390x/Makefile.objs | 1 -
target-s390x/cc_helper.c | 4 +-
target-s390x/cpu.h | 14 +++-
target-s390x/fpu_helper.c | 184 +++++++++++++++++++++++---------------------
target-s390x/helper.h | 126 +++++++++++++++---------------
target-s390x/mem_helper.c | 49 ++++++++++++
target-s390x/translate.c | 70 ++++++++--------
7 files changed, 257 insertions(+), 191 deletions(-)
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index a87d26f..7d965e9 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -4,7 +4,6 @@ obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o
$(obj)/int_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
-$(obj)/fpu_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/cc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/mem_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/misc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c
index 2ac1659..9c3a2c4 100644
--- a/target-s390x/cc_helper.c
+++ b/target-s390x/cc_helper.c
@@ -473,10 +473,10 @@ static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
break;
case CC_OP_LTGT_F32:
- r = set_cc_f32(src, dst);
+ r = set_cc_f32(env, src, dst);
break;
case CC_OP_LTGT_F64:
- r = set_cc_f64(src, dst);
+ r = set_cc_f64(env, src, dst);
break;
case CC_OP_NZ_F32:
r = set_cc_nz_f32(dst);
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 0ccb551..9b7a2e3 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -1000,12 +1000,22 @@ static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
}
/* fpu_helper.c */
-uint32_t set_cc_f32(float32 v1, float32 v2);
-uint32_t set_cc_f64(float64 v1, float64 v2);
+uint32_t set_cc_f32(CPUS390XState *env, float32 v1, float32 v2);
+uint32_t set_cc_f64(CPUS390XState *env, float64 v1, float64 v2);
uint32_t set_cc_nz_f32(float32 v);
uint32_t set_cc_nz_f64(float64 v);
/* misc_helper.c */
void program_interrupt(CPUS390XState *env, uint32_t code, int ilc);
+/* temporary wrappers */
+uint32_t cpu_ldub_data(CPUS390XState *env, target_ulong ptr);
+uint32_t cpu_lduw_data(CPUS390XState *env, target_ulong ptr);
+uint32_t cpu_ldl_data(CPUS390XState *env, target_ulong ptr);
+uint64_t cpu_ldq_data(CPUS390XState *env, target_ulong ptr);
+
+void cpu_stb_data(CPUS390XState *env, target_ulong ptr, uint32_t data);
+void cpu_stw_data(CPUS390XState *env, target_ulong ptr, uint32_t data);
+void cpu_stl_data(CPUS390XState *env, target_ulong ptr, uint32_t data);
+void cpu_stq_data(CPUS390XState *env, target_ulong ptr, uint64_t data);
#endif
diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c
index 1389052..e235419 100644
--- a/target-s390x/fpu_helper.c
+++ b/target-s390x/fpu_helper.c
@@ -19,10 +19,10 @@
*/
#include "cpu.h"
-#include "dyngen-exec.h"
#include "helper.h"
-#if !defined(CONFIG_USER_ONLY)
+/* temporarily disabled due to wrapper use */
+#if 0 && !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
@@ -33,7 +33,7 @@
#define HELPER_LOG(x...)
#endif
-static inline int float_comp_to_cc(int float_compare)
+static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
{
switch (float_compare) {
case float_relation_equal:
@@ -50,14 +50,16 @@ static inline int float_comp_to_cc(int float_compare)
}
/* condition codes for binary FP ops */
-uint32_t set_cc_f32(float32 v1, float32 v2)
+uint32_t set_cc_f32(CPUS390XState *env, float32 v1, float32 v2)
{
- return float_comp_to_cc(float32_compare_quiet(v1, v2, &env->fpu_status));
+ return float_comp_to_cc(env, float32_compare_quiet(v1, v2,
+ &env->fpu_status));
}
-uint32_t set_cc_f64(float64 v1, float64 v2)
+uint32_t set_cc_f64(CPUS390XState *env, float64 v1, float64 v2)
{
- return float_comp_to_cc(float64_compare_quiet(v1, v2, &env->fpu_status));
+ return float_comp_to_cc(env, float64_compare_quiet(v1, v2,
+ &env->fpu_status));
}
/* condition codes for unary FP ops */
@@ -101,14 +103,14 @@ static uint32_t set_cc_nz_f128(float128 v)
}
/* convert 32-bit int to 64-bit float */
-void HELPER(cdfbr)(uint32_t f1, int32_t v2)
+void HELPER(cdfbr)(CPUS390XState *env, uint32_t f1, int32_t v2)
{
HELPER_LOG("%s: converting %d to f%d\n", __func__, v2, f1);
env->fregs[f1].d = int32_to_float64(v2, &env->fpu_status);
}
/* convert 32-bit int to 128-bit float */
-void HELPER(cxfbr)(uint32_t f1, int32_t v2)
+void HELPER(cxfbr)(CPUS390XState *env, uint32_t f1, int32_t v2)
{
CPU_QuadU v1;
@@ -118,21 +120,21 @@ void HELPER(cxfbr)(uint32_t f1, int32_t v2)
}
/* convert 64-bit int to 32-bit float */
-void HELPER(cegbr)(uint32_t f1, int64_t v2)
+void HELPER(cegbr)(CPUS390XState *env, uint32_t f1, int64_t v2)
{
HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
env->fregs[f1].l.upper = int64_to_float32(v2, &env->fpu_status);
}
/* convert 64-bit int to 64-bit float */
-void HELPER(cdgbr)(uint32_t f1, int64_t v2)
+void HELPER(cdgbr)(CPUS390XState *env, uint32_t f1, int64_t v2)
{
HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
env->fregs[f1].d = int64_to_float64(v2, &env->fpu_status);
}
/* convert 64-bit int to 128-bit float */
-void HELPER(cxgbr)(uint32_t f1, int64_t v2)
+void HELPER(cxgbr)(CPUS390XState *env, uint32_t f1, int64_t v2)
{
CPU_QuadU x1;
@@ -144,7 +146,7 @@ void HELPER(cxgbr)(uint32_t f1, int64_t v2)
}
/* convert 32-bit int to 32-bit float */
-void HELPER(cefbr)(uint32_t f1, int32_t v2)
+void HELPER(cefbr)(CPUS390XState *env, uint32_t f1, int32_t v2)
{
env->fregs[f1].l.upper = int32_to_float32(v2, &env->fpu_status);
HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __func__, v2,
@@ -152,7 +154,7 @@ void HELPER(cefbr)(uint32_t f1, int32_t v2)
}
/* 32-bit FP addition RR */
-uint32_t HELPER(aebr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(aebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
env->fregs[f2].l.upper,
@@ -164,7 +166,7 @@ uint32_t HELPER(aebr)(uint32_t f1, uint32_t f2)
}
/* 64-bit FP addition RR */
-uint32_t HELPER(adbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(adbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].d = float64_add(env->fregs[f1].d, env->fregs[f2].d,
&env->fpu_status);
@@ -175,7 +177,7 @@ uint32_t HELPER(adbr)(uint32_t f1, uint32_t f2)
}
/* 32-bit FP subtraction RR */
-uint32_t HELPER(sebr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(sebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].l.upper = float32_sub(env->fregs[f1].l.upper,
env->fregs[f2].l.upper,
@@ -187,7 +189,7 @@ uint32_t HELPER(sebr)(uint32_t f1, uint32_t f2)
}
/* 64-bit FP subtraction RR */
-uint32_t HELPER(sdbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(sdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].d = float64_sub(env->fregs[f1].d, env->fregs[f2].d,
&env->fpu_status);
@@ -198,7 +200,7 @@ uint32_t HELPER(sdbr)(uint32_t f1, uint32_t f2)
}
/* 32-bit FP division RR */
-void HELPER(debr)(uint32_t f1, uint32_t f2)
+void HELPER(debr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].l.upper = float32_div(env->fregs[f1].l.upper,
env->fregs[f2].l.upper,
@@ -206,7 +208,7 @@ void HELPER(debr)(uint32_t f1, uint32_t f2)
}
/* 128-bit FP division RR */
-void HELPER(dxbr)(uint32_t f1, uint32_t f2)
+void HELPER(dxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
CPU_QuadU v2;
@@ -222,14 +224,14 @@ void HELPER(dxbr)(uint32_t f1, uint32_t f2)
}
/* 64-bit FP multiplication RR */
-void HELPER(mdbr)(uint32_t f1, uint32_t f2)
+void HELPER(mdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].d = float64_mul(env->fregs[f1].d, env->fregs[f2].d,
&env->fpu_status);
}
/* 128-bit FP multiplication RR */
-void HELPER(mxbr)(uint32_t f1, uint32_t f2)
+void HELPER(mxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
CPU_QuadU v2;
@@ -245,14 +247,14 @@ void HELPER(mxbr)(uint32_t f1, uint32_t f2)
}
/* convert 32-bit float to 64-bit float */
-void HELPER(ldebr)(uint32_t r1, uint32_t r2)
+void HELPER(ldebr)(CPUS390XState *env, uint32_t r1, uint32_t r2)
{
env->fregs[r1].d = float32_to_float64(env->fregs[r2].l.upper,
&env->fpu_status);
}
/* convert 128-bit float to 64-bit float */
-void HELPER(ldxbr)(uint32_t f1, uint32_t f2)
+void HELPER(ldxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
CPU_QuadU x2;
@@ -263,7 +265,7 @@ void HELPER(ldxbr)(uint32_t f1, uint32_t f2)
}
/* convert 64-bit float to 128-bit float */
-void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
+void HELPER(lxdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
CPU_QuadU res;
@@ -273,7 +275,7 @@ void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
}
/* convert 64-bit float to 32-bit float */
-void HELPER(ledbr)(uint32_t f1, uint32_t f2)
+void HELPER(ledbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
float64 d2 = env->fregs[f2].d;
@@ -281,7 +283,7 @@ void HELPER(ledbr)(uint32_t f1, uint32_t f2)
}
/* convert 128-bit float to 32-bit float */
-void HELPER(lexbr)(uint32_t f1, uint32_t f2)
+void HELPER(lexbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
CPU_QuadU x2;
@@ -292,7 +294,7 @@ void HELPER(lexbr)(uint32_t f1, uint32_t f2)
}
/* absolute value of 32-bit float */
-uint32_t HELPER(lpebr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(lpebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
float32 v1;
float32 v2 = env->fregs[f2].d;
@@ -303,7 +305,7 @@ uint32_t HELPER(lpebr)(uint32_t f1, uint32_t f2)
}
/* absolute value of 64-bit float */
-uint32_t HELPER(lpdbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(lpdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
float64 v1;
float64 v2 = env->fregs[f2].d;
@@ -314,7 +316,7 @@ uint32_t HELPER(lpdbr)(uint32_t f1, uint32_t f2)
}
/* absolute value of 128-bit float */
-uint32_t HELPER(lpxbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(lpxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
CPU_QuadU v2;
@@ -328,21 +330,21 @@ uint32_t HELPER(lpxbr)(uint32_t f1, uint32_t f2)
}
/* load and test 64-bit float */
-uint32_t HELPER(ltdbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(ltdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].d = env->fregs[f2].d;
return set_cc_nz_f64(env->fregs[f1].d);
}
/* load and test 32-bit float */
-uint32_t HELPER(ltebr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(ltebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].l.upper = env->fregs[f2].l.upper;
return set_cc_nz_f32(env->fregs[f1].l.upper);
}
/* load and test 128-bit float */
-uint32_t HELPER(ltxbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(ltxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
CPU_QuadU x;
@@ -354,7 +356,7 @@ uint32_t HELPER(ltxbr)(uint32_t f1, uint32_t f2)
}
/* load complement of 32-bit float */
-uint32_t HELPER(lcebr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(lcebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].l.upper = float32_chs(env->fregs[f2].l.upper);
@@ -362,7 +364,7 @@ uint32_t HELPER(lcebr)(uint32_t f1, uint32_t f2)
}
/* load complement of 64-bit float */
-uint32_t HELPER(lcdbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(lcdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].d = float64_chs(env->fregs[f2].d);
@@ -370,7 +372,7 @@ uint32_t HELPER(lcdbr)(uint32_t f1, uint32_t f2)
}
/* load complement of 128-bit float */
-uint32_t HELPER(lcxbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(lcxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
CPU_QuadU x1, x2;
@@ -383,7 +385,7 @@ uint32_t HELPER(lcxbr)(uint32_t f1, uint32_t f2)
}
/* 32-bit FP addition RM */
-void HELPER(aeb)(uint32_t f1, uint32_t val)
+void HELPER(aeb)(CPUS390XState *env, uint32_t f1, uint32_t val)
{
float32 v1 = env->fregs[f1].l.upper;
CPU_FloatU v2;
@@ -395,7 +397,7 @@ void HELPER(aeb)(uint32_t f1, uint32_t val)
}
/* 32-bit FP division RM */
-void HELPER(deb)(uint32_t f1, uint32_t val)
+void HELPER(deb)(CPUS390XState *env, uint32_t f1, uint32_t val)
{
float32 v1 = env->fregs[f1].l.upper;
CPU_FloatU v2;
@@ -407,7 +409,7 @@ void HELPER(deb)(uint32_t f1, uint32_t val)
}
/* 32-bit FP multiplication RM */
-void HELPER(meeb)(uint32_t f1, uint32_t val)
+void HELPER(meeb)(CPUS390XState *env, uint32_t f1, uint32_t val)
{
float32 v1 = env->fregs[f1].l.upper;
CPU_FloatU v2;
@@ -419,29 +421,29 @@ void HELPER(meeb)(uint32_t f1, uint32_t val)
}
/* 32-bit FP compare RR */
-uint32_t HELPER(cebr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(cebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
float32 v1 = env->fregs[f1].l.upper;
float32 v2 = env->fregs[f2].l.upper;
HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __func__,
v1, f1, v2);
- return set_cc_f32(v1, v2);
+ return set_cc_f32(env, v1, v2);
}
/* 64-bit FP compare RR */
-uint32_t HELPER(cdbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(cdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
float64 v1 = env->fregs[f1].d;
float64 v2 = env->fregs[f2].d;
HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __func__,
v1, f1, v2);
- return set_cc_f64(v1, v2);
+ return set_cc_f64(env, v1, v2);
}
/* 128-bit FP compare RR */
-uint32_t HELPER(cxbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(cxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
CPU_QuadU v2;
@@ -451,29 +453,29 @@ uint32_t HELPER(cxbr)(uint32_t f1, uint32_t f2)
v2.ll.upper = env->fregs[f2].ll;
v2.ll.lower = env->fregs[f2 + 2].ll;
- return float_comp_to_cc(float128_compare_quiet(v1.q, v2.q,
+ return float_comp_to_cc(env, float128_compare_quiet(v1.q, v2.q,
&env->fpu_status));
}
/* 64-bit FP compare RM */
-uint32_t HELPER(cdb)(uint32_t f1, uint64_t a2)
+uint32_t HELPER(cdb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
{
float64 v1 = env->fregs[f1].d;
CPU_DoubleU v2;
- v2.ll = ldq(a2);
+ v2.ll = cpu_ldq_data(env, a2);
HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __func__, v1,
f1, v2.d);
- return set_cc_f64(v1, v2.d);
+ return set_cc_f64(env, v1, v2.d);
}
/* 64-bit FP addition RM */
-uint32_t HELPER(adb)(uint32_t f1, uint64_t a2)
+uint32_t HELPER(adb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
{
float64 v1 = env->fregs[f1].d;
CPU_DoubleU v2;
- v2.ll = ldq(a2);
+ v2.ll = cpu_ldq_data(env, a2);
HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __func__,
v1, f1, v2.d);
env->fregs[f1].d = v1 = float64_add(v1, v2.d, &env->fpu_status);
@@ -481,7 +483,7 @@ uint32_t HELPER(adb)(uint32_t f1, uint64_t a2)
}
/* 32-bit FP subtraction RM */
-void HELPER(seb)(uint32_t f1, uint32_t val)
+void HELPER(seb)(CPUS390XState *env, uint32_t f1, uint32_t val)
{
float32 v1 = env->fregs[f1].l.upper;
CPU_FloatU v2;
@@ -491,41 +493,41 @@ void HELPER(seb)(uint32_t f1, uint32_t val)
}
/* 64-bit FP subtraction RM */
-uint32_t HELPER(sdb)(uint32_t f1, uint64_t a2)
+uint32_t HELPER(sdb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
{
float64 v1 = env->fregs[f1].d;
CPU_DoubleU v2;
- v2.ll = ldq(a2);
+ v2.ll = cpu_ldq_data(env, a2);
env->fregs[f1].d = v1 = float64_sub(v1, v2.d, &env->fpu_status);
return set_cc_nz_f64(v1);
}
/* 64-bit FP multiplication RM */
-void HELPER(mdb)(uint32_t f1, uint64_t a2)
+void HELPER(mdb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
{
float64 v1 = env->fregs[f1].d;
CPU_DoubleU v2;
- v2.ll = ldq(a2);
+ v2.ll = cpu_ldq_data(env, a2);
HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __func__,
v1, f1, v2.d);
env->fregs[f1].d = float64_mul(v1, v2.d, &env->fpu_status);
}
/* 64-bit FP division RM */
-void HELPER(ddb)(uint32_t f1, uint64_t a2)
+void HELPER(ddb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
{
float64 v1 = env->fregs[f1].d;
CPU_DoubleU v2;
- v2.ll = ldq(a2);
+ v2.ll = cpu_ldq_data(env, a2);
HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __func__,
v1, f1, v2.d);
env->fregs[f1].d = float64_div(v1, v2.d, &env->fpu_status);
}
-static void set_round_mode(int m3)
+static void set_round_mode(CPUS390XState *env, int m3)
{
switch (m3) {
case 0:
@@ -553,33 +555,36 @@ static void set_round_mode(int m3)
}
/* convert 32-bit float to 64-bit int */
-uint32_t HELPER(cgebr)(uint32_t r1, uint32_t f2, uint32_t m3)
+uint32_t HELPER(cgebr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
+ uint32_t m3)
{
float32 v2 = env->fregs[f2].l.upper;
- set_round_mode(m3);
+ set_round_mode(env, m3);
env->regs[r1] = float32_to_int64(v2, &env->fpu_status);
return set_cc_nz_f32(v2);
}
/* convert 64-bit float to 64-bit int */
-uint32_t HELPER(cgdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
+uint32_t HELPER(cgdbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
+ uint32_t m3)
{
float64 v2 = env->fregs[f2].d;
- set_round_mode(m3);
+ set_round_mode(env, m3);
env->regs[r1] = float64_to_int64(v2, &env->fpu_status);
return set_cc_nz_f64(v2);
}
/* convert 128-bit float to 64-bit int */
-uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
+uint32_t HELPER(cgxbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
+ uint32_t m3)
{
CPU_QuadU v2;
v2.ll.upper = env->fregs[f2].ll;
v2.ll.lower = env->fregs[f2 + 2].ll;
- set_round_mode(m3);
+ set_round_mode(env, m3);
env->regs[r1] = float128_to_int64(v2.q, &env->fpu_status);
if (float128_is_any_nan(v2.q)) {
return 3;
@@ -593,29 +598,32 @@ uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
}
/* convert 32-bit float to 32-bit int */
-uint32_t HELPER(cfebr)(uint32_t r1, uint32_t f2, uint32_t m3)
+uint32_t HELPER(cfebr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
+ uint32_t m3)
{
float32 v2 = env->fregs[f2].l.upper;
- set_round_mode(m3);
+ set_round_mode(env, m3);
env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
float32_to_int32(v2, &env->fpu_status);
return set_cc_nz_f32(v2);
}
/* convert 64-bit float to 32-bit int */
-uint32_t HELPER(cfdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
+uint32_t HELPER(cfdbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
+ uint32_t m3)
{
float64 v2 = env->fregs[f2].d;
- set_round_mode(m3);
+ set_round_mode(env, m3);
env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
float64_to_int32(v2, &env->fpu_status);
return set_cc_nz_f64(v2);
}
/* convert 128-bit float to 32-bit int */
-uint32_t HELPER(cfxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
+uint32_t HELPER(cfxbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
+ uint32_t m3)
{
CPU_QuadU v2;
@@ -627,19 +635,19 @@ uint32_t HELPER(cfxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
}
/* load 32-bit FP zero */
-void HELPER(lzer)(uint32_t f1)
+void HELPER(lzer)(CPUS390XState *env, uint32_t f1)
{
env->fregs[f1].l.upper = float32_zero;
}
/* load 64-bit FP zero */
-void HELPER(lzdr)(uint32_t f1)
+void HELPER(lzdr)(CPUS390XState *env, uint32_t f1)
{
env->fregs[f1].d = float64_zero;
}
/* load 128-bit FP zero */
-void HELPER(lzxr)(uint32_t f1)
+void HELPER(lzxr)(CPUS390XState *env, uint32_t f1)
{
CPU_QuadU x;
@@ -649,7 +657,7 @@ void HELPER(lzxr)(uint32_t f1)
}
/* 128-bit FP subtraction RR */
-uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(sxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
CPU_QuadU v2;
@@ -666,7 +674,7 @@ uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
}
/* 128-bit FP addition RR */
-uint32_t HELPER(axbr)(uint32_t f1, uint32_t f2)
+uint32_t HELPER(axbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
CPU_QuadU v1;
CPU_QuadU v2;
@@ -683,7 +691,7 @@ uint32_t HELPER(axbr)(uint32_t f1, uint32_t f2)
}
/* 32-bit FP multiplication RR */
-void HELPER(meebr)(uint32_t f1, uint32_t f2)
+void HELPER(meebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].l.upper = float32_mul(env->fregs[f1].l.upper,
env->fregs[f2].l.upper,
@@ -691,19 +699,19 @@ void HELPER(meebr)(uint32_t f1, uint32_t f2)
}
/* 64-bit FP division RR */
-void HELPER(ddbr)(uint32_t f1, uint32_t f2)
+void HELPER(ddbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].d = float64_div(env->fregs[f1].d, env->fregs[f2].d,
&env->fpu_status);
}
/* 64-bit FP multiply and add RM */
-void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
+void HELPER(madb)(CPUS390XState *env, uint32_t f1, uint64_t a2, uint32_t f3)
{
CPU_DoubleU v2;
HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __func__, f1, a2, f3);
- v2.ll = ldq(a2);
+ v2.ll = cpu_ldq_data(env, a2);
env->fregs[f1].d = float64_add(env->fregs[f1].d,
float64_mul(v2.d, env->fregs[f3].d,
&env->fpu_status),
@@ -711,7 +719,7 @@ void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
}
/* 64-bit FP multiply and add RR */
-void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
+void HELPER(madbr)(CPUS390XState *env, uint32_t f1, uint32_t f3, uint32_t f2)
{
HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
env->fregs[f1].d = float64_add(float64_mul(env->fregs[f2].d,
@@ -721,7 +729,7 @@ void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
}
/* 64-bit FP multiply and subtract RR */
-void HELPER(msdbr)(uint32_t f1, uint32_t f3, uint32_t f2)
+void HELPER(msdbr)(CPUS390XState *env, uint32_t f1, uint32_t f3, uint32_t f2)
{
HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
env->fregs[f1].d = float64_sub(float64_mul(env->fregs[f2].d,
@@ -731,7 +739,7 @@ void HELPER(msdbr)(uint32_t f1, uint32_t f3, uint32_t f2)
}
/* 32-bit FP multiply and add RR */
-void HELPER(maebr)(uint32_t f1, uint32_t f3, uint32_t f2)
+void HELPER(maebr)(CPUS390XState *env, uint32_t f1, uint32_t f3, uint32_t f2)
{
env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
float32_mul(env->fregs[f2].l.upper,
@@ -741,29 +749,29 @@ void HELPER(maebr)(uint32_t f1, uint32_t f3, uint32_t f2)
}
/* convert 32-bit float to 64-bit float */
-void HELPER(ldeb)(uint32_t f1, uint64_t a2)
+void HELPER(ldeb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
{
uint32_t v2;
- v2 = ldl(a2);
+ v2 = cpu_ldl_data(env, a2);
env->fregs[f1].d = float32_to_float64(v2,
&env->fpu_status);
}
/* convert 64-bit float to 128-bit float */
-void HELPER(lxdb)(uint32_t f1, uint64_t a2)
+void HELPER(lxdb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
{
CPU_DoubleU v2;
CPU_QuadU v1;
- v2.ll = ldq(a2);
+ v2.ll = cpu_ldq_data(env, a2);
v1.q = float64_to_float128(v2.d, &env->fpu_status);
env->fregs[f1].ll = v1.ll.upper;
env->fregs[f1 + 2].ll = v1.ll.lower;
}
/* test data class 32-bit */
-uint32_t HELPER(tceb)(uint32_t f1, uint64_t m2)
+uint32_t HELPER(tceb)(CPUS390XState *env, uint32_t f1, uint64_t m2)
{
float32 v1 = env->fregs[f1].l.upper;
int neg = float32_is_neg(v1);
@@ -785,7 +793,7 @@ uint32_t HELPER(tceb)(uint32_t f1, uint64_t m2)
}
/* test data class 64-bit */
-uint32_t HELPER(tcdb)(uint32_t f1, uint64_t m2)
+uint32_t HELPER(tcdb)(CPUS390XState *env, uint32_t f1, uint64_t m2)
{
float64 v1 = env->fregs[f1].d;
int neg = float64_is_neg(v1);
@@ -806,7 +814,7 @@ uint32_t HELPER(tcdb)(uint32_t f1, uint64_t m2)
}
/* test data class 128-bit */
-uint32_t HELPER(tcxb)(uint32_t f1, uint64_t m2)
+uint32_t HELPER(tcxb)(CPUS390XState *env, uint32_t f1, uint64_t m2)
{
CPU_QuadU v1;
uint32_t cc = 0;
@@ -830,7 +838,7 @@ uint32_t HELPER(tcxb)(uint32_t f1, uint64_t m2)
}
/* square root 64-bit RR */
-void HELPER(sqdbr)(uint32_t f1, uint32_t f2)
+void HELPER(sqdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
{
env->fregs[f1].d = float64_sqrt(env->fregs[f2].d, &env->fpu_status);
}
diff --git a/target-s390x/helper.h b/target-s390x/helper.h
index 01c8d0e..af98773 100644
--- a/target-s390x/helper.h
+++ b/target-s390x/helper.h
@@ -45,70 +45,70 @@ DEF_HELPER_3(mvcle, i32, i32, i64, i32)
DEF_HELPER_3(clcle, i32, i32, i64, i32)
DEF_HELPER_3(slb, i32, i32, i32, i32)
DEF_HELPER_4(slbg, i32, i32, i32, i64, i64)
-DEF_HELPER_2(cefbr, void, i32, s32)
-DEF_HELPER_2(cdfbr, void, i32, s32)
-DEF_HELPER_2(cxfbr, void, i32, s32)
-DEF_HELPER_2(cegbr, void, i32, s64)
-DEF_HELPER_2(cdgbr, void, i32, s64)
-DEF_HELPER_2(cxgbr, void, i32, s64)
-DEF_HELPER_2(adbr, i32, i32, i32)
-DEF_HELPER_2(aebr, i32, i32, i32)
-DEF_HELPER_2(sebr, i32, i32, i32)
-DEF_HELPER_2(sdbr, i32, i32, i32)
-DEF_HELPER_2(debr, void, i32, i32)
-DEF_HELPER_2(dxbr, void, i32, i32)
-DEF_HELPER_2(mdbr, void, i32, i32)
-DEF_HELPER_2(mxbr, void, i32, i32)
-DEF_HELPER_2(ldebr, void, i32, i32)
-DEF_HELPER_2(ldxbr, void, i32, i32)
-DEF_HELPER_2(lxdbr, void, i32, i32)
-DEF_HELPER_2(ledbr, void, i32, i32)
-DEF_HELPER_2(lexbr, void, i32, i32)
-DEF_HELPER_2(lpebr, i32, i32, i32)
-DEF_HELPER_2(lpdbr, i32, i32, i32)
-DEF_HELPER_2(lpxbr, i32, i32, i32)
-DEF_HELPER_2(ltebr, i32, i32, i32)
-DEF_HELPER_2(ltdbr, i32, i32, i32)
-DEF_HELPER_2(ltxbr, i32, i32, i32)
-DEF_HELPER_2(lcebr, i32, i32, i32)
-DEF_HELPER_2(lcdbr, i32, i32, i32)
-DEF_HELPER_2(lcxbr, i32, i32, i32)
-DEF_HELPER_2(aeb, void, i32, i32)
-DEF_HELPER_2(deb, void, i32, i32)
-DEF_HELPER_2(meeb, void, i32, i32)
-DEF_HELPER_2(cdb, i32, i32, i64)
-DEF_HELPER_2(adb, i32, i32, i64)
-DEF_HELPER_2(seb, void, i32, i32)
-DEF_HELPER_2(sdb, i32, i32, i64)
-DEF_HELPER_2(mdb, void, i32, i64)
-DEF_HELPER_2(ddb, void, i32, i64)
-DEF_HELPER_FLAGS_2(cebr, TCG_CALL_PURE, i32, i32, i32)
-DEF_HELPER_FLAGS_2(cdbr, TCG_CALL_PURE, i32, i32, i32)
-DEF_HELPER_FLAGS_2(cxbr, TCG_CALL_PURE, i32, i32, i32)
-DEF_HELPER_3(cgebr, i32, i32, i32, i32)
-DEF_HELPER_3(cgdbr, i32, i32, i32, i32)
-DEF_HELPER_3(cgxbr, i32, i32, i32, i32)
-DEF_HELPER_1(lzer, void, i32)
-DEF_HELPER_1(lzdr, void, i32)
-DEF_HELPER_1(lzxr, void, i32)
-DEF_HELPER_3(cfebr, i32, i32, i32, i32)
-DEF_HELPER_3(cfdbr, i32, i32, i32, i32)
-DEF_HELPER_3(cfxbr, i32, i32, i32, i32)
-DEF_HELPER_2(axbr, i32, i32, i32)
-DEF_HELPER_2(sxbr, i32, i32, i32)
-DEF_HELPER_2(meebr, void, i32, i32)
-DEF_HELPER_2(ddbr, void, i32, i32)
-DEF_HELPER_3(madb, void, i32, i64, i32)
-DEF_HELPER_3(maebr, void, i32, i32, i32)
-DEF_HELPER_3(madbr, void, i32, i32, i32)
-DEF_HELPER_3(msdbr, void, i32, i32, i32)
-DEF_HELPER_2(ldeb, void, i32, i64)
-DEF_HELPER_2(lxdb, void, i32, i64)
-DEF_HELPER_FLAGS_2(tceb, TCG_CALL_PURE, i32, i32, i64)
-DEF_HELPER_FLAGS_2(tcdb, TCG_CALL_PURE, i32, i32, i64)
-DEF_HELPER_FLAGS_2(tcxb, TCG_CALL_PURE, i32, i32, i64)
+DEF_HELPER_3(cefbr, void, env, i32, s32)
+DEF_HELPER_3(cdfbr, void, env, i32, s32)
+DEF_HELPER_3(cxfbr, void, env, i32, s32)
+DEF_HELPER_3(cegbr, void, env, i32, s64)
+DEF_HELPER_3(cdgbr, void, env, i32, s64)
+DEF_HELPER_3(cxgbr, void, env, i32, s64)
+DEF_HELPER_3(adbr, i32, env, i32, i32)
+DEF_HELPER_3(aebr, i32, env, i32, i32)
+DEF_HELPER_3(sebr, i32, env, i32, i32)
+DEF_HELPER_3(sdbr, i32, env, i32, i32)
+DEF_HELPER_3(debr, void, env, i32, i32)
+DEF_HELPER_3(dxbr, void, env, i32, i32)
+DEF_HELPER_3(mdbr, void, env, i32, i32)
+DEF_HELPER_3(mxbr, void, env, i32, i32)
+DEF_HELPER_3(ldebr, void, env, i32, i32)
+DEF_HELPER_3(ldxbr, void, env, i32, i32)
+DEF_HELPER_3(lxdbr, void, env, i32, i32)
+DEF_HELPER_3(ledbr, void, env, i32, i32)
+DEF_HELPER_3(lexbr, void, env, i32, i32)
+DEF_HELPER_3(lpebr, i32, env, i32, i32)
+DEF_HELPER_3(lpdbr, i32, env, i32, i32)
+DEF_HELPER_3(lpxbr, i32, env, i32, i32)
+DEF_HELPER_3(ltebr, i32, env, i32, i32)
+DEF_HELPER_3(ltdbr, i32, env, i32, i32)
+DEF_HELPER_3(ltxbr, i32, env, i32, i32)
+DEF_HELPER_3(lcebr, i32, env, i32, i32)
+DEF_HELPER_3(lcdbr, i32, env, i32, i32)
+DEF_HELPER_3(lcxbr, i32, env, i32, i32)
+DEF_HELPER_3(aeb, void, env, i32, i32)
+DEF_HELPER_3(deb, void, env, i32, i32)
+DEF_HELPER_3(meeb, void, env, i32, i32)
+DEF_HELPER_3(cdb, i32, env, i32, i64)
+DEF_HELPER_3(adb, i32, env, i32, i64)
+DEF_HELPER_3(seb, void, env, i32, i32)
+DEF_HELPER_3(sdb, i32, env, i32, i64)
+DEF_HELPER_3(mdb, void, env, i32, i64)
+DEF_HELPER_3(ddb, void, env, i32, i64)
+DEF_HELPER_FLAGS_3(cebr, TCG_CALL_PURE, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(cdbr, TCG_CALL_PURE, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(cxbr, TCG_CALL_PURE, i32, env, i32, i32)
+DEF_HELPER_4(cgebr, i32, env, i32, i32, i32)
+DEF_HELPER_4(cgdbr, i32, env, i32, i32, i32)
+DEF_HELPER_4(cgxbr, i32, env, i32, i32, i32)
+DEF_HELPER_2(lzer, void, env, i32)
+DEF_HELPER_2(lzdr, void, env, i32)
+DEF_HELPER_2(lzxr, void, env, i32)
+DEF_HELPER_4(cfebr, i32, env, i32, i32, i32)
+DEF_HELPER_4(cfdbr, i32, env, i32, i32, i32)
+DEF_HELPER_4(cfxbr, i32, env, i32, i32, i32)
+DEF_HELPER_3(axbr, i32, env, i32, i32)
+DEF_HELPER_3(sxbr, i32, env, i32, i32)
+DEF_HELPER_3(meebr, void, env, i32, i32)
+DEF_HELPER_3(ddbr, void, env, i32, i32)
+DEF_HELPER_4(madb, void, env, i32, i64, i32)
+DEF_HELPER_4(maebr, void, env, i32, i32, i32)
+DEF_HELPER_4(madbr, void, env, i32, i32, i32)
+DEF_HELPER_4(msdbr, void, env, i32, i32, i32)
+DEF_HELPER_3(ldeb, void, env, i32, i64)
+DEF_HELPER_3(lxdb, void, env, i32, i64)
+DEF_HELPER_FLAGS_3(tceb, TCG_CALL_PURE, i32, env, i32, i64)
+DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_PURE, i32, env, i32, i64)
+DEF_HELPER_FLAGS_3(tcxb, TCG_CALL_PURE, i32, env, i32, i64)
DEF_HELPER_2(flogr, i32, i32, i64)
-DEF_HELPER_2(sqdbr, void, i32, i32)
+DEF_HELPER_3(sqdbr, void, env, i32, i32)
DEF_HELPER_FLAGS_1(cvd, TCG_CALL_PURE|TCG_CALL_CONST, i64, s32)
DEF_HELPER_3(unpk, void, i32, i64, i64)
DEF_HELPER_3(tr, void, i32, i64, i64)
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index ba05e65..3f8b3ba 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -1188,3 +1188,52 @@ uint32_t HELPER(lra)(uint64_t addr, uint32_t r1)
}
#endif
+
+/* temporary wrappers */
+#if defined(CONFIG_USER_ONLY)
+#define ldub_data(addr) ldub_raw(addr)
+#define lduw_data(addr) lduw_raw(addr)
+#define ldl_data(addr) ldl_raw(addr)
+#define ldq_data(addr) ldq_raw(addr)
+
+#define stb_data(addr, data) stb_raw(addr, data)
+#define stw_data(addr, data) stw_raw(addr, data)
+#define stl_data(addr, data) stl_raw(addr, data)
+#define stq_data(addr, data) stq_raw(addr, data)
+#endif
+
+#define WRAP_LD(rettype, fn) \
+ rettype cpu_ ## fn(CPUS390XState *env1, target_ulong addr) \
+ { \
+ CPUS390XState *saved_env; \
+ rettype ret; \
+ \
+ saved_env = env; \
+ env = env1; \
+ ret = fn(addr); \
+ env = saved_env; \
+ return ret; \
+ }
+
+WRAP_LD(uint32_t, ldub_data)
+WRAP_LD(uint32_t, lduw_data)
+WRAP_LD(uint32_t, ldl_data)
+WRAP_LD(uint64_t, ldq_data)
+#undef WRAP_LD
+
+#define WRAP_ST(datatype, fn) \
+ void cpu_ ## fn(CPUS390XState *env1, target_ulong addr, datatype val) \
+ { \
+ CPUS390XState *saved_env; \
+ \
+ saved_env = env; \
+ env = env1; \
+ fn(addr, val); \
+ env = saved_env; \
+ }
+
+WRAP_ST(uint32_t, stb_data)
+WRAP_ST(uint32_t, stw_data)
+WRAP_ST(uint32_t, stl_data)
+WRAP_ST(uint64_t, stq_data)
+#undef WRAP_ST
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index c370df3..b1f2071 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -2206,11 +2206,11 @@ static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
switch (op) {
case 0x4: /* LDEB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_ldeb(tmp_r1, addr);
+ gen_helper_ldeb(cpu_env, tmp_r1, addr);
break;
case 0x5: /* LXDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_lxdb(tmp_r1, addr);
+ gen_helper_lxdb(cpu_env, tmp_r1, addr);
break;
case 0x9: /* CEB R1,D2(X2,B2) [RXE] */
tmp = tcg_temp_new_i64();
@@ -2225,7 +2225,7 @@ static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
tmp32 = tcg_temp_new_i32();
tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
tcg_gen_trunc_i64_i32(tmp32, tmp);
- gen_helper_aeb(tmp_r1, tmp32);
+ gen_helper_aeb(cpu_env, tmp_r1, tmp32);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32);
@@ -2238,7 +2238,7 @@ static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
tmp32 = tcg_temp_new_i32();
tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
tcg_gen_trunc_i64_i32(tmp32, tmp);
- gen_helper_seb(tmp_r1, tmp32);
+ gen_helper_seb(cpu_env, tmp_r1, tmp32);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32);
@@ -2251,23 +2251,23 @@ static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
tmp32 = tcg_temp_new_i32();
tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
tcg_gen_trunc_i64_i32(tmp32, tmp);
- gen_helper_deb(tmp_r1, tmp32);
+ gen_helper_deb(cpu_env, tmp_r1, tmp32);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32);
break;
case 0x10: /* TCEB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_tceb(cc_op, tmp_r1, addr);
+ gen_helper_tceb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x11: /* TCDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_tcdb(cc_op, tmp_r1, addr);
+ gen_helper_tcdb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x12: /* TCXB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_tcxb(cc_op, tmp_r1, addr);
+ gen_helper_tcxb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x17: /* MEEB R1,D2(X2,B2) [RXE] */
@@ -2275,38 +2275,38 @@ static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
tmp32 = tcg_temp_new_i32();
tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
tcg_gen_trunc_i64_i32(tmp32, tmp);
- gen_helper_meeb(tmp_r1, tmp32);
+ gen_helper_meeb(cpu_env, tmp_r1, tmp32);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32);
break;
case 0x19: /* CDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_cdb(cc_op, tmp_r1, addr);
+ gen_helper_cdb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x1a: /* ADB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_adb(cc_op, tmp_r1, addr);
+ gen_helper_adb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x1b: /* SDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_sdb(cc_op, tmp_r1, addr);
+ gen_helper_sdb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x1c: /* MDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_mdb(tmp_r1, addr);
+ gen_helper_mdb(cpu_env, tmp_r1, addr);
break;
case 0x1d: /* DDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_ddb(tmp_r1, addr);
+ gen_helper_ddb(cpu_env, tmp_r1, addr);
break;
case 0x1e: /* MADB R1,R3,D2(X2,B2) [RXF] */
/* for RXF insns, r1 is R3 and r1b is R1 */
tmp32 = tcg_const_i32(r1b);
potential_page_fault(s);
- gen_helper_madb(tmp32, addr, tmp_r1);
+ gen_helper_madb(cpu_env, tmp32, addr, tmp_r1);
tcg_temp_free_i32(tmp32);
break;
default:
@@ -3001,14 +3001,14 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
#define FP_HELPER(i) \
tmp32_1 = tcg_const_i32(r1); \
tmp32_2 = tcg_const_i32(r2); \
- gen_helper_ ## i (tmp32_1, tmp32_2); \
+ gen_helper_ ## i(cpu_env, tmp32_1, tmp32_2); \
tcg_temp_free_i32(tmp32_1); \
tcg_temp_free_i32(tmp32_2);
#define FP_HELPER_CC(i) \
tmp32_1 = tcg_const_i32(r1); \
tmp32_2 = tcg_const_i32(r2); \
- gen_helper_ ## i (cc_op, tmp32_1, tmp32_2); \
+ gen_helper_ ## i(cc_op, cpu_env, tmp32_1, tmp32_2); \
set_cc_static(s); \
tcg_temp_free_i32(tmp32_1); \
tcg_temp_free_i32(tmp32_2);
@@ -3080,13 +3080,13 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
tmp32_3 = tcg_const_i32(r1);
switch (op) {
case 0xe:
- gen_helper_maebr(tmp32_1, tmp32_3, tmp32_2);
+ gen_helper_maebr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
break;
case 0x1e:
- gen_helper_madbr(tmp32_1, tmp32_3, tmp32_2);
+ gen_helper_madbr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
break;
case 0x1f:
- gen_helper_msdbr(tmp32_1, tmp32_3, tmp32_2);
+ gen_helper_msdbr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
break;
default:
tcg_abort();
@@ -3138,17 +3138,17 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
break;
case 0x74: /* LZER R1 [RRE] */
tmp32_1 = tcg_const_i32(r1);
- gen_helper_lzer(tmp32_1);
+ gen_helper_lzer(cpu_env, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x75: /* LZDR R1 [RRE] */
tmp32_1 = tcg_const_i32(r1);
- gen_helper_lzdr(tmp32_1);
+ gen_helper_lzdr(cpu_env, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x76: /* LZXR R1 [RRE] */
tmp32_1 = tcg_const_i32(r1);
- gen_helper_lzxr(tmp32_1);
+ gen_helper_lzxr(cpu_env, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x84: /* SFPC R1 [RRE] */
@@ -3169,13 +3169,13 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
tmp32_2 = load_reg32(r2);
switch (op) {
case 0x94:
- gen_helper_cefbr(tmp32_1, tmp32_2);
+ gen_helper_cefbr(cpu_env, tmp32_1, tmp32_2);
break;
case 0x95:
- gen_helper_cdfbr(tmp32_1, tmp32_2);
+ gen_helper_cdfbr(cpu_env, tmp32_1, tmp32_2);
break;
case 0x96:
- gen_helper_cxfbr(tmp32_1, tmp32_2);
+ gen_helper_cxfbr(cpu_env, tmp32_1, tmp32_2);
break;
default:
tcg_abort();
@@ -3191,13 +3191,13 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
tmp32_3 = tcg_const_i32(m3);
switch (op) {
case 0x98:
- gen_helper_cfebr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cfebr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
break;
case 0x99:
- gen_helper_cfdbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cfdbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
break;
case 0x9a:
- gen_helper_cfxbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cfxbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
break;
default:
tcg_abort();
@@ -3213,10 +3213,10 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
tmp = load_reg(r2);
switch (op) {
case 0xa4:
- gen_helper_cegbr(tmp32_1, tmp);
+ gen_helper_cegbr(cpu_env, tmp32_1, tmp);
break;
case 0xa5:
- gen_helper_cdgbr(tmp32_1, tmp);
+ gen_helper_cdgbr(cpu_env, tmp32_1, tmp);
break;
default:
tcg_abort();
@@ -3227,7 +3227,7 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
case 0xa6: /* CXGBR R1,R2 [RRE] */
tmp32_1 = tcg_const_i32(r1);
tmp = load_reg(r2);
- gen_helper_cxgbr(tmp32_1, tmp);
+ gen_helper_cxgbr(cpu_env, tmp32_1, tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp);
break;
@@ -3235,7 +3235,7 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
tmp32_3 = tcg_const_i32(m3);
- gen_helper_cgebr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cgebr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -3245,7 +3245,7 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
tmp32_3 = tcg_const_i32(m3);
- gen_helper_cgdbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cgdbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -3255,7 +3255,7 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
tmp32_3 = tcg_const_i32(m3);
- gen_helper_cgxbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cgxbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 08/21] target-s390x: avoid AREG0 for integer helpers
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (6 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 07/21] target-s390x: avoid AREG0 for FPU helpers Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 09/21] target-s390x: avoid AREG0 for condition code helpers Blue Swirl
` (13 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Make integer helpers take a parameter for CPUState instead
of relying on global env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
target-s390x/Makefile.objs | 1 -
target-s390x/helper.h | 10 +++++-----
target-s390x/int_helper.c | 12 ++++++------
target-s390x/translate.c | 16 ++++++++--------
4 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index 7d965e9..7b2c5c1 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -3,7 +3,6 @@ obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o misc_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o
-$(obj)/int_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/cc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/mem_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/misc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-s390x/helper.h b/target-s390x/helper.h
index af98773..c03cd59 100644
--- a/target-s390x/helper.h
+++ b/target-s390x/helper.h
@@ -12,8 +12,8 @@ DEF_HELPER_FLAGS_1(set_cc_comp_s64, TCG_CALL_PURE|TCG_CALL_CONST, i32, s64)
DEF_HELPER_FLAGS_2(set_cc_icm, TCG_CALL_PURE|TCG_CALL_CONST, i32, i32, i32)
DEF_HELPER_3(clm, i32, i32, i32, i64)
DEF_HELPER_3(stcm, void, i32, i32, i64)
-DEF_HELPER_2(mlg, void, i32, i64)
-DEF_HELPER_2(dlg, void, i32, i64)
+DEF_HELPER_3(mlg, void, env, i32, i64)
+DEF_HELPER_3(dlg, void, env, i32, i64)
DEF_HELPER_FLAGS_3(set_cc_add64, TCG_CALL_PURE|TCG_CALL_CONST, i32, s64, s64, s64)
DEF_HELPER_FLAGS_3(set_cc_addu64, TCG_CALL_PURE|TCG_CALL_CONST, i32, i64, i64, i64)
DEF_HELPER_FLAGS_3(set_cc_add32, TCG_CALL_PURE|TCG_CALL_CONST, i32, s32, s32, s32)
@@ -43,8 +43,8 @@ DEF_HELPER_3(stam, void, i32, i64, i32)
DEF_HELPER_3(lam, void, i32, i64, i32)
DEF_HELPER_3(mvcle, i32, i32, i64, i32)
DEF_HELPER_3(clcle, i32, i32, i64, i32)
-DEF_HELPER_3(slb, i32, i32, i32, i32)
-DEF_HELPER_4(slbg, i32, i32, i32, i64, i64)
+DEF_HELPER_4(slb, i32, env, i32, i32, i32)
+DEF_HELPER_5(slbg, i32, env, i32, i32, i64, i64)
DEF_HELPER_3(cefbr, void, env, i32, s32)
DEF_HELPER_3(cdfbr, void, env, i32, s32)
DEF_HELPER_3(cxfbr, void, env, i32, s32)
@@ -107,7 +107,7 @@ DEF_HELPER_3(lxdb, void, env, i32, i64)
DEF_HELPER_FLAGS_3(tceb, TCG_CALL_PURE, i32, env, i32, i64)
DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_PURE, i32, env, i32, i64)
DEF_HELPER_FLAGS_3(tcxb, TCG_CALL_PURE, i32, env, i32, i64)
-DEF_HELPER_2(flogr, i32, i32, i64)
+DEF_HELPER_3(flogr, i32, env, i32, i64)
DEF_HELPER_3(sqdbr, void, env, i32, i32)
DEF_HELPER_FLAGS_1(cvd, TCG_CALL_PURE|TCG_CALL_CONST, i64, s32)
DEF_HELPER_3(unpk, void, i32, i64, i64)
diff --git a/target-s390x/int_helper.c b/target-s390x/int_helper.c
index e2eeb07..f202a7e 100644
--- a/target-s390x/int_helper.c
+++ b/target-s390x/int_helper.c
@@ -19,7 +19,6 @@
*/
#include "cpu.h"
-#include "dyngen-exec.h"
#include "host-utils.h"
#include "helper.h"
@@ -31,7 +30,7 @@
#endif
/* 64/64 -> 128 unsigned multiplication */
-void HELPER(mlg)(uint32_t r1, uint64_t v2)
+void HELPER(mlg)(CPUS390XState *env, uint32_t r1, uint64_t v2)
{
#if HOST_LONG_BITS == 64 && defined(__GNUC__)
/* assuming 64-bit hosts have __uint128_t */
@@ -46,7 +45,7 @@ void HELPER(mlg)(uint32_t r1, uint64_t v2)
}
/* 128 -> 64/64 unsigned division */
-void HELPER(dlg)(uint32_t r1, uint64_t v2)
+void HELPER(dlg)(CPUS390XState *env, uint32_t r1, uint64_t v2)
{
uint64_t divisor = v2;
@@ -129,7 +128,7 @@ uint32_t HELPER(addc_u32)(uint32_t cc, uint32_t v1, uint32_t v2)
}
/* subtract unsigned v2 from v1 with borrow */
-uint32_t HELPER(slb)(uint32_t cc, uint32_t r1, uint32_t v2)
+uint32_t HELPER(slb)(CPUS390XState *env, uint32_t cc, uint32_t r1, uint32_t v2)
{
uint32_t v1 = env->regs[r1];
uint32_t res = v1 + (~v2) + (cc >> 1);
@@ -144,7 +143,8 @@ uint32_t HELPER(slb)(uint32_t cc, uint32_t r1, uint32_t v2)
}
/* subtract unsigned v2 from v1 with borrow */
-uint32_t HELPER(slbg)(uint32_t cc, uint32_t r1, uint64_t v1, uint64_t v2)
+uint32_t HELPER(slbg)(CPUS390XState *env, uint32_t cc, uint32_t r1,
+ uint64_t v1, uint64_t v2)
{
uint64_t res = v1 + (~v2) + (cc >> 1);
@@ -158,7 +158,7 @@ uint32_t HELPER(slbg)(uint32_t cc, uint32_t r1, uint64_t v1, uint64_t v2)
}
/* find leftmost one */
-uint32_t HELPER(flogr)(uint32_t r1, uint64_t v2)
+uint32_t HELPER(flogr)(CPUS390XState *env, uint32_t r1, uint64_t v2)
{
uint64_t res = 0;
uint64_t ov2 = v2;
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index b1f2071..2a61e92 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -1803,7 +1803,7 @@ static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)
tmp2 = tcg_temp_new_i64();
tmp32_1 = tcg_const_i32(r1);
tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
- gen_helper_mlg(tmp32_1, tmp2);
+ gen_helper_mlg(cpu_env, tmp32_1, tmp2);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
break;
@@ -1811,7 +1811,7 @@ static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)
tmp2 = tcg_temp_new_i64();
tmp32_1 = tcg_const_i32(r1);
tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
- gen_helper_dlg(tmp32_1, tmp2);
+ gen_helper_dlg(cpu_env, tmp32_1, tmp2);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
break;
@@ -1837,7 +1837,7 @@ static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)
tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
/* XXX possible optimization point */
gen_op_calc_cc(s);
- gen_helper_slbg(cc_op, cc_op, tmp32_1, regs[r1], tmp2);
+ gen_helper_slbg(cc_op, cpu_env, cc_op, tmp32_1, regs[r1], tmp2);
set_cc_static(s);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
@@ -1917,7 +1917,7 @@ static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)
tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
/* XXX possible optimization point */
gen_op_calc_cc(s);
- gen_helper_slb(cc_op, cc_op, tmp32_1, tmp32_2);
+ gen_helper_slb(cc_op, cpu_env, cc_op, tmp32_1, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
@@ -3535,7 +3535,7 @@ static void disas_b9(DisasContext *s, int op, int r1, int r2)
case 0x83: /* FLOGR R1,R2 [RRE] */
tmp = load_reg(r2);
tmp32_1 = tcg_const_i32(r1);
- gen_helper_flogr(cc_op, tmp32_1, tmp);
+ gen_helper_flogr(cc_op, cpu_env, tmp32_1, tmp);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
@@ -3555,7 +3555,7 @@ static void disas_b9(DisasContext *s, int op, int r1, int r2)
case 0x87: /* DLGR R1,R2 [RRE] */
tmp32_1 = tcg_const_i32(r1);
tmp = load_reg(r2);
- gen_helper_dlg(tmp32_1, tmp);
+ gen_helper_dlg(cpu_env, tmp32_1, tmp);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
break;
@@ -3580,7 +3580,7 @@ static void disas_b9(DisasContext *s, int op, int r1, int r2)
tmp2 = load_reg(r2);
tmp32_1 = tcg_const_i32(r1);
gen_op_calc_cc(s);
- gen_helper_slbg(cc_op, cc_op, tmp32_1, tmp, tmp2);
+ gen_helper_slbg(cc_op, cpu_env, cc_op, tmp32_1, tmp, tmp2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
@@ -3647,7 +3647,7 @@ static void disas_b9(DisasContext *s, int op, int r1, int r2)
tmp32_1 = load_reg32(r2);
tmp32_2 = tcg_const_i32(r1);
gen_op_calc_cc(s);
- gen_helper_slb(cc_op, cc_op, tmp32_2, tmp32_1);
+ gen_helper_slb(cc_op, cpu_env, cc_op, tmp32_2, tmp32_1);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 09/21] target-s390x: avoid AREG0 for condition code helpers
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (7 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 08/21] target-s390x: avoid AREG0 for integer helpers Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 10/21] target-s390x: avoid AREG0 for misc helpers Blue Swirl
` (12 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Make condition code helpers take a parameter for CPUState instead
of relying on global env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
target-s390x/Makefile.objs | 1 -
target-s390x/cc_helper.c | 11 +++++------
target-s390x/helper.h | 10 +++++-----
target-s390x/translate.c | 16 ++++++++--------
4 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index 7b2c5c1..736cf33 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -3,6 +3,5 @@ obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o misc_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o
-$(obj)/cc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/mem_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/misc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c
index 9c3a2c4..19ef145 100644
--- a/target-s390x/cc_helper.c
+++ b/target-s390x/cc_helper.c
@@ -19,7 +19,6 @@
*/
#include "cpu.h"
-#include "dyngen-exec.h"
#include "helper.h"
/* #define DEBUG_HELPER */
@@ -500,14 +499,14 @@ uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
return do_calc_cc(env, cc_op, src, dst, vr);
}
-uint32_t HELPER(calc_cc)(uint32_t cc_op, uint64_t src, uint64_t dst,
- uint64_t vr)
+uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src,
+ uint64_t dst, uint64_t vr)
{
return do_calc_cc(env, cc_op, src, dst, vr);
}
/* insert psw mask and condition code into r1 */
-void HELPER(ipm)(uint32_t cc, uint32_t r1)
+void HELPER(ipm)(CPUS390XState *env, uint32_t cc, uint32_t r1)
{
uint64_t r = env->regs[r1];
@@ -519,13 +518,13 @@ void HELPER(ipm)(uint32_t cc, uint32_t r1)
}
#ifndef CONFIG_USER_ONLY
-void HELPER(load_psw)(uint64_t mask, uint64_t addr)
+void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr)
{
load_psw(env, mask, addr);
cpu_loop_exit(env);
}
-void HELPER(sacf)(uint64_t a1)
+void HELPER(sacf)(CPUS390XState *env, uint64_t a1)
{
HELPER_LOG("%s: %16" PRIx64 "\n", __func__, a1);
diff --git a/target-s390x/helper.h b/target-s390x/helper.h
index c03cd59..876b88e 100644
--- a/target-s390x/helper.h
+++ b/target-s390x/helper.h
@@ -36,7 +36,7 @@ DEF_HELPER_FLAGS_1(abs_i64, TCG_CALL_PURE|TCG_CALL_CONST, i64, s64)
DEF_HELPER_FLAGS_1(nabs_i64, TCG_CALL_PURE|TCG_CALL_CONST, s64, s64)
DEF_HELPER_3(stcmh, void, i32, i64, i32)
DEF_HELPER_3(icmh, i32, i32, i64, i32)
-DEF_HELPER_2(ipm, void, i32, i32)
+DEF_HELPER_3(ipm, void, env, i32, i32)
DEF_HELPER_FLAGS_3(addc_u32, TCG_CALL_PURE|TCG_CALL_CONST, i32, i32, i32, i32)
DEF_HELPER_FLAGS_3(set_cc_addc_u64, TCG_CALL_PURE|TCG_CALL_CONST, i32, i64, i64, i64)
DEF_HELPER_3(stam, void, i32, i64, i32)
@@ -115,7 +115,7 @@ DEF_HELPER_3(tr, void, i32, i64, i64)
DEF_HELPER_2(servc, i32, i32, i64)
DEF_HELPER_3(diag, i64, i32, i64, i64)
-DEF_HELPER_2(load_psw, void, i64, i64)
+DEF_HELPER_3(load_psw, void, env, i64, i64)
DEF_HELPER_1(program_interrupt, void, i32)
DEF_HELPER_FLAGS_1(stidp, TCG_CALL_CONST, void, i64)
DEF_HELPER_FLAGS_1(spx, TCG_CALL_CONST, void, i64)
@@ -139,14 +139,14 @@ DEF_HELPER_2(csp, i32, i32, i32)
DEF_HELPER_3(mvcs, i32, i64, i64, i64)
DEF_HELPER_3(mvcp, i32, i64, i64, i64)
DEF_HELPER_3(sigp, i32, i64, i32, i64)
-DEF_HELPER_1(sacf, void, i64)
+DEF_HELPER_2(sacf, void, env, i64)
DEF_HELPER_FLAGS_2(ipte, TCG_CALL_CONST, void, i64, i64)
DEF_HELPER_FLAGS_0(ptlb, TCG_CALL_CONST, void)
DEF_HELPER_2(lra, i32, i64, i32)
DEF_HELPER_2(stura, void, i64, i32)
DEF_HELPER_2(cksm, void, i32, i32)
-DEF_HELPER_FLAGS_4(calc_cc, TCG_CALL_PURE|TCG_CALL_CONST,
- i32, i32, i64, i64, i64)
+DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_PURE|TCG_CALL_CONST,
+ i32, env, i32, i64, i64, i64)
#include "def-helper.h"
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 2a61e92..1d87272 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -722,7 +722,7 @@ static void gen_op_calc_cc(DisasContext *s)
case CC_OP_NZ_F32:
case CC_OP_NZ_F64:
/* 1 argument */
- gen_helper_calc_cc(cc_op, local_cc_op, dummy, cc_dst, dummy);
+ gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
break;
case CC_OP_ICM:
case CC_OP_LTGT_32:
@@ -735,7 +735,7 @@ static void gen_op_calc_cc(DisasContext *s)
case CC_OP_LTGT_F64:
case CC_OP_SLAG:
/* 2 arguments */
- gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, dummy);
+ gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
break;
case CC_OP_ADD_64:
case CC_OP_ADDU_64:
@@ -746,11 +746,11 @@ static void gen_op_calc_cc(DisasContext *s)
case CC_OP_SUB_32:
case CC_OP_SUBU_32:
/* 3 arguments */
- gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, cc_vr);
+ gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
break;
case CC_OP_DYNAMIC:
/* unknown operation - assume 3 arguments and cc_op in env */
- gen_helper_calc_cc(cc_op, cc_op, cc_src, cc_dst, cc_vr);
+ gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
break;
default:
tcg_abort();
@@ -2628,7 +2628,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
case 0x22: /* IPM R1 [RRE] */
tmp32_1 = tcg_const_i32(r1);
gen_op_calc_cc(s);
- gen_helper_ipm(cc_op, tmp32_1);
+ gen_helper_ipm(cpu_env, cc_op, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x41: /* CKSM R1,R2 [RRE] */
@@ -2916,7 +2916,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_sacf(tmp);
+ gen_helper_sacf(cpu_env, tmp);
tcg_temp_free_i64(tmp);
/* addressing mode has changed, so end the block */
s->pc += ilc * 2;
@@ -2967,7 +2967,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
tcg_gen_addi_i64(tmp, tmp, 8);
tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
- gen_helper_load_psw(tmp2, tmp3);
+ gen_helper_load_psw(cpu_env, tmp2, tmp3);
/* we need to keep cc_op intact */
s->is_jmp = DISAS_JUMP;
tcg_temp_free_i64(tmp);
@@ -4527,7 +4527,7 @@ static void disas_s390_insn(DisasContext *s)
tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
tcg_gen_addi_i64(tmp, tmp, 4);
tcg_gen_qemu_ld32u(tmp3, tmp, get_mem_index(s));
- gen_helper_load_psw(tmp2, tmp3);
+ gen_helper_load_psw(cpu_env, tmp2, tmp3);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i64(tmp3);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 10/21] target-s390x: avoid AREG0 for misc helpers
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (8 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 09/21] target-s390x: avoid AREG0 for condition code helpers Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 11/21] target-s390x: switch to AREG0 free mode Blue Swirl
` (11 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Make misc helpers take a parameter for CPUState instead
of relying on global env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
target-s390x/Makefile.objs | 1 -
target-s390x/helper.h | 26 ++++++++++----------
target-s390x/mem_helper.c | 2 +-
target-s390x/misc_helper.c | 55 +++++++++++++++++++++++--------------------
target-s390x/translate.c | 32 ++++++++++++------------
5 files changed, 59 insertions(+), 57 deletions(-)
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index 736cf33..156d946 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -4,4 +4,3 @@ obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o
$(obj)/mem_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
-$(obj)/misc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-s390x/helper.h b/target-s390x/helper.h
index 876b88e..f4e0b37 100644
--- a/target-s390x/helper.h
+++ b/target-s390x/helper.h
@@ -1,6 +1,6 @@
#include "def-helper.h"
-DEF_HELPER_1(exception, void, i32)
+DEF_HELPER_2(exception, void, env, i32)
DEF_HELPER_3(nc, i32, i32, i64, i64)
DEF_HELPER_3(oc, i32, i32, i64, i64)
DEF_HELPER_3(xc, i32, i32, i64, i64)
@@ -113,20 +113,20 @@ DEF_HELPER_FLAGS_1(cvd, TCG_CALL_PURE|TCG_CALL_CONST, i64, s32)
DEF_HELPER_3(unpk, void, i32, i64, i64)
DEF_HELPER_3(tr, void, i32, i64, i64)
-DEF_HELPER_2(servc, i32, i32, i64)
-DEF_HELPER_3(diag, i64, i32, i64, i64)
+DEF_HELPER_3(servc, i32, env, i32, i64)
+DEF_HELPER_4(diag, i64, env, i32, i64, i64)
DEF_HELPER_3(load_psw, void, env, i64, i64)
DEF_HELPER_1(program_interrupt, void, i32)
-DEF_HELPER_FLAGS_1(stidp, TCG_CALL_CONST, void, i64)
-DEF_HELPER_FLAGS_1(spx, TCG_CALL_CONST, void, i64)
+DEF_HELPER_FLAGS_2(stidp, TCG_CALL_CONST, void, env, i64)
+DEF_HELPER_FLAGS_2(spx, TCG_CALL_CONST, void, env, i64)
DEF_HELPER_FLAGS_1(sck, TCG_CALL_CONST, i32, i64)
-DEF_HELPER_1(stck, i32, i64)
-DEF_HELPER_1(stcke, i32, i64)
-DEF_HELPER_FLAGS_1(sckc, TCG_CALL_CONST, void, i64)
-DEF_HELPER_FLAGS_1(stckc, TCG_CALL_CONST, void, i64)
-DEF_HELPER_FLAGS_1(spt, TCG_CALL_CONST, void, i64)
-DEF_HELPER_FLAGS_1(stpt, TCG_CALL_CONST, void, i64)
-DEF_HELPER_3(stsi, i32, i64, i32, i32)
+DEF_HELPER_2(stck, i32, env, i64)
+DEF_HELPER_2(stcke, i32, env, i64)
+DEF_HELPER_FLAGS_2(sckc, TCG_CALL_CONST, void, env, i64)
+DEF_HELPER_FLAGS_2(stckc, TCG_CALL_CONST, void, env, i64)
+DEF_HELPER_FLAGS_2(spt, TCG_CALL_CONST, void, env, i64)
+DEF_HELPER_FLAGS_2(stpt, TCG_CALL_CONST, void, env, i64)
+DEF_HELPER_4(stsi, i32, env, i64, i32, i32)
DEF_HELPER_3(lctl, void, i32, i64, i32)
DEF_HELPER_3(lctlg, void, i32, i64, i32)
DEF_HELPER_3(stctl, void, i32, i64, i32)
@@ -138,7 +138,7 @@ DEF_HELPER_FLAGS_2(rrbe, TCG_CALL_CONST, i32, i32, i64)
DEF_HELPER_2(csp, i32, i32, i32)
DEF_HELPER_3(mvcs, i32, i64, i64, i64)
DEF_HELPER_3(mvcp, i32, i64, i64, i64)
-DEF_HELPER_3(sigp, i32, i64, i32, i64)
+DEF_HELPER_4(sigp, i32, env, i64, i32, i64)
DEF_HELPER_2(sacf, void, env, i64)
DEF_HELPER_FLAGS_2(ipte, TCG_CALL_CONST, void, i64, i64)
DEF_HELPER_FLAGS_0(ptlb, TCG_CALL_CONST, void)
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 3f8b3ba..52f2602 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -595,7 +595,7 @@ uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
env->psw.addr = ret - 4;
env->int_svc_code = (insn | v1) & 0xff;
env->int_svc_ilc = 4;
- helper_exception(EXCP_SVC);
+ helper_exception(env, EXCP_SVC);
} else if ((insn & 0xff00) == 0xbf00) {
uint32_t insn2, r1, r3, b2, d2;
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index 4869674..0ba737a 100644
--- a/target-s390x/misc_helper.c
+++ b/target-s390x/misc_helper.c
@@ -21,7 +21,6 @@
#include "cpu.h"
#include "memory.h"
#include "cputlb.h"
-#include "dyngen-exec.h"
#include "host-utils.h"
#include "helper.h"
#include <string.h>
@@ -31,7 +30,8 @@
#include <linux/kvm.h>
#endif
-#if !defined(CONFIG_USER_ONLY)
+/* temporarily disabled due to wrapper use */
+#if 0 && !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
@@ -47,7 +47,7 @@
#endif
/* raise an exception */
-void HELPER(exception)(uint32_t excp)
+void HELPER(exception)(CPUS390XState *env, uint32_t excp)
{
HELPER_LOG("%s: exception %d\n", __func__, excp);
env->exception_index = excp;
@@ -115,7 +115,7 @@ int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
}
/* SCLP service call */
-uint32_t HELPER(servc)(uint32_t r1, uint64_t r2)
+uint32_t HELPER(servc)(CPUS390XState *env, uint32_t r1, uint64_t r2)
{
int r;
@@ -128,7 +128,8 @@ uint32_t HELPER(servc)(uint32_t r1, uint64_t r2)
}
/* DIAG */
-uint64_t HELPER(diag)(uint32_t num, uint64_t mem, uint64_t code)
+uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,
+ uint64_t code)
{
uint64_t r;
@@ -158,17 +159,17 @@ uint64_t HELPER(diag)(uint32_t num, uint64_t mem, uint64_t code)
}
/* Store CPU ID */
-void HELPER(stidp)(uint64_t a1)
+void HELPER(stidp)(CPUS390XState *env, uint64_t a1)
{
- stq(a1, env->cpu_num);
+ cpu_stq_data(env, a1, env->cpu_num);
}
/* Set Prefix */
-void HELPER(spx)(uint64_t a1)
+void HELPER(spx)(CPUS390XState *env, uint64_t a1)
{
uint32_t prefix;
- prefix = ldl(a1);
+ prefix = cpu_ldl_data(env, a1);
env->psa = prefix & 0xfffff000;
qemu_log("prefix: %#x\n", prefix);
tlb_flush_page(env, 0);
@@ -194,31 +195,31 @@ static inline uint64_t clock_value(CPUS390XState *env)
}
/* Store Clock */
-uint32_t HELPER(stck)(uint64_t a1)
+uint32_t HELPER(stck)(CPUS390XState *env, uint64_t a1)
{
- stq(a1, clock_value(env));
+ cpu_stq_data(env, a1, clock_value(env));
return 0;
}
/* Store Clock Extended */
-uint32_t HELPER(stcke)(uint64_t a1)
+uint32_t HELPER(stcke)(CPUS390XState *env, uint64_t a1)
{
- stb(a1, 0);
+ cpu_stb_data(env, a1, 0);
/* basically the same value as stck */
- stq(a1 + 1, clock_value(env) | env->cpu_num);
+ cpu_stq_data(env, a1 + 1, clock_value(env) | env->cpu_num);
/* more fine grained than stck */
- stq(a1 + 9, 0);
+ cpu_stq_data(env, a1 + 9, 0);
/* XXX programmable fields */
- stw(a1 + 17, 0);
+ cpu_stw_data(env, a1 + 17, 0);
return 0;
}
/* Set Clock Comparator */
-void HELPER(sckc)(uint64_t a1)
+void HELPER(sckc)(CPUS390XState *env, uint64_t a1)
{
- uint64_t time = ldq(a1);
+ uint64_t time = cpu_ldq_data(env, a1);
if (time == -1ULL) {
return;
@@ -233,16 +234,16 @@ void HELPER(sckc)(uint64_t a1)
}
/* Store Clock Comparator */
-void HELPER(stckc)(uint64_t a1)
+void HELPER(stckc)(CPUS390XState *env, uint64_t a1)
{
/* XXX implement */
- stq(a1, 0);
+ cpu_stq_data(env, a1, 0);
}
/* Set CPU Timer */
-void HELPER(spt)(uint64_t a1)
+void HELPER(spt)(CPUS390XState *env, uint64_t a1)
{
- uint64_t time = ldq(a1);
+ uint64_t time = cpu_ldq_data(env, a1);
if (time == -1ULL) {
return;
@@ -255,14 +256,15 @@ void HELPER(spt)(uint64_t a1)
}
/* Store CPU Timer */
-void HELPER(stpt)(uint64_t a1)
+void HELPER(stpt)(CPUS390XState *env, uint64_t a1)
{
/* XXX implement */
- stq(a1, 0);
+ cpu_stq_data(env, a1, 0);
}
/* Store System Information */
-uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
+uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint32_t r0,
+ uint32_t r1)
{
int cc = 0;
int sel1, sel2;
@@ -387,7 +389,8 @@ uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
return cc;
}
-uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
+uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
+ uint64_t cpu_addr)
{
int cc = 0;
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 1d87272..0c61e63 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -312,7 +312,7 @@ static inline void gen_debug(DisasContext *s)
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
update_psw_addr(s);
gen_op_calc_cc(s);
- gen_helper_exception(tmp);
+ gen_helper_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
s->is_jmp = DISAS_EXCP;
}
@@ -324,7 +324,7 @@ static void gen_illegal_opcode(DisasContext *s, int ilc)
TCGv_i32 tmp = tcg_const_i32(EXCP_SPEC);
update_psw_addr(s);
gen_op_calc_cc(s);
- gen_helper_exception(tmp);
+ gen_helper_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
s->is_jmp = DISAS_EXCP;
}
@@ -377,7 +377,7 @@ static void gen_program_exception(DisasContext *s, int ilc, int code)
/* trigger exception */
tmp = tcg_const_i32(EXCP_PGM);
- gen_helper_exception(tmp);
+ gen_helper_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
/* end TB here */
@@ -2712,7 +2712,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_stidp(tmp);
+ gen_helper_stidp(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x04: /* SCK D2(B2) [S] */
@@ -2730,7 +2730,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_stck(cc_op, tmp);
+ gen_helper_stck(cc_op, cpu_env, tmp);
set_cc_static(s);
tcg_temp_free_i64(tmp);
break;
@@ -2740,7 +2740,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_sckc(tmp);
+ gen_helper_sckc(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x07: /* STCKC D2(B2) [S] */
@@ -2749,7 +2749,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_stckc(tmp);
+ gen_helper_stckc(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x08: /* SPT D2(B2) [S] */
@@ -2758,7 +2758,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_spt(tmp);
+ gen_helper_spt(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x09: /* STPT D2(B2) [S] */
@@ -2767,7 +2767,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_stpt(tmp);
+ gen_helper_stpt(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x0a: /* SPKA D2(B2) [S] */
@@ -2793,7 +2793,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_spx(tmp);
+ gen_helper_spx(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x11: /* STPX D2(B2) [S] */
@@ -2906,7 +2906,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_stcke(cc_op, tmp);
+ gen_helper_stcke(cc_op, cpu_env, tmp);
set_cc_static(s);
tcg_temp_free_i64(tmp);
break;
@@ -2930,7 +2930,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tmp32_1 = load_reg32(0);
tmp32_2 = load_reg32(1);
potential_page_fault(s);
- gen_helper_stsi(cc_op, tmp, tmp32_1, tmp32_2);
+ gen_helper_stsi(cc_op, cpu_env, tmp, tmp32_1, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
@@ -2980,7 +2980,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
potential_page_fault(s);
tmp32_1 = load_reg32(r2);
tmp = load_reg(r1);
- gen_helper_servc(cc_op, tmp32_1, tmp);
+ gen_helper_servc(cc_op, cpu_env, tmp32_1, tmp);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp);
@@ -3926,7 +3926,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_3 = tcg_const_i32(EXCP_SVC);
tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, int_svc_code));
tcg_gen_st_i32(tmp32_2, cpu_env, offsetof(CPUS390XState, int_svc_ilc));
- gen_helper_exception(tmp32_3);
+ gen_helper_exception(cpu_env, tmp32_3);
s->is_jmp = DISAS_EXCP;
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -4543,7 +4543,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_const_i32(insn & 0xfff);
tmp2 = load_reg(2);
tmp3 = load_reg(1);
- gen_helper_diag(tmp2, tmp32_1, tmp2, tmp3);
+ gen_helper_diag(tmp2, cpu_env, tmp32_1, tmp2, tmp3);
store_reg(2, tmp2);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp2);
@@ -4777,7 +4777,7 @@ static void disas_s390_insn(DisasContext *s)
tmp2 = load_reg(r3);
tmp32_1 = tcg_const_i32(r1);
potential_page_fault(s);
- gen_helper_sigp(cc_op, tmp, tmp32_1, tmp2);
+ gen_helper_sigp(cc_op, cpu_env, tmp, tmp32_1, tmp2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 11/21] target-s390x: switch to AREG0 free mode
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (9 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 10/21] target-s390x: avoid AREG0 for misc helpers Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 12/21] target-s390x: split helper.c Blue Swirl
` (10 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Add an explicit CPUState parameter instead of relying on AREG0.
Remove temporary wrappers and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
configure | 2 +-
target-s390x/Makefile.objs | 2 -
target-s390x/cpu.h | 10 --
target-s390x/fpu_helper.c | 3 +-
target-s390x/helper.c | 6 +-
target-s390x/helper.h | 78 +++++-----
target-s390x/mem_helper.c | 338 ++++++++++++++++++++------------------------
target-s390x/misc_helper.c | 6 +-
target-s390x/translate.c | 88 ++++++------
9 files changed, 240 insertions(+), 293 deletions(-)
diff --git a/configure b/configure
index d97fd81..a88a465 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
case "$target_arch2" in
- alpha | i386 | or32 | sparc* | x86_64 | xtensa* | ppc*)
+ alpha | i386 | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
;;
esac
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index 156d946..e728abf 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -2,5 +2,3 @@ obj-y += translate.o helper.o cpu.o interrupt.o
obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o misc_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o
-
-$(obj)/mem_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 9b7a2e3..ed81af3 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -1008,14 +1008,4 @@ uint32_t set_cc_nz_f64(float64 v);
/* misc_helper.c */
void program_interrupt(CPUS390XState *env, uint32_t code, int ilc);
-/* temporary wrappers */
-uint32_t cpu_ldub_data(CPUS390XState *env, target_ulong ptr);
-uint32_t cpu_lduw_data(CPUS390XState *env, target_ulong ptr);
-uint32_t cpu_ldl_data(CPUS390XState *env, target_ulong ptr);
-uint64_t cpu_ldq_data(CPUS390XState *env, target_ulong ptr);
-
-void cpu_stb_data(CPUS390XState *env, target_ulong ptr, uint32_t data);
-void cpu_stw_data(CPUS390XState *env, target_ulong ptr, uint32_t data);
-void cpu_stl_data(CPUS390XState *env, target_ulong ptr, uint32_t data);
-void cpu_stq_data(CPUS390XState *env, target_ulong ptr, uint64_t data);
#endif
diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c
index e235419..ee9420d 100644
--- a/target-s390x/fpu_helper.c
+++ b/target-s390x/fpu_helper.c
@@ -21,8 +21,7 @@
#include "cpu.h"
#include "helper.h"
-/* temporarily disabled due to wrapper use */
-#if 0 && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index d98e6d9..a5741ec 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -499,14 +499,14 @@ static void do_program_interrupt(CPUS390XState *env)
switch (ilc) {
case ILC_LATER:
- ilc = get_ilc(ldub_code(env->psw.addr));
+ ilc = get_ilc(cpu_ldub_code(env, env->psw.addr));
break;
case ILC_LATER_INC:
- ilc = get_ilc(ldub_code(env->psw.addr));
+ ilc = get_ilc(cpu_ldub_code(env, env->psw.addr));
env->psw.addr += ilc * 2;
break;
case ILC_LATER_INC_2:
- ilc = get_ilc(ldub_code(env->psw.addr)) * 2;
+ ilc = get_ilc(cpu_ldub_code(env, env->psw.addr)) * 2;
env->psw.addr += ilc;
break;
}
diff --git a/target-s390x/helper.h b/target-s390x/helper.h
index f4e0b37..5419f37 100644
--- a/target-s390x/helper.h
+++ b/target-s390x/helper.h
@@ -1,17 +1,17 @@
#include "def-helper.h"
DEF_HELPER_2(exception, void, env, i32)
-DEF_HELPER_3(nc, i32, i32, i64, i64)
-DEF_HELPER_3(oc, i32, i32, i64, i64)
-DEF_HELPER_3(xc, i32, i32, i64, i64)
-DEF_HELPER_3(mvc, void, i32, i64, i64)
-DEF_HELPER_3(clc, i32, i32, i64, i64)
-DEF_HELPER_2(mvcl, i32, i32, i32)
+DEF_HELPER_4(nc, i32, env, i32, i64, i64)
+DEF_HELPER_4(oc, i32, env, i32, i64, i64)
+DEF_HELPER_4(xc, i32, env, i32, i64, i64)
+DEF_HELPER_4(mvc, void, env, i32, i64, i64)
+DEF_HELPER_4(clc, i32, env, i32, i64, i64)
+DEF_HELPER_3(mvcl, i32, env, i32, i32)
DEF_HELPER_FLAGS_1(set_cc_comp_s32, TCG_CALL_PURE|TCG_CALL_CONST, i32, s32)
DEF_HELPER_FLAGS_1(set_cc_comp_s64, TCG_CALL_PURE|TCG_CALL_CONST, i32, s64)
DEF_HELPER_FLAGS_2(set_cc_icm, TCG_CALL_PURE|TCG_CALL_CONST, i32, i32, i32)
-DEF_HELPER_3(clm, i32, i32, i32, i64)
-DEF_HELPER_3(stcm, void, i32, i32, i64)
+DEF_HELPER_4(clm, i32, env, i32, i32, i64)
+DEF_HELPER_4(stcm, void, env, i32, i32, i64)
DEF_HELPER_3(mlg, void, env, i32, i64)
DEF_HELPER_3(dlg, void, env, i32, i64)
DEF_HELPER_FLAGS_3(set_cc_add64, TCG_CALL_PURE|TCG_CALL_CONST, i32, s64, s64, s64)
@@ -22,27 +22,27 @@ DEF_HELPER_FLAGS_3(set_cc_sub64, TCG_CALL_PURE|TCG_CALL_CONST, i32, s64, s64, s6
DEF_HELPER_FLAGS_3(set_cc_subu64, TCG_CALL_PURE|TCG_CALL_CONST, i32, i64, i64, i64)
DEF_HELPER_FLAGS_3(set_cc_sub32, TCG_CALL_PURE|TCG_CALL_CONST, i32, s32, s32, s32)
DEF_HELPER_FLAGS_3(set_cc_subu32, TCG_CALL_PURE|TCG_CALL_CONST, i32, i32, i32, i32)
-DEF_HELPER_3(srst, i32, i32, i32, i32)
-DEF_HELPER_3(clst, i32, i32, i32, i32)
-DEF_HELPER_3(mvpg, void, i64, i64, i64)
-DEF_HELPER_3(mvst, void, i32, i32, i32)
-DEF_HELPER_3(csg, i32, i32, i64, i32)
-DEF_HELPER_3(cdsg, i32, i32, i64, i32)
-DEF_HELPER_3(cs, i32, i32, i64, i32)
-DEF_HELPER_4(ex, i32, i32, i64, i64, i64)
+DEF_HELPER_4(srst, i32, env, i32, i32, i32)
+DEF_HELPER_4(clst, i32, env, i32, i32, i32)
+DEF_HELPER_4(mvpg, void, env, i64, i64, i64)
+DEF_HELPER_4(mvst, void, env, i32, i32, i32)
+DEF_HELPER_4(csg, i32, env, i32, i64, i32)
+DEF_HELPER_4(cdsg, i32, env, i32, i64, i32)
+DEF_HELPER_4(cs, i32, env, i32, i64, i32)
+DEF_HELPER_5(ex, i32, env, i32, i64, i64, i64)
DEF_HELPER_FLAGS_1(abs_i32, TCG_CALL_PURE|TCG_CALL_CONST, i32, s32)
DEF_HELPER_FLAGS_1(nabs_i32, TCG_CALL_PURE|TCG_CALL_CONST, s32, s32)
DEF_HELPER_FLAGS_1(abs_i64, TCG_CALL_PURE|TCG_CALL_CONST, i64, s64)
DEF_HELPER_FLAGS_1(nabs_i64, TCG_CALL_PURE|TCG_CALL_CONST, s64, s64)
-DEF_HELPER_3(stcmh, void, i32, i64, i32)
-DEF_HELPER_3(icmh, i32, i32, i64, i32)
+DEF_HELPER_4(stcmh, void, env, i32, i64, i32)
+DEF_HELPER_4(icmh, i32, env, i32, i64, i32)
DEF_HELPER_3(ipm, void, env, i32, i32)
DEF_HELPER_FLAGS_3(addc_u32, TCG_CALL_PURE|TCG_CALL_CONST, i32, i32, i32, i32)
DEF_HELPER_FLAGS_3(set_cc_addc_u64, TCG_CALL_PURE|TCG_CALL_CONST, i32, i64, i64, i64)
-DEF_HELPER_3(stam, void, i32, i64, i32)
-DEF_HELPER_3(lam, void, i32, i64, i32)
-DEF_HELPER_3(mvcle, i32, i32, i64, i32)
-DEF_HELPER_3(clcle, i32, i32, i64, i32)
+DEF_HELPER_4(stam, void, env, i32, i64, i32)
+DEF_HELPER_4(lam, void, env, i32, i64, i32)
+DEF_HELPER_4(mvcle, i32, env, i32, i64, i32)
+DEF_HELPER_4(clcle, i32, env, i32, i64, i32)
DEF_HELPER_4(slb, i32, env, i32, i32, i32)
DEF_HELPER_5(slbg, i32, env, i32, i32, i64, i64)
DEF_HELPER_3(cefbr, void, env, i32, s32)
@@ -110,8 +110,8 @@ DEF_HELPER_FLAGS_3(tcxb, TCG_CALL_PURE, i32, env, i32, i64)
DEF_HELPER_3(flogr, i32, env, i32, i64)
DEF_HELPER_3(sqdbr, void, env, i32, i32)
DEF_HELPER_FLAGS_1(cvd, TCG_CALL_PURE|TCG_CALL_CONST, i64, s32)
-DEF_HELPER_3(unpk, void, i32, i64, i64)
-DEF_HELPER_3(tr, void, i32, i64, i64)
+DEF_HELPER_4(unpk, void, env, i32, i64, i64)
+DEF_HELPER_4(tr, void, env, i32, i64, i64)
DEF_HELPER_3(servc, i32, env, i32, i64)
DEF_HELPER_4(diag, i64, env, i32, i64, i64)
@@ -127,24 +127,24 @@ DEF_HELPER_FLAGS_2(stckc, TCG_CALL_CONST, void, env, i64)
DEF_HELPER_FLAGS_2(spt, TCG_CALL_CONST, void, env, i64)
DEF_HELPER_FLAGS_2(stpt, TCG_CALL_CONST, void, env, i64)
DEF_HELPER_4(stsi, i32, env, i64, i32, i32)
-DEF_HELPER_3(lctl, void, i32, i64, i32)
-DEF_HELPER_3(lctlg, void, i32, i64, i32)
-DEF_HELPER_3(stctl, void, i32, i64, i32)
-DEF_HELPER_3(stctg, void, i32, i64, i32)
+DEF_HELPER_4(lctl, void, env, i32, i64, i32)
+DEF_HELPER_4(lctlg, void, env, i32, i64, i32)
+DEF_HELPER_4(stctl, void, env, i32, i64, i32)
+DEF_HELPER_4(stctg, void, env, i32, i64, i32)
DEF_HELPER_FLAGS_2(tprot, TCG_CALL_CONST, i32, i64, i64)
-DEF_HELPER_FLAGS_1(iske, TCG_CALL_PURE|TCG_CALL_CONST, i64, i64)
-DEF_HELPER_FLAGS_2(sske, TCG_CALL_CONST, void, i32, i64)
-DEF_HELPER_FLAGS_2(rrbe, TCG_CALL_CONST, i32, i32, i64)
-DEF_HELPER_2(csp, i32, i32, i32)
-DEF_HELPER_3(mvcs, i32, i64, i64, i64)
-DEF_HELPER_3(mvcp, i32, i64, i64, i64)
+DEF_HELPER_FLAGS_2(iske, TCG_CALL_PURE|TCG_CALL_CONST, i64, env, i64)
+DEF_HELPER_FLAGS_3(sske, TCG_CALL_CONST, void, env, i32, i64)
+DEF_HELPER_FLAGS_3(rrbe, TCG_CALL_CONST, i32, env, i32, i64)
+DEF_HELPER_3(csp, i32, env, i32, i32)
+DEF_HELPER_4(mvcs, i32, env, i64, i64, i64)
+DEF_HELPER_4(mvcp, i32, env, i64, i64, i64)
DEF_HELPER_4(sigp, i32, env, i64, i32, i64)
DEF_HELPER_2(sacf, void, env, i64)
-DEF_HELPER_FLAGS_2(ipte, TCG_CALL_CONST, void, i64, i64)
-DEF_HELPER_FLAGS_0(ptlb, TCG_CALL_CONST, void)
-DEF_HELPER_2(lra, i32, i64, i32)
-DEF_HELPER_2(stura, void, i64, i32)
-DEF_HELPER_2(cksm, void, i32, i32)
+DEF_HELPER_FLAGS_3(ipte, TCG_CALL_CONST, void, env, i64, i64)
+DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_CONST, void, env)
+DEF_HELPER_3(lra, i32, env, i64, i32)
+DEF_HELPER_3(stura, void, env, i64, i32)
+DEF_HELPER_3(cksm, void, env, i32, i32)
DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_PURE|TCG_CALL_CONST,
i32, env, i32, i64, i64, i64)
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 52f2602..b21b37c 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -19,7 +19,6 @@
*/
#include "cpu.h"
-#include "dyngen-exec.h"
#include "helper.h"
/*****************************************************************************/
@@ -45,15 +44,12 @@
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUS390XState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUS390XState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
TranslationBlock *tb;
- CPUS390XState *saved_env;
int ret;
- saved_env = env;
- env = env1;
ret = cpu_s390x_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
if (likely(retaddr)) {
@@ -67,7 +63,6 @@ void tlb_fill(CPUS390XState *env1, target_ulong addr, int is_write, int mmu_idx,
}
cpu_loop_exit(env);
}
- env = saved_env;
}
#endif
@@ -90,7 +85,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
int flags;
if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
- stb(dest, byte);
+ cpu_stb_data(env, dest, byte);
cpu_abort(env, "should never reach here");
}
dest_phys |= dest & ~TARGET_PAGE_MASK;
@@ -114,13 +109,13 @@ static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
int flags;
if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
- stb(dest, 0);
+ cpu_stb_data(env, dest, 0);
cpu_abort(env, "should never reach here");
}
dest_phys |= dest & ~TARGET_PAGE_MASK;
if (mmu_translate(env, src, 0, asc, &src_phys, &flags)) {
- ldub(src);
+ cpu_ldub_data(env, src);
cpu_abort(env, "should never reach here");
}
src_phys |= src & ~TARGET_PAGE_MASK;
@@ -136,7 +131,8 @@ static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
#endif
/* and on array */
-uint32_t HELPER(nc)(uint32_t l, uint64_t dest, uint64_t src)
+uint32_t HELPER(nc)(CPUS390XState *env, uint32_t l, uint64_t dest,
+ uint64_t src)
{
int i;
unsigned char x;
@@ -145,17 +141,18 @@ uint32_t HELPER(nc)(uint32_t l, uint64_t dest, uint64_t src)
HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
__func__, l, dest, src);
for (i = 0; i <= l; i++) {
- x = ldub(dest + i) & ldub(src + i);
+ x = cpu_ldub_data(env, dest + i) & cpu_ldub_data(env, src + i);
if (x) {
cc = 1;
}
- stb(dest + i, x);
+ cpu_stb_data(env, dest + i, x);
}
return cc;
}
/* xor on array */
-uint32_t HELPER(xc)(uint32_t l, uint64_t dest, uint64_t src)
+uint32_t HELPER(xc)(CPUS390XState *env, uint32_t l, uint64_t dest,
+ uint64_t src)
{
int i;
unsigned char x;
@@ -179,17 +176,18 @@ uint32_t HELPER(xc)(uint32_t l, uint64_t dest, uint64_t src)
#endif
for (i = 0; i <= l; i++) {
- x = ldub(dest + i) ^ ldub(src + i);
+ x = cpu_ldub_data(env, dest + i) ^ cpu_ldub_data(env, src + i);
if (x) {
cc = 1;
}
- stb(dest + i, x);
+ cpu_stb_data(env, dest + i, x);
}
return cc;
}
/* or on array */
-uint32_t HELPER(oc)(uint32_t l, uint64_t dest, uint64_t src)
+uint32_t HELPER(oc)(CPUS390XState *env, uint32_t l, uint64_t dest,
+ uint64_t src)
{
int i;
unsigned char x;
@@ -198,17 +196,17 @@ uint32_t HELPER(oc)(uint32_t l, uint64_t dest, uint64_t src)
HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n",
__func__, l, dest, src);
for (i = 0; i <= l; i++) {
- x = ldub(dest + i) | ldub(src + i);
+ x = cpu_ldub_data(env, dest + i) | cpu_ldub_data(env, src + i);
if (x) {
cc = 1;
}
- stb(dest + i, x);
+ cpu_stb_data(env, dest + i, x);
}
return cc;
}
/* memmove */
-void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
+void HELPER(mvc)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src)
{
int i = 0;
int x = 0;
@@ -222,7 +220,7 @@ void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
(src & TARGET_PAGE_MASK) == ((src + l) & TARGET_PAGE_MASK) &&
(dest & TARGET_PAGE_MASK) == ((dest + l) & TARGET_PAGE_MASK)) {
if (dest == (src + 1)) {
- mvc_fast_memset(env, l + 1, dest, ldub(src));
+ mvc_fast_memset(env, l + 1, dest, cpu_ldub_data(env, src));
return;
} else if ((src & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
mvc_fast_memmove(env, l + 1, dest, src);
@@ -231,7 +229,7 @@ void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
}
#else
if (dest == (src + 1)) {
- memset(g2h(dest), ldub(src), l + 1);
+ memset(g2h(dest), cpu_ldub_data(env, src), l + 1);
return;
} else {
memmove(g2h(dest), g2h(src), l + 1);
@@ -242,19 +240,19 @@ void HELPER(mvc)(uint32_t l, uint64_t dest, uint64_t src)
/* handle the parts that fit into 8-byte loads/stores */
if (dest != (src + 1)) {
for (i = 0; i < l_64; i++) {
- stq(dest + x, ldq(src + x));
+ cpu_stq_data(env, dest + x, cpu_ldq_data(env, src + x));
x += 8;
}
}
/* slow version crossing pages with byte accesses */
for (i = x; i <= l; i++) {
- stb(dest + i, ldub(src + i));
+ cpu_stb_data(env, dest + i, cpu_ldub_data(env, src + i));
}
}
/* compare unsigned byte arrays */
-uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
+uint32_t HELPER(clc)(CPUS390XState *env, uint32_t l, uint64_t s1, uint64_t s2)
{
int i;
unsigned char x, y;
@@ -263,8 +261,8 @@ uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
HELPER_LOG("%s l %d s1 %" PRIx64 " s2 %" PRIx64 "\n",
__func__, l, s1, s2);
for (i = 0; i <= l; i++) {
- x = ldub(s1 + i);
- y = ldub(s2 + i);
+ x = cpu_ldub_data(env, s1 + i);
+ y = cpu_ldub_data(env, s2 + i);
HELPER_LOG("%02x (%c)/%02x (%c) ", x, x, y, y);
if (x < y) {
cc = 1;
@@ -281,7 +279,8 @@ uint32_t HELPER(clc)(uint32_t l, uint64_t s1, uint64_t s2)
}
/* compare logical under mask */
-uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
+uint32_t HELPER(clm)(CPUS390XState *env, uint32_t r1, uint32_t mask,
+ uint64_t addr)
{
uint8_t r, d;
uint32_t cc;
@@ -291,7 +290,7 @@ uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
cc = 0;
while (mask) {
if (mask & 8) {
- d = ldub(addr);
+ d = cpu_ldub_data(env, addr);
r = (r1 & 0xff000000UL) >> 24;
HELPER_LOG("mask 0x%x %02x/%02x (0x%" PRIx64 ") ", mask, r, d,
addr);
@@ -312,7 +311,8 @@ uint32_t HELPER(clm)(uint32_t r1, uint32_t mask, uint64_t addr)
}
/* store character under mask */
-void HELPER(stcm)(uint32_t r1, uint32_t mask, uint64_t addr)
+void HELPER(stcm)(CPUS390XState *env, uint32_t r1, uint32_t mask,
+ uint64_t addr)
{
uint8_t r;
@@ -321,7 +321,7 @@ void HELPER(stcm)(uint32_t r1, uint32_t mask, uint64_t addr)
while (mask) {
if (mask & 8) {
r = (r1 & 0xff000000UL) >> 24;
- stb(addr, r);
+ cpu_stb_data(env, addr, r);
HELPER_LOG("mask 0x%x %02x (0x%lx) ", mask, r, addr);
addr++;
}
@@ -331,7 +331,7 @@ void HELPER(stcm)(uint32_t r1, uint32_t mask, uint64_t addr)
HELPER_LOG("\n");
}
-static inline uint64_t get_address(int x2, int b2, int d2)
+static inline uint64_t get_address(CPUS390XState *env, int x2, int b2, int d2)
{
uint64_t r = d2;
@@ -351,7 +351,7 @@ static inline uint64_t get_address(int x2, int b2, int d2)
return r;
}
-static inline uint64_t get_address_31fix(int reg)
+static inline uint64_t get_address_31fix(CPUS390XState *env, int reg)
{
uint64_t r = env->regs[reg];
@@ -364,18 +364,18 @@ static inline uint64_t get_address_31fix(int reg)
}
/* search string (c is byte to search, r2 is string, r1 end of string) */
-uint32_t HELPER(srst)(uint32_t c, uint32_t r1, uint32_t r2)
+uint32_t HELPER(srst)(CPUS390XState *env, uint32_t c, uint32_t r1, uint32_t r2)
{
uint64_t i;
uint32_t cc = 2;
- uint64_t str = get_address_31fix(r2);
- uint64_t end = get_address_31fix(r1);
+ uint64_t str = get_address_31fix(env, r2);
+ uint64_t end = get_address_31fix(env, r1);
HELPER_LOG("%s: c %d *r1 0x%" PRIx64 " *r2 0x%" PRIx64 "\n", __func__,
c, env->regs[r1], env->regs[r2]);
for (i = str; i != end; i++) {
- if (ldub(i) == c) {
+ if (cpu_ldub_data(env, i) == c) {
env->regs[r1] = i;
cc = 1;
break;
@@ -386,10 +386,10 @@ uint32_t HELPER(srst)(uint32_t c, uint32_t r1, uint32_t r2)
}
/* unsigned string compare (c is string terminator) */
-uint32_t HELPER(clst)(uint32_t c, uint32_t r1, uint32_t r2)
+uint32_t HELPER(clst)(CPUS390XState *env, uint32_t c, uint32_t r1, uint32_t r2)
{
- uint64_t s1 = get_address_31fix(r1);
- uint64_t s2 = get_address_31fix(r2);
+ uint64_t s1 = get_address_31fix(env, r1);
+ uint64_t s2 = get_address_31fix(env, r2);
uint8_t v1, v2;
uint32_t cc;
@@ -401,8 +401,8 @@ uint32_t HELPER(clst)(uint32_t c, uint32_t r1, uint32_t r2)
}
#endif
for (;;) {
- v1 = ldub(s1);
- v2 = ldub(s2);
+ v1 = cpu_ldub_data(env, s1);
+ v2 = cpu_ldub_data(env, s2);
if ((v1 == c || v2 == c) || (v1 != v2)) {
break;
}
@@ -422,14 +422,14 @@ uint32_t HELPER(clst)(uint32_t c, uint32_t r1, uint32_t r2)
}
/* move page */
-void HELPER(mvpg)(uint64_t r0, uint64_t r1, uint64_t r2)
+void HELPER(mvpg)(CPUS390XState *env, uint64_t r0, uint64_t r1, uint64_t r2)
{
/* XXX missing r0 handling */
#ifdef CONFIG_USER_ONLY
int i;
for (i = 0; i < TARGET_PAGE_SIZE; i++) {
- stb(r1 + i, ldub(r2 + i));
+ cpu_stb_data(env, r1 + i, cpu_ldub_data(env, r2 + i));
}
#else
mvc_fast_memmove(env, TARGET_PAGE_SIZE, r1, r2);
@@ -437,10 +437,10 @@ void HELPER(mvpg)(uint64_t r0, uint64_t r1, uint64_t r2)
}
/* string copy (c is string terminator) */
-void HELPER(mvst)(uint32_t c, uint32_t r1, uint32_t r2)
+void HELPER(mvst)(CPUS390XState *env, uint32_t c, uint32_t r1, uint32_t r2)
{
- uint64_t dest = get_address_31fix(r1);
- uint64_t src = get_address_31fix(r2);
+ uint64_t dest = get_address_31fix(env, r1);
+ uint64_t src = get_address_31fix(env, r2);
uint8_t v;
c = c & 0xff;
@@ -451,8 +451,8 @@ void HELPER(mvst)(uint32_t c, uint32_t r1, uint32_t r2)
}
#endif
for (;;) {
- v = ldub(src);
- stb(dest, v);
+ v = cpu_ldub_data(env, src);
+ cpu_stb_data(env, dest, v);
if (v == c) {
break;
}
@@ -463,15 +463,15 @@ void HELPER(mvst)(uint32_t c, uint32_t r1, uint32_t r2)
}
/* compare and swap 64-bit */
-uint32_t HELPER(csg)(uint32_t r1, uint64_t a2, uint32_t r3)
+uint32_t HELPER(csg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
/* FIXME: locking? */
uint32_t cc;
- uint64_t v2 = ldq(a2);
+ uint64_t v2 = cpu_ldq_data(env, a2);
if (env->regs[r1] == v2) {
cc = 0;
- stq(a2, env->regs[r3]);
+ cpu_stq_data(env, a2, env->regs[r3]);
} else {
cc = 1;
env->regs[r1] = v2;
@@ -480,19 +480,19 @@ uint32_t HELPER(csg)(uint32_t r1, uint64_t a2, uint32_t r3)
}
/* compare double and swap 64-bit */
-uint32_t HELPER(cdsg)(uint32_t r1, uint64_t a2, uint32_t r3)
+uint32_t HELPER(cdsg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
/* FIXME: locking? */
uint32_t cc;
- uint64_t v2_hi = ldq(a2);
- uint64_t v2_lo = ldq(a2 + 8);
+ uint64_t v2_hi = cpu_ldq_data(env, a2);
+ uint64_t v2_lo = cpu_ldq_data(env, a2 + 8);
uint64_t v1_hi = env->regs[r1];
uint64_t v1_lo = env->regs[r1 + 1];
if ((v1_hi == v2_hi) && (v1_lo == v2_lo)) {
cc = 0;
- stq(a2, env->regs[r3]);
- stq(a2 + 8, env->regs[r3 + 1]);
+ cpu_stq_data(env, a2, env->regs[r3]);
+ cpu_stq_data(env, a2 + 8, env->regs[r3 + 1]);
} else {
cc = 1;
env->regs[r1] = v2_hi;
@@ -503,16 +503,16 @@ uint32_t HELPER(cdsg)(uint32_t r1, uint64_t a2, uint32_t r3)
}
/* compare and swap 32-bit */
-uint32_t HELPER(cs)(uint32_t r1, uint64_t a2, uint32_t r3)
+uint32_t HELPER(cs)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
/* FIXME: locking? */
uint32_t cc;
- uint32_t v2 = ldl(a2);
+ uint32_t v2 = cpu_ldl_data(env, a2);
HELPER_LOG("%s: r1 %d a2 0x%lx r3 %d\n", __func__, r1, a2, r3);
if (((uint32_t)env->regs[r1]) == v2) {
cc = 0;
- stl(a2, (uint32_t)env->regs[r3]);
+ cpu_stl_data(env, a2, (uint32_t)env->regs[r3]);
} else {
cc = 1;
env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | v2;
@@ -520,7 +520,8 @@ uint32_t HELPER(cs)(uint32_t r1, uint64_t a2, uint32_t r3)
return cc;
}
-static uint32_t helper_icm(uint32_t r1, uint64_t address, uint32_t mask)
+static uint32_t helper_icm(CPUS390XState *env, uint32_t r1, uint64_t address,
+ uint32_t mask)
{
int pos = 24; /* top of the lower half of r1 */
uint64_t rmask = 0xff000000ULL;
@@ -531,7 +532,7 @@ static uint32_t helper_icm(uint32_t r1, uint64_t address, uint32_t mask)
while (mask) {
if (mask & 8) {
env->regs[r1] &= ~rmask;
- val = ldub(address);
+ val = cpu_ldub_data(env, address);
if ((val & 0x80) && !ccd) {
cc = 1;
}
@@ -557,9 +558,10 @@ static uint32_t helper_icm(uint32_t r1, uint64_t address, uint32_t mask)
in other words: tricky...
currently implemented by interpreting the cases it is most commonly used in
*/
-uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
+uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1,
+ uint64_t addr, uint64_t ret)
{
- uint16_t insn = lduw_code(addr);
+ uint16_t insn = cpu_lduw_code(env, addr);
HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr,
insn);
@@ -567,23 +569,27 @@ uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
uint32_t l, insn2, b1, b2, d1, d2;
l = v1 & 0xff;
- insn2 = ldl_code(addr + 2);
+ insn2 = cpu_ldl_code(env, addr + 2);
b1 = (insn2 >> 28) & 0xf;
b2 = (insn2 >> 12) & 0xf;
d1 = (insn2 >> 16) & 0xfff;
d2 = insn2 & 0xfff;
switch (insn & 0xf00) {
case 0x200:
- helper_mvc(l, get_address(0, b1, d1), get_address(0, b2, d2));
+ helper_mvc(env, l, get_address(env, 0, b1, d1),
+ get_address(env, 0, b2, d2));
break;
case 0x500:
- cc = helper_clc(l, get_address(0, b1, d1), get_address(0, b2, d2));
+ cc = helper_clc(env, l, get_address(env, 0, b1, d1),
+ get_address(env, 0, b2, d2));
break;
case 0x700:
- cc = helper_xc(l, get_address(0, b1, d1), get_address(0, b2, d2));
+ cc = helper_xc(env, l, get_address(env, 0, b1, d1),
+ get_address(env, 0, b2, d2));
break;
case 0xc00:
- helper_tr(l, get_address(0, b1, d1), get_address(0, b2, d2));
+ helper_tr(env, l, get_address(env, 0, b1, d1),
+ get_address(env, 0, b2, d2));
break;
default:
goto abort;
@@ -599,12 +605,12 @@ uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
} else if ((insn & 0xff00) == 0xbf00) {
uint32_t insn2, r1, r3, b2, d2;
- insn2 = ldl_code(addr + 2);
+ insn2 = cpu_ldl_code(env, addr + 2);
r1 = (insn2 >> 20) & 0xf;
r3 = (insn2 >> 16) & 0xf;
b2 = (insn2 >> 12) & 0xf;
d2 = insn2 & 0xfff;
- cc = helper_icm(r1, get_address(0, b2, d2), r3);
+ cc = helper_icm(env, r1, get_address(env, 0, b2, d2), r3);
} else {
abort:
cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n",
@@ -614,13 +620,14 @@ uint32_t HELPER(ex)(uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret)
}
/* store character under mask high operates on the upper half of r1 */
-void HELPER(stcmh)(uint32_t r1, uint64_t address, uint32_t mask)
+void HELPER(stcmh)(CPUS390XState *env, uint32_t r1, uint64_t address,
+ uint32_t mask)
{
int pos = 56; /* top of the upper half of r1 */
while (mask) {
if (mask & 8) {
- stb(address, (env->regs[r1] >> pos) & 0xff);
+ cpu_stb_data(env, address, (env->regs[r1] >> pos) & 0xff);
address++;
}
mask = (mask << 1) & 0xf;
@@ -630,7 +637,8 @@ void HELPER(stcmh)(uint32_t r1, uint64_t address, uint32_t mask)
/* insert character under mask high; same as icm, but operates on the
upper half of r1 */
-uint32_t HELPER(icmh)(uint32_t r1, uint64_t address, uint32_t mask)
+uint32_t HELPER(icmh)(CPUS390XState *env, uint32_t r1, uint64_t address,
+ uint32_t mask)
{
int pos = 56; /* top of the upper half of r1 */
uint64_t rmask = 0xff00000000000000ULL;
@@ -641,7 +649,7 @@ uint32_t HELPER(icmh)(uint32_t r1, uint64_t address, uint32_t mask)
while (mask) {
if (mask & 8) {
env->regs[r1] &= ~rmask;
- val = ldub(address);
+ val = cpu_ldub_data(env, address);
if ((val & 0x80) && !ccd) {
cc = 1;
}
@@ -661,12 +669,12 @@ uint32_t HELPER(icmh)(uint32_t r1, uint64_t address, uint32_t mask)
}
/* load access registers r1 to r3 from memory at a2 */
-void HELPER(lam)(uint32_t r1, uint64_t a2, uint32_t r3)
+void HELPER(lam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
int i;
for (i = r1;; i = (i + 1) % 16) {
- env->aregs[i] = ldl(a2);
+ env->aregs[i] = cpu_ldl_data(env, a2);
a2 += 4;
if (i == r3) {
@@ -676,12 +684,12 @@ void HELPER(lam)(uint32_t r1, uint64_t a2, uint32_t r3)
}
/* store access registers r1 to r3 in memory at a2 */
-void HELPER(stam)(uint32_t r1, uint64_t a2, uint32_t r3)
+void HELPER(stam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
int i;
for (i = r1;; i = (i + 1) % 16) {
- stl(a2, env->aregs[i]);
+ cpu_stl_data(env, a2, env->aregs[i]);
a2 += 4;
if (i == r3) {
@@ -691,12 +699,12 @@ void HELPER(stam)(uint32_t r1, uint64_t a2, uint32_t r3)
}
/* move long */
-uint32_t HELPER(mvcl)(uint32_t r1, uint32_t r2)
+uint32_t HELPER(mvcl)(CPUS390XState *env, uint32_t r1, uint32_t r2)
{
uint64_t destlen = env->regs[r1 + 1] & 0xffffff;
- uint64_t dest = get_address_31fix(r1);
+ uint64_t dest = get_address_31fix(env, r1);
uint64_t srclen = env->regs[r2 + 1] & 0xffffff;
- uint64_t src = get_address_31fix(r2);
+ uint64_t src = get_address_31fix(env, r2);
uint8_t pad = src >> 24;
uint8_t v;
uint32_t cc;
@@ -714,12 +722,12 @@ uint32_t HELPER(mvcl)(uint32_t r1, uint32_t r2)
}
for (; destlen && srclen; src++, dest++, destlen--, srclen--) {
- v = ldub(src);
- stb(dest, v);
+ v = cpu_ldub_data(env, src);
+ cpu_stb_data(env, dest, v);
}
for (; destlen; dest++, destlen--) {
- stb(dest, pad);
+ cpu_stb_data(env, dest, pad);
}
env->regs[r1 + 1] = destlen;
@@ -732,7 +740,8 @@ uint32_t HELPER(mvcl)(uint32_t r1, uint32_t r2)
}
/* move long extended another memcopy insn with more bells and whistles */
-uint32_t HELPER(mvcle)(uint32_t r1, uint64_t a2, uint32_t r3)
+uint32_t HELPER(mvcle)(CPUS390XState *env, uint32_t r1, uint64_t a2,
+ uint32_t r3)
{
uint64_t destlen = env->regs[r1 + 1];
uint64_t dest = env->regs[r1];
@@ -762,12 +771,12 @@ uint32_t HELPER(mvcle)(uint32_t r1, uint64_t a2, uint32_t r3)
}
for (; destlen && srclen; src++, dest++, destlen--, srclen--) {
- v = ldub(src);
- stb(dest, v);
+ v = cpu_ldub_data(env, src);
+ cpu_stb_data(env, dest, v);
}
for (; destlen; dest++, destlen--) {
- stb(dest, pad);
+ cpu_stb_data(env, dest, pad);
}
env->regs[r1 + 1] = destlen;
@@ -781,12 +790,13 @@ uint32_t HELPER(mvcle)(uint32_t r1, uint64_t a2, uint32_t r3)
}
/* compare logical long extended memcompare insn with padding */
-uint32_t HELPER(clcle)(uint32_t r1, uint64_t a2, uint32_t r3)
+uint32_t HELPER(clcle)(CPUS390XState *env, uint32_t r1, uint64_t a2,
+ uint32_t r3)
{
uint64_t destlen = env->regs[r1 + 1];
- uint64_t dest = get_address_31fix(r1);
+ uint64_t dest = get_address_31fix(env, r1);
uint64_t srclen = env->regs[r3 + 1];
- uint64_t src = get_address_31fix(r3);
+ uint64_t src = get_address_31fix(env, r3);
uint8_t pad = a2 & 0xff;
uint8_t v1 = 0, v2 = 0;
uint32_t cc = 0;
@@ -800,8 +810,8 @@ uint32_t HELPER(clcle)(uint32_t r1, uint64_t a2, uint32_t r3)
}
for (; destlen || srclen; src++, dest++, destlen--, srclen--) {
- v1 = srclen ? ldub(src) : pad;
- v2 = destlen ? ldub(dest) : pad;
+ v1 = srclen ? cpu_ldub_data(env, src) : pad;
+ v2 = destlen ? cpu_ldub_data(env, dest) : pad;
if (v1 != v2) {
cc = (v1 < v2) ? 1 : 2;
break;
@@ -818,14 +828,14 @@ uint32_t HELPER(clcle)(uint32_t r1, uint64_t a2, uint32_t r3)
}
/* checksum */
-void HELPER(cksm)(uint32_t r1, uint32_t r2)
+void HELPER(cksm)(CPUS390XState *env, uint32_t r1, uint32_t r2)
{
- uint64_t src = get_address_31fix(r2);
+ uint64_t src = get_address_31fix(env, r2);
uint64_t src_len = env->regs[(r2 + 1) & 15];
uint64_t cksm = (uint32_t)env->regs[r1];
while (src_len >= 4) {
- cksm += ldl(src);
+ cksm += cpu_ldl_data(env, src);
/* move to next word */
src_len -= 4;
@@ -836,14 +846,14 @@ void HELPER(cksm)(uint32_t r1, uint32_t r2)
case 0:
break;
case 1:
- cksm += ldub(src) << 24;
+ cksm += cpu_ldub_data(env, src) << 24;
break;
case 2:
- cksm += lduw(src) << 16;
+ cksm += cpu_lduw_data(env, src) << 16;
break;
case 3:
- cksm += lduw(src) << 16;
- cksm += ldub(src + 2) << 8;
+ cksm += cpu_lduw_data(env, src) << 16;
+ cksm += cpu_ldub_data(env, src + 2) << 8;
break;
}
@@ -856,7 +866,8 @@ void HELPER(cksm)(uint32_t r1, uint32_t r2)
((uint32_t)cksm + (cksm >> 32));
}
-void HELPER(unpk)(uint32_t len, uint64_t dest, uint64_t src)
+void HELPER(unpk)(CPUS390XState *env, uint32_t len, uint64_t dest,
+ uint64_t src)
{
int len_dest = len >> 4;
int len_src = len & 0xf;
@@ -867,8 +878,8 @@ void HELPER(unpk)(uint32_t len, uint64_t dest, uint64_t src)
src += len_src;
/* last byte is special, it only flips the nibbles */
- b = ldub(src);
- stb(dest, (b << 4) | (b >> 4));
+ b = cpu_ldub_data(env, src);
+ cpu_stb_data(env, dest, (b << 4) | (b >> 4));
src--;
len_src--;
@@ -878,7 +889,7 @@ void HELPER(unpk)(uint32_t len, uint64_t dest, uint64_t src)
uint8_t cur_byte = 0;
if (len_src > 0) {
- cur_byte = ldub(src);
+ cur_byte = cpu_ldub_data(env, src);
}
len_dest--;
@@ -897,30 +908,31 @@ void HELPER(unpk)(uint32_t len, uint64_t dest, uint64_t src)
/* zone bits */
cur_byte |= 0xf0;
- stb(dest, cur_byte);
+ cpu_stb_data(env, dest, cur_byte);
}
}
-void HELPER(tr)(uint32_t len, uint64_t array, uint64_t trans)
+void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array,
+ uint64_t trans)
{
int i;
for (i = 0; i <= len; i++) {
- uint8_t byte = ldub(array + i);
- uint8_t new_byte = ldub(trans + byte);
+ uint8_t byte = cpu_ldub_data(env, array + i);
+ uint8_t new_byte = cpu_ldub_data(env, trans + byte);
- stb(array + i, new_byte);
+ cpu_stb_data(env, array + i, new_byte);
}
}
#if !defined(CONFIG_USER_ONLY)
-void HELPER(lctlg)(uint32_t r1, uint64_t a2, uint32_t r3)
+void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
int i;
uint64_t src = a2;
for (i = r1;; i = (i + 1) % 16) {
- env->cregs[i] = ldq(src);
+ env->cregs[i] = cpu_ldq_data(env, src);
HELPER_LOG("load ctl %d from 0x%" PRIx64 " == 0x%" PRIx64 "\n",
i, src, env->cregs[i]);
src += sizeof(uint64_t);
@@ -933,13 +945,14 @@ void HELPER(lctlg)(uint32_t r1, uint64_t a2, uint32_t r3)
tlb_flush(env, 1);
}
-void HELPER(lctl)(uint32_t r1, uint64_t a2, uint32_t r3)
+void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
int i;
uint64_t src = a2;
for (i = r1;; i = (i + 1) % 16) {
- env->cregs[i] = (env->cregs[i] & 0xFFFFFFFF00000000ULL) | ldl(src);
+ env->cregs[i] = (env->cregs[i] & 0xFFFFFFFF00000000ULL) |
+ cpu_ldl_data(env, src);
src += sizeof(uint32_t);
if (i == r3) {
@@ -950,13 +963,13 @@ void HELPER(lctl)(uint32_t r1, uint64_t a2, uint32_t r3)
tlb_flush(env, 1);
}
-void HELPER(stctg)(uint32_t r1, uint64_t a2, uint32_t r3)
+void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
int i;
uint64_t dest = a2;
for (i = r1;; i = (i + 1) % 16) {
- stq(dest, env->cregs[i]);
+ cpu_stq_data(env, dest, env->cregs[i]);
dest += sizeof(uint64_t);
if (i == r3) {
@@ -965,13 +978,13 @@ void HELPER(stctg)(uint32_t r1, uint64_t a2, uint32_t r3)
}
}
-void HELPER(stctl)(uint32_t r1, uint64_t a2, uint32_t r3)
+void HELPER(stctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
int i;
uint64_t dest = a2;
for (i = r1;; i = (i + 1) % 16) {
- stl(dest, env->cregs[i]);
+ cpu_stl_data(env, dest, env->cregs[i]);
dest += sizeof(uint32_t);
if (i == r3) {
@@ -988,9 +1001,9 @@ uint32_t HELPER(tprot)(uint64_t a1, uint64_t a2)
}
/* insert storage key extended */
-uint64_t HELPER(iske)(uint64_t r2)
+uint64_t HELPER(iske)(CPUS390XState *env, uint64_t r2)
{
- uint64_t addr = get_address(0, 0, r2);
+ uint64_t addr = get_address(env, 0, 0, r2);
if (addr > ram_size) {
return 0;
@@ -1000,9 +1013,9 @@ uint64_t HELPER(iske)(uint64_t r2)
}
/* set storage key extended */
-void HELPER(sske)(uint32_t r1, uint64_t r2)
+void HELPER(sske)(CPUS390XState *env, uint32_t r1, uint64_t r2)
{
- uint64_t addr = get_address(0, 0, r2);
+ uint64_t addr = get_address(env, 0, 0, r2);
if (addr > ram_size) {
return;
@@ -1012,7 +1025,7 @@ void HELPER(sske)(uint32_t r1, uint64_t r2)
}
/* reset reference bit extended */
-uint32_t HELPER(rrbe)(uint32_t r1, uint64_t r2)
+uint32_t HELPER(rrbe)(CPUS390XState *env, uint32_t r1, uint64_t r2)
{
uint8_t re;
uint8_t key;
@@ -1038,15 +1051,15 @@ uint32_t HELPER(rrbe)(uint32_t r1, uint64_t r2)
}
/* compare and swap and purge */
-uint32_t HELPER(csp)(uint32_t r1, uint32_t r2)
+uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint32_t r2)
{
uint32_t cc;
uint32_t o1 = env->regs[r1];
- uint64_t a2 = get_address_31fix(r2) & ~3ULL;
- uint32_t o2 = ldl(a2);
+ uint64_t a2 = get_address_31fix(env, r2) & ~3ULL;
+ uint32_t o2 = cpu_ldl_data(env, a2);
if (o1 == o2) {
- stl(a2, env->regs[(r1 + 1) & 15]);
+ cpu_stl_data(env, a2, env->regs[(r1 + 1) & 15]);
if (env->regs[r2] & 0x3) {
/* flush TLB / ALB */
tlb_flush(env, 1);
@@ -1060,8 +1073,8 @@ uint32_t HELPER(csp)(uint32_t r1, uint32_t r2)
return cc;
}
-static uint32_t mvc_asc(int64_t l, uint64_t a1, uint64_t mode1, uint64_t a2,
- uint64_t mode2)
+static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1,
+ uint64_t mode1, uint64_t a2, uint64_t mode2)
{
target_ulong src, dest;
int flags, cc = 0, i;
@@ -1089,7 +1102,7 @@ static uint32_t mvc_asc(int64_t l, uint64_t a1, uint64_t mode1, uint64_t a2,
/* XXX be more clever */
if ((((dest + i) & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) ||
(((src + i) & TARGET_PAGE_MASK) != (src & TARGET_PAGE_MASK))) {
- mvc_asc(l - i, a1 + i, mode1, a2 + i, mode2);
+ mvc_asc(env, l - i, a1 + i, mode1, a2 + i, mode2);
break;
}
stb_phys(dest + i, ldub_phys(src + i));
@@ -1098,24 +1111,24 @@ static uint32_t mvc_asc(int64_t l, uint64_t a1, uint64_t mode1, uint64_t a2,
return cc;
}
-uint32_t HELPER(mvcs)(uint64_t l, uint64_t a1, uint64_t a2)
+uint32_t HELPER(mvcs)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2)
{
HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
__func__, l, a1, a2);
- return mvc_asc(l, a1, PSW_ASC_SECONDARY, a2, PSW_ASC_PRIMARY);
+ return mvc_asc(env, l, a1, PSW_ASC_SECONDARY, a2, PSW_ASC_PRIMARY);
}
-uint32_t HELPER(mvcp)(uint64_t l, uint64_t a1, uint64_t a2)
+uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2)
{
HELPER_LOG("%s: %16" PRIx64 " %16" PRIx64 " %16" PRIx64 "\n",
__func__, l, a1, a2);
- return mvc_asc(l, a1, PSW_ASC_PRIMARY, a2, PSW_ASC_SECONDARY);
+ return mvc_asc(env, l, a1, PSW_ASC_PRIMARY, a2, PSW_ASC_SECONDARY);
}
/* invalidate pte */
-void HELPER(ipte)(uint64_t pte_addr, uint64_t vaddr)
+void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
{
uint64_t page = vaddr & TARGET_PAGE_MASK;
uint64_t pte = 0;
@@ -1141,19 +1154,19 @@ void HELPER(ipte)(uint64_t pte_addr, uint64_t vaddr)
}
/* flush local tlb */
-void HELPER(ptlb)(void)
+void HELPER(ptlb)(CPUS390XState *env)
{
tlb_flush(env, 1);
}
/* store using real address */
-void HELPER(stura)(uint64_t addr, uint32_t v1)
+void HELPER(stura)(CPUS390XState *env, uint64_t addr, uint32_t v1)
{
- stw_phys(get_address(0, 0, addr), v1);
+ stw_phys(get_address(env, 0, 0, addr), v1);
}
/* load real address */
-uint32_t HELPER(lra)(uint64_t addr, uint32_t r1)
+uint32_t HELPER(lra)(CPUS390XState *env, uint64_t addr, uint32_t r1)
{
uint32_t cc = 0;
int old_exc = env->exception_index;
@@ -1188,52 +1201,3 @@ uint32_t HELPER(lra)(uint64_t addr, uint32_t r1)
}
#endif
-
-/* temporary wrappers */
-#if defined(CONFIG_USER_ONLY)
-#define ldub_data(addr) ldub_raw(addr)
-#define lduw_data(addr) lduw_raw(addr)
-#define ldl_data(addr) ldl_raw(addr)
-#define ldq_data(addr) ldq_raw(addr)
-
-#define stb_data(addr, data) stb_raw(addr, data)
-#define stw_data(addr, data) stw_raw(addr, data)
-#define stl_data(addr, data) stl_raw(addr, data)
-#define stq_data(addr, data) stq_raw(addr, data)
-#endif
-
-#define WRAP_LD(rettype, fn) \
- rettype cpu_ ## fn(CPUS390XState *env1, target_ulong addr) \
- { \
- CPUS390XState *saved_env; \
- rettype ret; \
- \
- saved_env = env; \
- env = env1; \
- ret = fn(addr); \
- env = saved_env; \
- return ret; \
- }
-
-WRAP_LD(uint32_t, ldub_data)
-WRAP_LD(uint32_t, lduw_data)
-WRAP_LD(uint32_t, ldl_data)
-WRAP_LD(uint64_t, ldq_data)
-#undef WRAP_LD
-
-#define WRAP_ST(datatype, fn) \
- void cpu_ ## fn(CPUS390XState *env1, target_ulong addr, datatype val) \
- { \
- CPUS390XState *saved_env; \
- \
- saved_env = env; \
- env = env1; \
- fn(addr, val); \
- env = saved_env; \
- }
-
-WRAP_ST(uint32_t, stb_data)
-WRAP_ST(uint32_t, stw_data)
-WRAP_ST(uint32_t, stl_data)
-WRAP_ST(uint64_t, stq_data)
-#undef WRAP_ST
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index 0ba737a..2938ac9 100644
--- a/target-s390x/misc_helper.c
+++ b/target-s390x/misc_helper.c
@@ -30,12 +30,8 @@
#include <linux/kvm.h>
#endif
-/* temporarily disabled due to wrapper use */
-#if 0 && !defined(CONFIG_USER_ONLY)
-#include "softmmu_exec.h"
-#endif
-
#if !defined(CONFIG_USER_ONLY)
+#include "softmmu_exec.h"
#include "sysemu.h"
#endif
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 0c61e63..66119cd 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -276,19 +276,19 @@ static inline void potential_page_fault(DisasContext *s)
static inline uint64_t ld_code2(uint64_t pc)
{
- return (uint64_t)lduw_code(pc);
+ return (uint64_t)cpu_lduw_code(cpu_single_env, pc);
}
static inline uint64_t ld_code4(uint64_t pc)
{
- return (uint64_t)ldl_code(pc);
+ return (uint64_t)cpu_ldl_code(cpu_single_env, pc);
}
static inline uint64_t ld_code6(uint64_t pc)
{
uint64_t opc;
- opc = (uint64_t)lduw_code(pc) << 32;
- opc |= (uint64_t)(uint32_t)ldl_code(pc+2);
+ opc = (uint64_t)cpu_lduw_code(cpu_single_env, pc) << 32;
+ opc |= (uint64_t)(uint32_t)cpu_ldl_code(cpu_single_env, pc + 2);
return opc;
}
@@ -1263,7 +1263,7 @@ static void gen_op_mvc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2)
/* Fall back to helper */
vl = tcg_const_i32(l);
potential_page_fault(s);
- gen_helper_mvc(vl, s1, s2);
+ gen_helper_mvc(cpu_env, vl, s1, s2);
tcg_temp_free_i32(vl);
return;
}
@@ -1455,7 +1455,7 @@ static void gen_op_clc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2)
potential_page_fault(s);
vl = tcg_const_i32(l);
- gen_helper_clc(cc_op, vl, s1, s2);
+ gen_helper_clc(cc_op, cpu_env, vl, s1, s2);
tcg_temp_free_i32(vl);
set_cc_static(s);
}
@@ -2094,7 +2094,7 @@ do_mh:
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_stcmh(tmp32_1, tmp, tmp32_2);
+ gen_helper_stcmh(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -2107,7 +2107,7 @@ do_mh:
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_lctlg(tmp32_1, tmp, tmp32_2);
+ gen_helper_lctlg(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -2119,7 +2119,7 @@ do_mh:
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_stctg(tmp32_1, tmp, tmp32_2);
+ gen_helper_stctg(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -2131,7 +2131,7 @@ do_mh:
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
/* XXX rewrite in tcg */
- gen_helper_csg(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_csg(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
@@ -2143,7 +2143,7 @@ do_mh:
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
/* XXX rewrite in tcg */
- gen_helper_cdsg(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_cdsg(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
@@ -2183,7 +2183,7 @@ do_mh:
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
/* XXX split CC calculation out */
- gen_helper_icmh(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_icmh(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
@@ -2635,7 +2635,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
potential_page_fault(s);
- gen_helper_cksm(tmp32_1, tmp32_2);
+ gen_helper_cksm(cpu_env, tmp32_1, tmp32_2);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
gen_op_movi_cc(s, 0);
@@ -2664,7 +2664,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tmp2 = load_reg(r1);
tmp3 = load_reg(r2);
potential_page_fault(s);
- gen_helper_mvpg(tmp, tmp2, tmp3);
+ gen_helper_mvpg(cpu_env, tmp, tmp2, tmp3);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i64(tmp3);
@@ -2676,7 +2676,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tmp32_2 = tcg_const_i32(r1);
tmp32_3 = tcg_const_i32(r2);
potential_page_fault(s);
- gen_helper_mvst(tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_mvst(cpu_env, tmp32_1, tmp32_2, tmp32_3);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
tcg_temp_free_i32(tmp32_3);
@@ -2687,7 +2687,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tmp32_2 = tcg_const_i32(r1);
tmp32_3 = tcg_const_i32(r2);
potential_page_fault(s);
- gen_helper_clst(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_clst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -2698,7 +2698,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tmp32_2 = tcg_const_i32(r1);
tmp32_3 = tcg_const_i32(r2);
potential_page_fault(s);
- gen_helper_srst(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_srst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -2785,7 +2785,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
case 0x0d: /* PTLB [S] */
/* Purge TLB */
check_privileged(s, ilc);
- gen_helper_ptlb();
+ gen_helper_ptlb(cpu_env);
break;
case 0x10: /* SPX D2(B2) [S] */
/* Set Prefix Register */
@@ -2828,7 +2828,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
r2 = insn & 0xf;
tmp = load_reg(r1);
tmp2 = load_reg(r2);
- gen_helper_ipte(tmp, tmp2);
+ gen_helper_ipte(cpu_env, tmp, tmp2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
break;
@@ -2839,7 +2839,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
r2 = insn & 0xf;
tmp = load_reg(r2);
tmp2 = tcg_temp_new_i64();
- gen_helper_iske(tmp2, tmp);
+ gen_helper_iske(tmp2, cpu_env, tmp);
store_reg(r1, tmp2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
@@ -2851,7 +2851,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
r2 = insn & 0xf;
tmp32_1 = load_reg32(r1);
tmp = load_reg(r2);
- gen_helper_rrbe(cc_op, tmp32_1, tmp);
+ gen_helper_rrbe(cc_op, cpu_env, tmp32_1, tmp);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp);
@@ -2863,7 +2863,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
r2 = insn & 0xf;
tmp32_1 = load_reg32(r1);
tmp = load_reg(r2);
- gen_helper_sske(tmp32_1, tmp);
+ gen_helper_sske(cpu_env, tmp32_1, tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp);
break;
@@ -2880,7 +2880,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tmp32_1 = load_reg32(r1);
tmp = load_reg(r2);
potential_page_fault(s);
- gen_helper_stura(tmp, tmp32_1);
+ gen_helper_stura(cpu_env, tmp, tmp32_1);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp);
break;
@@ -2891,7 +2891,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
r2 = insn & 0xf;
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
- gen_helper_csp(cc_op, tmp32_1, tmp32_2);
+ gen_helper_csp(cc_op, cpu_env, tmp32_1, tmp32_2);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -3865,7 +3865,7 @@ static void disas_s390_insn(DisasContext *s)
int ilc;
int l1;
- opc = ldub_code(s->pc);
+ opc = cpu_ldub_code(cpu_single_env, s->pc);
LOG_DISAS("opc 0x%x\n", opc);
ilc = get_ilc(opc);
@@ -3951,7 +3951,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
potential_page_fault(s);
- gen_helper_mvcl(cc_op, tmp32_1, tmp32_2);
+ gen_helper_mvcl(cc_op, cpu_env, tmp32_1, tmp32_2);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -4165,7 +4165,7 @@ static void disas_s390_insn(DisasContext *s)
tmp3 = tcg_const_i64(s->pc + 4);
update_psw_addr(s);
gen_op_calc_cc(s);
- gen_helper_ex(cc_op, cc_op, tmp2, tmp, tmp3);
+ gen_helper_ex(cc_op, cpu_env, cc_op, tmp2, tmp, tmp3);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
@@ -4694,7 +4694,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_lam(tmp32_1, tmp, tmp32_2);
+ gen_helper_lam(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -4706,7 +4706,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_stam(tmp32_1, tmp, tmp32_2);
+ gen_helper_stam(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -4732,7 +4732,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_mvcle(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_mvcle(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
@@ -4745,7 +4745,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_clcle(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_clcle(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
@@ -4789,7 +4789,7 @@ static void disas_s390_insn(DisasContext *s)
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp32_1 = tcg_const_i32(r1);
potential_page_fault(s);
- gen_helper_lra(cc_op, tmp, tmp32_1);
+ gen_helper_lra(cc_op, cpu_env, tmp, tmp32_1);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
@@ -4835,7 +4835,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_stctl(tmp32_1, tmp, tmp32_2);
+ gen_helper_stctl(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -4849,7 +4849,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_lctl(tmp32_1, tmp, tmp32_2);
+ gen_helper_lctl(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -4869,7 +4869,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_cs(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_cs(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
@@ -4882,7 +4882,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = load_reg32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_clm(cc_op, tmp32_1, tmp32_2, tmp);
+ gen_helper_clm(cc_op, cpu_env, tmp32_1, tmp32_2, tmp);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
@@ -4895,7 +4895,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = load_reg32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_stcm(tmp32_1, tmp32_2, tmp);
+ gen_helper_stcm(cpu_env, tmp32_1, tmp32_2, tmp);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
@@ -4992,7 +4992,7 @@ static void disas_s390_insn(DisasContext *s)
break;
case 0xd4:
potential_page_fault(s);
- gen_helper_nc(cc_op, vl, tmp, tmp2);
+ gen_helper_nc(cc_op, cpu_env, vl, tmp, tmp2);
set_cc_static(s);
break;
case 0xd5:
@@ -5000,22 +5000,22 @@ static void disas_s390_insn(DisasContext *s)
break;
case 0xd6:
potential_page_fault(s);
- gen_helper_oc(cc_op, vl, tmp, tmp2);
+ gen_helper_oc(cc_op, cpu_env, vl, tmp, tmp2);
set_cc_static(s);
break;
case 0xd7:
potential_page_fault(s);
- gen_helper_xc(cc_op, vl, tmp, tmp2);
+ gen_helper_xc(cc_op, cpu_env, vl, tmp, tmp2);
set_cc_static(s);
break;
case 0xdc:
potential_page_fault(s);
- gen_helper_tr(vl, tmp, tmp2);
+ gen_helper_tr(cpu_env, vl, tmp, tmp2);
set_cc_static(s);
break;
case 0xf3:
potential_page_fault(s);
- gen_helper_unpk(vl, tmp, tmp2);
+ gen_helper_unpk(cpu_env, vl, tmp, tmp2);
break;
default:
tcg_abort();
@@ -5040,9 +5040,9 @@ static void disas_s390_insn(DisasContext *s)
tmp2 = get_address(s, 0, b1, d1);
tmp3 = get_address(s, 0, b2, d2);
if (opc == 0xda) {
- gen_helper_mvcp(cc_op, tmp, tmp2, tmp3);
+ gen_helper_mvcp(cc_op, cpu_env, tmp, tmp2, tmp3);
} else {
- gen_helper_mvcs(cc_op, tmp, tmp2, tmp3);
+ gen_helper_mvcs(cc_op, cpu_env, tmp, tmp2, tmp3);
}
set_cc_static(s);
tcg_temp_free_i64(tmp);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 12/21] target-s390x: split helper.c
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (10 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 11/21] target-s390x: switch to AREG0 free mode Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 13/21] target-lm32: switch to AREG0 free mode Blue Swirl
` (9 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Alexander Graf
Move CPU init to cpu.c and the rest of helper.c to misc_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
target-s390x/Makefile.objs | 2 +-
target-s390x/cpu.c | 18 ++
target-s390x/helper.c | 619 --------------------------------------------
target-s390x/misc_helper.c | 570 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 589 insertions(+), 620 deletions(-)
delete mode 100644 target-s390x/helper.c
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
index e728abf..eadcf6a 100644
--- a/target-s390x/Makefile.objs
+++ b/target-s390x/Makefile.objs
@@ -1,4 +1,4 @@
-obj-y += translate.o helper.o cpu.o interrupt.o
+obj-y += translate.o cpu.o interrupt.o
obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o misc_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o
obj-$(CONFIG_KVM) += kvm.o
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 619b202..837feff 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -24,6 +24,24 @@
#include "qemu-common.h"
#include "qemu-timer.h"
+S390CPU *cpu_s390x_init(const char *cpu_model)
+{
+ S390CPU *cpu;
+ CPUS390XState *env;
+ static int inited;
+
+ cpu = S390_CPU(object_new(TYPE_S390_CPU));
+ env = &cpu->env;
+
+ if (tcg_enabled() && !inited) {
+ inited = 1;
+ s390x_translate_init();
+ }
+
+ env->cpu_model_str = cpu_model;
+ qemu_init_vcpu(env);
+ return cpu;
+}
/* CPUClass::reset() */
static void s390_cpu_reset(CPUState *s)
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
deleted file mode 100644
index a5741ec..0000000
--- a/target-s390x/helper.c
+++ /dev/null
@@ -1,619 +0,0 @@
-/*
- * S/390 helpers
- *
- * Copyright (c) 2009 Ulrich Hecht
- * Copyright (c) 2011 Alexander Graf
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "cpu.h"
-#include "gdbstub.h"
-#include "qemu-timer.h"
-#ifndef CONFIG_USER_ONLY
-#include "sysemu.h"
-#endif
-
-//#define DEBUG_S390
-//#define DEBUG_S390_PTE
-//#define DEBUG_S390_STDOUT
-
-#ifdef DEBUG_S390
-#ifdef DEBUG_S390_STDOUT
-#define DPRINTF(fmt, ...) \
- do { fprintf(stderr, fmt, ## __VA_ARGS__); \
- qemu_log(fmt, ##__VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...) \
- do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
-#endif
-#else
-#define DPRINTF(fmt, ...) \
- do { } while (0)
-#endif
-
-#ifdef DEBUG_S390_PTE
-#define PTE_DPRINTF DPRINTF
-#else
-#define PTE_DPRINTF(fmt, ...) \
- do { } while (0)
-#endif
-
-#ifndef CONFIG_USER_ONLY
-void s390x_tod_timer(void *opaque)
-{
- S390CPU *cpu = opaque;
- CPUS390XState *env = &cpu->env;
-
- env->pending_int |= INTERRUPT_TOD;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
-}
-
-void s390x_cpu_timer(void *opaque)
-{
- S390CPU *cpu = opaque;
- CPUS390XState *env = &cpu->env;
-
- env->pending_int |= INTERRUPT_CPUTIMER;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
-}
-#endif
-
-S390CPU *cpu_s390x_init(const char *cpu_model)
-{
- S390CPU *cpu;
- CPUS390XState *env;
- static int inited;
-
- cpu = S390_CPU(object_new(TYPE_S390_CPU));
- env = &cpu->env;
-
- if (tcg_enabled() && !inited) {
- inited = 1;
- s390x_translate_init();
- }
-
- env->cpu_model_str = cpu_model;
- qemu_init_vcpu(env);
- return cpu;
-}
-
-#if defined(CONFIG_USER_ONLY)
-
-void do_interrupt(CPUS390XState *env)
-{
- env->exception_index = -1;
-}
-
-int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
- int rw, int mmu_idx)
-{
- /* fprintf(stderr, "%s: address 0x%lx rw %d mmu_idx %d\n",
- __func__, address, rw, mmu_idx); */
- env->exception_index = EXCP_ADDR;
- /* FIXME: find out how this works on a real machine */
- env->__excp_addr = address;
- return 1;
-}
-
-#else /* !CONFIG_USER_ONLY */
-
-/* Ensure to exit the TB after this call! */
-static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
- uint32_t ilc)
-{
- env->exception_index = EXCP_PGM;
- env->int_pgm_code = code;
- env->int_pgm_ilc = ilc;
-}
-
-static int trans_bits(CPUS390XState *env, uint64_t mode)
-{
- int bits = 0;
-
- switch (mode) {
- case PSW_ASC_PRIMARY:
- bits = 1;
- break;
- case PSW_ASC_SECONDARY:
- bits = 2;
- break;
- case PSW_ASC_HOME:
- bits = 3;
- break;
- default:
- cpu_abort(env, "unknown asc mode\n");
- break;
- }
-
- return bits;
-}
-
-static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
- uint64_t mode)
-{
- int ilc = ILC_LATER_INC_2;
- int bits = trans_bits(env, mode) | 4;
-
- DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
-
- stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
- trigger_pgm_exception(env, PGM_PROTECTION, ilc);
-}
-
-static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
- uint32_t type, uint64_t asc, int rw)
-{
- int ilc = ILC_LATER;
- int bits = trans_bits(env, asc);
-
- if (rw == 2) {
- /* code has is undefined ilc */
- ilc = 2;
- }
-
- DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
-
- stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
- trigger_pgm_exception(env, type, ilc);
-}
-
-static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
- uint64_t asc, uint64_t asce, int level,
- target_ulong *raddr, int *flags, int rw)
-{
- uint64_t offs = 0;
- uint64_t origin;
- uint64_t new_asce;
-
- PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);
-
- if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
- ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
- /* XXX different regions have different faults */
- DPRINTF("%s: invalid region\n", __func__);
- trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
- return -1;
- }
-
- if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
- trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
- return -1;
- }
-
- if (asce & _ASCE_REAL_SPACE) {
- /* direct mapping */
-
- *raddr = vaddr;
- return 0;
- }
-
- origin = asce & _ASCE_ORIGIN;
-
- switch (level) {
- case _ASCE_TYPE_REGION1 + 4:
- offs = (vaddr >> 50) & 0x3ff8;
- break;
- case _ASCE_TYPE_REGION1:
- offs = (vaddr >> 39) & 0x3ff8;
- break;
- case _ASCE_TYPE_REGION2:
- offs = (vaddr >> 28) & 0x3ff8;
- break;
- case _ASCE_TYPE_REGION3:
- offs = (vaddr >> 17) & 0x3ff8;
- break;
- case _ASCE_TYPE_SEGMENT:
- offs = (vaddr >> 9) & 0x07f8;
- origin = asce & _SEGMENT_ENTRY_ORIGIN;
- break;
- }
-
- /* XXX region protection flags */
- /* *flags &= ~PAGE_WRITE */
-
- new_asce = ldq_phys(origin + offs);
- PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
- __func__, origin, offs, new_asce);
-
- if (level != _ASCE_TYPE_SEGMENT) {
- /* yet another region */
- return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
- flags, rw);
- }
-
- /* PTE */
- if (new_asce & _PAGE_INVALID) {
- DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce);
- trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
- return -1;
- }
-
- if (new_asce & _PAGE_RO) {
- *flags &= ~PAGE_WRITE;
- }
-
- *raddr = new_asce & _ASCE_ORIGIN;
-
- PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce);
-
- return 0;
-}
-
-static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
- uint64_t asc, target_ulong *raddr, int *flags,
- int rw)
-{
- uint64_t asce = 0;
- int level, new_level;
- int r;
-
- switch (asc) {
- case PSW_ASC_PRIMARY:
- PTE_DPRINTF("%s: asc=primary\n", __func__);
- asce = env->cregs[1];
- break;
- case PSW_ASC_SECONDARY:
- PTE_DPRINTF("%s: asc=secondary\n", __func__);
- asce = env->cregs[7];
- break;
- case PSW_ASC_HOME:
- PTE_DPRINTF("%s: asc=home\n", __func__);
- asce = env->cregs[13];
- break;
- }
-
- switch (asce & _ASCE_TYPE_MASK) {
- case _ASCE_TYPE_REGION1:
- break;
- case _ASCE_TYPE_REGION2:
- if (vaddr & 0xffe0000000000000ULL) {
- DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
- " 0xffe0000000000000ULL\n", __func__, vaddr);
- trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
- return -1;
- }
- break;
- case _ASCE_TYPE_REGION3:
- if (vaddr & 0xfffffc0000000000ULL) {
- DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
- " 0xfffffc0000000000ULL\n", __func__, vaddr);
- trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
- return -1;
- }
- break;
- case _ASCE_TYPE_SEGMENT:
- if (vaddr & 0xffffffff80000000ULL) {
- DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
- " 0xffffffff80000000ULL\n", __func__, vaddr);
- trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
- return -1;
- }
- break;
- }
-
- /* fake level above current */
- level = asce & _ASCE_TYPE_MASK;
- new_level = level + 4;
- asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK);
-
- r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);
-
- if ((rw == 1) && !(*flags & PAGE_WRITE)) {
- trigger_prot_fault(env, vaddr, asc);
- return -1;
- }
-
- return r;
-}
-
-int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
- target_ulong *raddr, int *flags)
-{
- int r = -1;
- uint8_t *sk;
-
- *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- vaddr &= TARGET_PAGE_MASK;
-
- if (!(env->psw.mask & PSW_MASK_DAT)) {
- *raddr = vaddr;
- r = 0;
- goto out;
- }
-
- switch (asc) {
- case PSW_ASC_PRIMARY:
- case PSW_ASC_HOME:
- r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
- break;
- case PSW_ASC_SECONDARY:
- /*
- * Instruction: Primary
- * Data: Secondary
- */
- if (rw == 2) {
- r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
- rw);
- *flags &= ~(PAGE_READ | PAGE_WRITE);
- } else {
- r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
- rw);
- *flags &= ~(PAGE_EXEC);
- }
- break;
- case PSW_ASC_ACCREG:
- default:
- hw_error("guest switched to unknown asc mode\n");
- break;
- }
-
- out:
- /* Convert real address -> absolute address */
- if (*raddr < 0x2000) {
- *raddr = *raddr + env->psa;
- }
-
- if (*raddr <= ram_size) {
- sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
- if (*flags & PAGE_READ) {
- *sk |= SK_R;
- }
-
- if (*flags & PAGE_WRITE) {
- *sk |= SK_C;
- }
- }
-
- return r;
-}
-
-int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
- int rw, int mmu_idx)
-{
- uint64_t asc = env->psw.mask & PSW_MASK_ASC;
- target_ulong vaddr, raddr;
- int prot;
-
- DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
- __func__, _vaddr, rw, mmu_idx);
-
- orig_vaddr &= TARGET_PAGE_MASK;
- vaddr = orig_vaddr;
-
- /* 31-Bit mode */
- if (!(env->psw.mask & PSW_MASK_64)) {
- vaddr &= 0x7fffffff;
- }
-
- if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
- /* Translation ended in exception */
- return 1;
- }
-
- /* check out of RAM access */
- if (raddr > (ram_size + virtio_size)) {
- DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
- (uint64_t)aaddr, (uint64_t)ram_size);
- trigger_pgm_exception(env, PGM_ADDRESSING, ILC_LATER);
- return 1;
- }
-
- DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
- (uint64_t)vaddr, (uint64_t)raddr, prot);
-
- tlb_set_page(env, orig_vaddr, raddr, prot,
- mmu_idx, TARGET_PAGE_SIZE);
-
- return 0;
-}
-
-target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env,
- target_ulong vaddr)
-{
- target_ulong raddr;
- int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- int old_exc = env->exception_index;
- uint64_t asc = env->psw.mask & PSW_MASK_ASC;
-
- /* 31-Bit mode */
- if (!(env->psw.mask & PSW_MASK_64)) {
- vaddr &= 0x7fffffff;
- }
-
- mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
- env->exception_index = old_exc;
-
- return raddr;
-}
-
-void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
-{
- if (mask & PSW_MASK_WAIT) {
- if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
- if (s390_del_running_cpu(env) == 0) {
-#ifndef CONFIG_USER_ONLY
- qemu_system_shutdown_request();
-#endif
- }
- }
- env->halted = 1;
- env->exception_index = EXCP_HLT;
- }
-
- env->psw.addr = addr;
- env->psw.mask = mask;
- env->cc_op = (mask >> 13) & 3;
-}
-
-static uint64_t get_psw_mask(CPUS390XState *env)
-{
- uint64_t r = env->psw.mask;
-
- env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
-
- r &= ~(3ULL << 13);
- assert(!(env->cc_op & ~3));
- r |= env->cc_op << 13;
-
- return r;
-}
-
-static void do_svc_interrupt(CPUS390XState *env)
-{
- uint64_t mask, addr;
- LowCore *lowcore;
- target_phys_addr_t len = TARGET_PAGE_SIZE;
-
- lowcore = cpu_physical_memory_map(env->psa, &len, 1);
-
- lowcore->svc_code = cpu_to_be16(env->int_svc_code);
- lowcore->svc_ilc = cpu_to_be16(env->int_svc_ilc);
- lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
- lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + (env->int_svc_ilc));
- mask = be64_to_cpu(lowcore->svc_new_psw.mask);
- addr = be64_to_cpu(lowcore->svc_new_psw.addr);
-
- cpu_physical_memory_unmap(lowcore, len, 1, len);
-
- load_psw(env, mask, addr);
-}
-
-static void do_program_interrupt(CPUS390XState *env)
-{
- uint64_t mask, addr;
- LowCore *lowcore;
- target_phys_addr_t len = TARGET_PAGE_SIZE;
- int ilc = env->int_pgm_ilc;
-
- switch (ilc) {
- case ILC_LATER:
- ilc = get_ilc(cpu_ldub_code(env, env->psw.addr));
- break;
- case ILC_LATER_INC:
- ilc = get_ilc(cpu_ldub_code(env, env->psw.addr));
- env->psw.addr += ilc * 2;
- break;
- case ILC_LATER_INC_2:
- ilc = get_ilc(cpu_ldub_code(env, env->psw.addr)) * 2;
- env->psw.addr += ilc;
- break;
- }
-
- qemu_log("%s: code=0x%x ilc=%d\n", __func__, env->int_pgm_code, ilc);
-
- lowcore = cpu_physical_memory_map(env->psa, &len, 1);
-
- lowcore->pgm_ilc = cpu_to_be16(ilc);
- lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
- lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
- lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
- mask = be64_to_cpu(lowcore->program_new_psw.mask);
- addr = be64_to_cpu(lowcore->program_new_psw.addr);
-
- cpu_physical_memory_unmap(lowcore, len, 1, len);
-
- DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
- env->int_pgm_code, ilc, env->psw.mask,
- env->psw.addr);
-
- load_psw(env, mask, addr);
-}
-
-#define VIRTIO_SUBCODE_64 0x0D00
-
-static void do_ext_interrupt(CPUS390XState *env)
-{
- uint64_t mask, addr;
- LowCore *lowcore;
- target_phys_addr_t len = TARGET_PAGE_SIZE;
- ExtQueue *q;
-
- if (!(env->psw.mask & PSW_MASK_EXT)) {
- cpu_abort(env, "Ext int w/o ext mask\n");
- }
-
- if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
- cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
- }
-
- q = &env->ext_queue[env->ext_index];
- lowcore = cpu_physical_memory_map(env->psa, &len, 1);
-
- lowcore->ext_int_code = cpu_to_be16(q->code);
- lowcore->ext_params = cpu_to_be32(q->param);
- lowcore->ext_params2 = cpu_to_be64(q->param64);
- lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
- lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
- lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
- mask = be64_to_cpu(lowcore->external_new_psw.mask);
- addr = be64_to_cpu(lowcore->external_new_psw.addr);
-
- cpu_physical_memory_unmap(lowcore, len, 1, len);
-
- env->ext_index--;
- if (env->ext_index == -1) {
- env->pending_int &= ~INTERRUPT_EXT;
- }
-
- DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
- env->psw.mask, env->psw.addr);
-
- load_psw(env, mask, addr);
-}
-
-void do_interrupt(CPUS390XState *env)
-{
- qemu_log("%s: %d at pc=%" PRIx64 "\n", __func__, env->exception_index,
- env->psw.addr);
-
- s390_add_running_cpu(env);
- /* handle external interrupts */
- if ((env->psw.mask & PSW_MASK_EXT) &&
- env->exception_index == -1) {
- if (env->pending_int & INTERRUPT_EXT) {
- /* code is already in env */
- env->exception_index = EXCP_EXT;
- } else if (env->pending_int & INTERRUPT_TOD) {
- cpu_inject_ext(env, 0x1004, 0, 0);
- env->exception_index = EXCP_EXT;
- env->pending_int &= ~INTERRUPT_EXT;
- env->pending_int &= ~INTERRUPT_TOD;
- } else if (env->pending_int & INTERRUPT_CPUTIMER) {
- cpu_inject_ext(env, 0x1005, 0, 0);
- env->exception_index = EXCP_EXT;
- env->pending_int &= ~INTERRUPT_EXT;
- env->pending_int &= ~INTERRUPT_TOD;
- }
- }
-
- switch (env->exception_index) {
- case EXCP_PGM:
- do_program_interrupt(env);
- break;
- case EXCP_SVC:
- do_svc_interrupt(env);
- break;
- case EXCP_EXT:
- do_ext_interrupt(env);
- break;
- }
- env->exception_index = -1;
-
- if (!env->pending_int) {
- env->interrupt_request &= ~CPU_INTERRUPT_HARD;
- }
-}
-
-#endif /* CONFIG_USER_ONLY */
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index 2938ac9..f405b97 100644
--- a/target-s390x/misc_helper.c
+++ b/target-s390x/misc_helper.c
@@ -22,6 +22,7 @@
#include "memory.h"
#include "cputlb.h"
#include "host-utils.h"
+#include "gdbstub.h"
#include "helper.h"
#include <string.h>
#include "kvm.h"
@@ -43,6 +44,31 @@
#endif
/* raise an exception */
+//#define DEBUG_S390
+//#define DEBUG_S390_PTE
+//#define DEBUG_S390_STDOUT
+
+#ifdef DEBUG_S390
+#ifdef DEBUG_S390_STDOUT
+#define DPRINTF(fmt, ...) \
+ do { fprintf(stderr, fmt, ## __VA_ARGS__); \
+ qemu_log(fmt, ##__VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) \
+ do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
+#endif
+#else
+#define DPRINTF(fmt, ...) \
+ do { } while (0)
+#endif
+
+#ifdef DEBUG_S390_PTE
+#define PTE_DPRINTF DPRINTF
+#else
+#define PTE_DPRINTF(fmt, ...) \
+ do { } while (0)
+#endif
+
void HELPER(exception)(CPUS390XState *env, uint32_t excp)
{
HELPER_LOG("%s: exception %d\n", __func__, excp);
@@ -50,7 +76,533 @@ void HELPER(exception)(CPUS390XState *env, uint32_t excp)
cpu_loop_exit(env);
}
+#if defined(CONFIG_USER_ONLY)
+
+void do_interrupt(CPUS390XState *env)
+{
+ env->exception_index = -1;
+}
+
+int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
+ int rw, int mmu_idx)
+{
+ /* fprintf(stderr, "%s: address 0x%lx rw %d mmu_idx %d\n",
+ __func__, address, rw, mmu_idx); */
+ env->exception_index = EXCP_ADDR;
+ /* FIXME: find out how this works on a real machine */
+ env->__excp_addr = address;
+ return 1;
+}
+
+#else /* !CONFIG_USER_ONLY */
+
+/* Ensure to exit the TB after this call! */
+static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
+ uint32_t ilc)
+{
+ env->exception_index = EXCP_PGM;
+ env->int_pgm_code = code;
+ env->int_pgm_ilc = ilc;
+}
+
+static int trans_bits(CPUS390XState *env, uint64_t mode)
+{
+ int bits = 0;
+
+ switch (mode) {
+ case PSW_ASC_PRIMARY:
+ bits = 1;
+ break;
+ case PSW_ASC_SECONDARY:
+ bits = 2;
+ break;
+ case PSW_ASC_HOME:
+ bits = 3;
+ break;
+ default:
+ cpu_abort(env, "unknown asc mode\n");
+ break;
+ }
+
+ return bits;
+}
+
+static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
+ uint64_t mode)
+{
+ int ilc = ILC_LATER_INC_2;
+ int bits = trans_bits(env, mode) | 4;
+
+ DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
+
+ stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
+ trigger_pgm_exception(env, PGM_PROTECTION, ilc);
+}
+
+static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
+ uint32_t type, uint64_t asc, int rw)
+{
+ int ilc = ILC_LATER;
+ int bits = trans_bits(env, asc);
+
+ if (rw == 2) {
+ /* code has is undefined ilc */
+ ilc = 2;
+ }
+
+ DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
+
+ stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
+ trigger_pgm_exception(env, type, ilc);
+}
+
+static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
+ uint64_t asc, uint64_t asce, int level,
+ target_ulong *raddr, int *flags, int rw)
+{
+ uint64_t offs = 0;
+ uint64_t origin;
+ uint64_t new_asce;
+
+ PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);
+
+ if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
+ ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
+ /* XXX different regions have different faults */
+ DPRINTF("%s: invalid region\n", __func__);
+ trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
+ return -1;
+ }
+
+ if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
+ trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
+ return -1;
+ }
+
+ if (asce & _ASCE_REAL_SPACE) {
+ /* direct mapping */
+
+ *raddr = vaddr;
+ return 0;
+ }
+
+ origin = asce & _ASCE_ORIGIN;
+
+ switch (level) {
+ case _ASCE_TYPE_REGION1 + 4:
+ offs = (vaddr >> 50) & 0x3ff8;
+ break;
+ case _ASCE_TYPE_REGION1:
+ offs = (vaddr >> 39) & 0x3ff8;
+ break;
+ case _ASCE_TYPE_REGION2:
+ offs = (vaddr >> 28) & 0x3ff8;
+ break;
+ case _ASCE_TYPE_REGION3:
+ offs = (vaddr >> 17) & 0x3ff8;
+ break;
+ case _ASCE_TYPE_SEGMENT:
+ offs = (vaddr >> 9) & 0x07f8;
+ origin = asce & _SEGMENT_ENTRY_ORIGIN;
+ break;
+ }
+
+ /* XXX region protection flags */
+ /* *flags &= ~PAGE_WRITE */
+
+ new_asce = ldq_phys(origin + offs);
+ PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
+ __func__, origin, offs, new_asce);
+
+ if (level != _ASCE_TYPE_SEGMENT) {
+ /* yet another region */
+ return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
+ flags, rw);
+ }
+
+ /* PTE */
+ if (new_asce & _PAGE_INVALID) {
+ DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce);
+ trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
+ return -1;
+ }
+
+ if (new_asce & _PAGE_RO) {
+ *flags &= ~PAGE_WRITE;
+ }
+
+ *raddr = new_asce & _ASCE_ORIGIN;
+
+ PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce);
+
+ return 0;
+}
+
+static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
+ uint64_t asc, target_ulong *raddr, int *flags,
+ int rw)
+{
+ uint64_t asce = 0;
+ int level, new_level;
+ int r;
+
+ switch (asc) {
+ case PSW_ASC_PRIMARY:
+ PTE_DPRINTF("%s: asc=primary\n", __func__);
+ asce = env->cregs[1];
+ break;
+ case PSW_ASC_SECONDARY:
+ PTE_DPRINTF("%s: asc=secondary\n", __func__);
+ asce = env->cregs[7];
+ break;
+ case PSW_ASC_HOME:
+ PTE_DPRINTF("%s: asc=home\n", __func__);
+ asce = env->cregs[13];
+ break;
+ }
+
+ switch (asce & _ASCE_TYPE_MASK) {
+ case _ASCE_TYPE_REGION1:
+ break;
+ case _ASCE_TYPE_REGION2:
+ if (vaddr & 0xffe0000000000000ULL) {
+ DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
+ " 0xffe0000000000000ULL\n", __func__, vaddr);
+ trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
+ return -1;
+ }
+ break;
+ case _ASCE_TYPE_REGION3:
+ if (vaddr & 0xfffffc0000000000ULL) {
+ DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
+ " 0xfffffc0000000000ULL\n", __func__, vaddr);
+ trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
+ return -1;
+ }
+ break;
+ case _ASCE_TYPE_SEGMENT:
+ if (vaddr & 0xffffffff80000000ULL) {
+ DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
+ " 0xffffffff80000000ULL\n", __func__, vaddr);
+ trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
+ return -1;
+ }
+ break;
+ }
+
+ /* fake level above current */
+ level = asce & _ASCE_TYPE_MASK;
+ new_level = level + 4;
+ asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK);
+
+ r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);
+
+ if ((rw == 1) && !(*flags & PAGE_WRITE)) {
+ trigger_prot_fault(env, vaddr, asc);
+ return -1;
+ }
+
+ return r;
+}
+
+int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
+ target_ulong *raddr, int *flags)
+{
+ int r = -1;
+ uint8_t *sk;
+
+ *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ vaddr &= TARGET_PAGE_MASK;
+
+ if (!(env->psw.mask & PSW_MASK_DAT)) {
+ *raddr = vaddr;
+ r = 0;
+ goto out;
+ }
+
+ switch (asc) {
+ case PSW_ASC_PRIMARY:
+ case PSW_ASC_HOME:
+ r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
+ break;
+ case PSW_ASC_SECONDARY:
+ /*
+ * Instruction: Primary
+ * Data: Secondary
+ */
+ if (rw == 2) {
+ r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
+ rw);
+ *flags &= ~(PAGE_READ | PAGE_WRITE);
+ } else {
+ r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
+ rw);
+ *flags &= ~(PAGE_EXEC);
+ }
+ break;
+ case PSW_ASC_ACCREG:
+ default:
+ hw_error("guest switched to unknown asc mode\n");
+ break;
+ }
+
+ out:
+ /* Convert real address -> absolute address */
+ if (*raddr < 0x2000) {
+ *raddr = *raddr + env->psa;
+ }
+
+ if (*raddr <= ram_size) {
+ sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
+ if (*flags & PAGE_READ) {
+ *sk |= SK_R;
+ }
+
+ if (*flags & PAGE_WRITE) {
+ *sk |= SK_C;
+ }
+ }
+
+ return r;
+}
+
+int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
+ int rw, int mmu_idx)
+{
+ uint64_t asc = env->psw.mask & PSW_MASK_ASC;
+ target_ulong vaddr, raddr;
+ int prot;
+
+ DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
+ __func__, _vaddr, rw, mmu_idx);
+
+ orig_vaddr &= TARGET_PAGE_MASK;
+ vaddr = orig_vaddr;
+
+ /* 31-Bit mode */
+ if (!(env->psw.mask & PSW_MASK_64)) {
+ vaddr &= 0x7fffffff;
+ }
+
+ if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
+ /* Translation ended in exception */
+ return 1;
+ }
+
+ /* check out of RAM access */
+ if (raddr > (ram_size + virtio_size)) {
+ DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
+ (uint64_t)aaddr, (uint64_t)ram_size);
+ trigger_pgm_exception(env, PGM_ADDRESSING, ILC_LATER);
+ return 1;
+ }
+
+ DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
+ (uint64_t)vaddr, (uint64_t)raddr, prot);
+
+ tlb_set_page(env, orig_vaddr, raddr, prot,
+ mmu_idx, TARGET_PAGE_SIZE);
+
+ return 0;
+}
+
+target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env,
+ target_ulong vaddr)
+{
+ target_ulong raddr;
+ int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ int old_exc = env->exception_index;
+ uint64_t asc = env->psw.mask & PSW_MASK_ASC;
+
+ /* 31-Bit mode */
+ if (!(env->psw.mask & PSW_MASK_64)) {
+ vaddr &= 0x7fffffff;
+ }
+
+ mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
+ env->exception_index = old_exc;
+
+ return raddr;
+}
+
+void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
+{
+ if (mask & PSW_MASK_WAIT) {
+ if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
+ if (s390_del_running_cpu(env) == 0) {
#ifndef CONFIG_USER_ONLY
+ qemu_system_shutdown_request();
+#endif
+ }
+ }
+ env->halted = 1;
+ env->exception_index = EXCP_HLT;
+ }
+
+ env->psw.addr = addr;
+ env->psw.mask = mask;
+ env->cc_op = (mask >> 13) & 3;
+}
+
+static uint64_t get_psw_mask(CPUS390XState *env)
+{
+ uint64_t r = env->psw.mask;
+
+ env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
+
+ r &= ~(3ULL << 13);
+ assert(!(env->cc_op & ~3));
+ r |= env->cc_op << 13;
+
+ return r;
+}
+
+static void do_svc_interrupt(CPUS390XState *env)
+{
+ uint64_t mask, addr;
+ LowCore *lowcore;
+ target_phys_addr_t len = TARGET_PAGE_SIZE;
+
+ lowcore = cpu_physical_memory_map(env->psa, &len, 1);
+
+ lowcore->svc_code = cpu_to_be16(env->int_svc_code);
+ lowcore->svc_ilc = cpu_to_be16(env->int_svc_ilc);
+ lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
+ lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + (env->int_svc_ilc));
+ mask = be64_to_cpu(lowcore->svc_new_psw.mask);
+ addr = be64_to_cpu(lowcore->svc_new_psw.addr);
+
+ cpu_physical_memory_unmap(lowcore, len, 1, len);
+
+ load_psw(env, mask, addr);
+}
+
+static void do_program_interrupt(CPUS390XState *env)
+{
+ uint64_t mask, addr;
+ LowCore *lowcore;
+ target_phys_addr_t len = TARGET_PAGE_SIZE;
+ int ilc = env->int_pgm_ilc;
+
+ switch (ilc) {
+ case ILC_LATER:
+ ilc = get_ilc(cpu_ldub_code(env, env->psw.addr));
+ break;
+ case ILC_LATER_INC:
+ ilc = get_ilc(cpu_ldub_code(env, env->psw.addr));
+ env->psw.addr += ilc * 2;
+ break;
+ case ILC_LATER_INC_2:
+ ilc = get_ilc(cpu_ldub_code(env, env->psw.addr)) * 2;
+ env->psw.addr += ilc;
+ break;
+ }
+
+ qemu_log("%s: code=0x%x ilc=%d\n", __func__, env->int_pgm_code, ilc);
+
+ lowcore = cpu_physical_memory_map(env->psa, &len, 1);
+
+ lowcore->pgm_ilc = cpu_to_be16(ilc);
+ lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
+ lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
+ lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
+ mask = be64_to_cpu(lowcore->program_new_psw.mask);
+ addr = be64_to_cpu(lowcore->program_new_psw.addr);
+
+ cpu_physical_memory_unmap(lowcore, len, 1, len);
+
+ DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
+ env->int_pgm_code, ilc, env->psw.mask,
+ env->psw.addr);
+
+ load_psw(env, mask, addr);
+}
+
+#define VIRTIO_SUBCODE_64 0x0D00
+
+static void do_ext_interrupt(CPUS390XState *env)
+{
+ uint64_t mask, addr;
+ LowCore *lowcore;
+ target_phys_addr_t len = TARGET_PAGE_SIZE;
+ ExtQueue *q;
+
+ if (!(env->psw.mask & PSW_MASK_EXT)) {
+ cpu_abort(env, "Ext int w/o ext mask\n");
+ }
+
+ if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
+ cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
+ }
+
+ q = &env->ext_queue[env->ext_index];
+ lowcore = cpu_physical_memory_map(env->psa, &len, 1);
+
+ lowcore->ext_int_code = cpu_to_be16(q->code);
+ lowcore->ext_params = cpu_to_be32(q->param);
+ lowcore->ext_params2 = cpu_to_be64(q->param64);
+ lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
+ lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
+ lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
+ mask = be64_to_cpu(lowcore->external_new_psw.mask);
+ addr = be64_to_cpu(lowcore->external_new_psw.addr);
+
+ cpu_physical_memory_unmap(lowcore, len, 1, len);
+
+ env->ext_index--;
+ if (env->ext_index == -1) {
+ env->pending_int &= ~INTERRUPT_EXT;
+ }
+
+ DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
+ env->psw.mask, env->psw.addr);
+
+ load_psw(env, mask, addr);
+}
+
+void do_interrupt(CPUS390XState *env)
+{
+ qemu_log("%s: %d at pc=%" PRIx64 "\n", __func__, env->exception_index,
+ env->psw.addr);
+
+ s390_add_running_cpu(env);
+ /* handle external interrupts */
+ if ((env->psw.mask & PSW_MASK_EXT) &&
+ env->exception_index == -1) {
+ if (env->pending_int & INTERRUPT_EXT) {
+ /* code is already in env */
+ env->exception_index = EXCP_EXT;
+ } else if (env->pending_int & INTERRUPT_TOD) {
+ cpu_inject_ext(env, 0x1004, 0, 0);
+ env->exception_index = EXCP_EXT;
+ env->pending_int &= ~INTERRUPT_EXT;
+ env->pending_int &= ~INTERRUPT_TOD;
+ } else if (env->pending_int & INTERRUPT_CPUTIMER) {
+ cpu_inject_ext(env, 0x1005, 0, 0);
+ env->exception_index = EXCP_EXT;
+ env->pending_int &= ~INTERRUPT_EXT;
+ env->pending_int &= ~INTERRUPT_TOD;
+ }
+ }
+
+ switch (env->exception_index) {
+ case EXCP_PGM:
+ do_program_interrupt(env);
+ break;
+ case EXCP_SVC:
+ do_svc_interrupt(env);
+ break;
+ case EXCP_EXT:
+ do_ext_interrupt(env);
+ break;
+ }
+ env->exception_index = -1;
+
+ if (!env->pending_int) {
+ env->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ }
+}
+
void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
{
qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
@@ -427,4 +979,22 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
return cc;
}
+
+void s390x_tod_timer(void *opaque)
+{
+ S390CPU *cpu = opaque;
+ CPUS390XState *env = &cpu->env;
+
+ env->pending_int |= INTERRUPT_TOD;
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+}
+
+void s390x_cpu_timer(void *opaque)
+{
+ S390CPU *cpu = opaque;
+ CPUS390XState *env = &cpu->env;
+
+ env->pending_int |= INTERRUPT_CPUTIMER;
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+}
#endif
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 13/21] target-lm32: switch to AREG0 free mode
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (11 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 12/21] target-s390x: split helper.c Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 14/21] target-m68k: " Blue Swirl
` (8 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Michael Walle
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
configure | 2 +-
target-lm32/Makefile.objs | 2 --
target-lm32/helper.h | 20 ++++++++++----------
target-lm32/op_helper.c | 29 +++++++++++------------------
target-lm32/translate.c | 22 +++++++++++-----------
5 files changed, 33 insertions(+), 42 deletions(-)
diff --git a/configure b/configure
index a88a465..9261f68 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
case "$target_arch2" in
- alpha | i386 | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
+ alpha | i386 | lm32 | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
;;
esac
diff --git a/target-lm32/Makefile.objs b/target-lm32/Makefile.objs
index 2e0e093..ca20f21 100644
--- a/target-lm32/Makefile.objs
+++ b/target-lm32/Makefile.objs
@@ -1,4 +1,2 @@
obj-y += translate.o op_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-lm32/helper.h b/target-lm32/helper.h
index 9d335ef..07f5670 100644
--- a/target-lm32/helper.h
+++ b/target-lm32/helper.h
@@ -1,14 +1,14 @@
#include "def-helper.h"
-DEF_HELPER_1(raise_exception, void, i32)
-DEF_HELPER_0(hlt, void)
-DEF_HELPER_1(wcsr_im, void, i32)
-DEF_HELPER_1(wcsr_ip, void, i32)
-DEF_HELPER_1(wcsr_jtx, void, i32)
-DEF_HELPER_1(wcsr_jrx, void, i32)
-DEF_HELPER_0(rcsr_im, i32)
-DEF_HELPER_0(rcsr_ip, i32)
-DEF_HELPER_0(rcsr_jtx, i32)
-DEF_HELPER_0(rcsr_jrx, i32)
+DEF_HELPER_2(raise_exception, void, env, i32)
+DEF_HELPER_1(hlt, void, env)
+DEF_HELPER_2(wcsr_im, void, env, i32)
+DEF_HELPER_2(wcsr_ip, void, env, i32)
+DEF_HELPER_2(wcsr_jtx, void, env, i32)
+DEF_HELPER_2(wcsr_jrx, void, env, i32)
+DEF_HELPER_1(rcsr_im, i32, env)
+DEF_HELPER_1(rcsr_ip, i32, env)
+DEF_HELPER_1(rcsr_jtx, i32, env)
+DEF_HELPER_1(rcsr_jrx, i32, env)
#include "def-helper.h"
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index 51edc1a..7b91d8c 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -1,6 +1,5 @@
#include <assert.h>
#include "cpu.h"
-#include "dyngen-exec.h"
#include "helper.h"
#include "host-utils.h"
@@ -18,55 +17,55 @@
#define SHIFT 3
#include "softmmu_template.h"
-void helper_raise_exception(uint32_t index)
+void helper_raise_exception(CPULM32State *env, uint32_t index)
{
env->exception_index = index;
cpu_loop_exit(env);
}
-void helper_hlt(void)
+void helper_hlt(CPULM32State *env)
{
env->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit(env);
}
-void helper_wcsr_im(uint32_t im)
+void helper_wcsr_im(CPULM32State *env, uint32_t im)
{
lm32_pic_set_im(env->pic_state, im);
}
-void helper_wcsr_ip(uint32_t im)
+void helper_wcsr_ip(CPULM32State *env, uint32_t im)
{
lm32_pic_set_ip(env->pic_state, im);
}
-void helper_wcsr_jtx(uint32_t jtx)
+void helper_wcsr_jtx(CPULM32State *env, uint32_t jtx)
{
lm32_juart_set_jtx(env->juart_state, jtx);
}
-void helper_wcsr_jrx(uint32_t jrx)
+void helper_wcsr_jrx(CPULM32State *env, uint32_t jrx)
{
lm32_juart_set_jrx(env->juart_state, jrx);
}
-uint32_t helper_rcsr_im(void)
+uint32_t helper_rcsr_im(CPULM32State *env)
{
return lm32_pic_get_im(env->pic_state);
}
-uint32_t helper_rcsr_ip(void)
+uint32_t helper_rcsr_ip(CPULM32State *env)
{
return lm32_pic_get_ip(env->pic_state);
}
-uint32_t helper_rcsr_jtx(void)
+uint32_t helper_rcsr_jtx(CPULM32State *env)
{
return lm32_juart_get_jtx(env->juart_state);
}
-uint32_t helper_rcsr_jrx(void)
+uint32_t helper_rcsr_jrx(CPULM32State *env)
{
return lm32_juart_get_jrx(env->juart_state);
}
@@ -74,17 +73,12 @@ uint32_t helper_rcsr_jrx(void)
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPULM32State *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPULM32State *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
TranslationBlock *tb;
- CPULM32State *saved_env;
int ret;
- saved_env = env;
- env = env1;
-
ret = cpu_lm32_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
@@ -98,7 +92,6 @@ void tlb_fill(CPULM32State *env1, target_ulong addr, int is_write, int mmu_idx,
}
cpu_loop_exit(env);
}
- env = saved_env;
}
#endif
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 872a2ba..b9ae277 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -116,7 +116,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
{
TCGv_i32 tmp = tcg_const_i32(index);
- gen_helper_raise_exception(tmp);
+ gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
}
@@ -179,7 +179,7 @@ static void dec_and(DisasContext *dc)
} else {
if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) {
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
- gen_helper_hlt();
+ gen_helper_hlt(cpu_env);
} else {
tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
}
@@ -601,10 +601,10 @@ static void dec_rcsr(DisasContext *dc)
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie);
break;
case CSR_IM:
- gen_helper_rcsr_im(cpu_R[dc->r2]);
+ gen_helper_rcsr_im(cpu_R[dc->r2], cpu_env);
break;
case CSR_IP:
- gen_helper_rcsr_ip(cpu_R[dc->r2]);
+ gen_helper_rcsr_ip(cpu_R[dc->r2], cpu_env);
break;
case CSR_CC:
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc);
@@ -622,10 +622,10 @@ static void dec_rcsr(DisasContext *dc)
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba);
break;
case CSR_JTX:
- gen_helper_rcsr_jtx(cpu_R[dc->r2]);
+ gen_helper_rcsr_jtx(cpu_R[dc->r2], cpu_env);
break;
case CSR_JRX:
- gen_helper_rcsr_jrx(cpu_R[dc->r2]);
+ gen_helper_rcsr_jrx(cpu_R[dc->r2], cpu_env);
break;
case CSR_ICC:
case CSR_DCC:
@@ -812,7 +812,7 @@ static void dec_wcsr(DisasContext *dc)
if (use_icount) {
gen_io_start();
}
- gen_helper_wcsr_im(cpu_R[dc->r1]);
+ gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]);
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
if (use_icount) {
gen_io_end();
@@ -824,7 +824,7 @@ static void dec_wcsr(DisasContext *dc)
if (use_icount) {
gen_io_start();
}
- gen_helper_wcsr_ip(cpu_R[dc->r1]);
+ gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]);
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
if (use_icount) {
gen_io_end();
@@ -844,10 +844,10 @@ static void dec_wcsr(DisasContext *dc)
tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]);
break;
case CSR_JTX:
- gen_helper_wcsr_jtx(cpu_R[dc->r1]);
+ gen_helper_wcsr_jtx(cpu_env, cpu_R[dc->r1]);
break;
case CSR_JRX:
- gen_helper_wcsr_jrx(cpu_R[dc->r1]);
+ gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]);
break;
case CSR_DC:
tcg_gen_mov_tl(cpu_dc, cpu_R[dc->r1]);
@@ -948,7 +948,7 @@ static inline void decode(DisasContext *dc)
tcg_gen_debug_insn_start(dc->pc);
}
- dc->ir = ir = ldl_code(dc->pc);
+ dc->ir = ir = cpu_ldl_code(cpu_single_env, dc->pc);
LOG_DIS("%8.8x\t", dc->ir);
/* try guessing 'empty' instruction memory, although it may be a valid
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 14/21] target-m68k: switch to AREG0 free mode
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (12 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 13/21] target-lm32: switch to AREG0 free mode Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 17:33 ` [Qemu-devel] [PATCH 15/21] target-unicore32: " Blue Swirl
` (7 subsequent siblings)
21 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Paul Brook
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
configure | 2 +-
target-m68k/Makefile.objs | 2 -
target-m68k/helpers.h | 2 +-
target-m68k/op_helper.c | 68 ++++++++++++++++------------------------
target-m68k/translate.c | 76 +++++++++++++++++++++++----------------------
5 files changed, 68 insertions(+), 82 deletions(-)
diff --git a/configure b/configure
index 9261f68..350b47c 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
case "$target_arch2" in
- alpha | i386 | lm32 | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
+ alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
;;
esac
diff --git a/target-m68k/Makefile.objs b/target-m68k/Makefile.objs
index cda6015..7eccfab 100644
--- a/target-m68k/Makefile.objs
+++ b/target-m68k/Makefile.objs
@@ -1,5 +1,3 @@
obj-y += m68k-semi.o
obj-y += translate.o op_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index cb8a0c7..8112b44 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -49,6 +49,6 @@ DEF_HELPER_3(set_mac_exts, void, env, i32, i32)
DEF_HELPER_3(set_mac_extu, void, env, i32, i32)
DEF_HELPER_2(flush_flags, void, env, i32)
-DEF_HELPER_1(raise_exception, void, i32)
+DEF_HELPER_2(raise_exception, void, env, i32)
#include "def-helper.h"
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 1971a57..3116287 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -17,17 +17,16 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "cpu.h"
-#include "dyngen-exec.h"
#include "helpers.h"
#if defined(CONFIG_USER_ONLY)
-void do_interrupt(CPUM68KState *env1)
+void do_interrupt(CPUM68KState *env)
{
- env1->exception_index = -1;
+ env->exception_index = -1;
}
-void do_interrupt_m68k_hardirq(CPUM68KState *env1)
+void do_interrupt_m68k_hardirq(CPUM68KState *env)
{
}
@@ -54,16 +53,12 @@ extern int semihosting_enabled;
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUM68KState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUM68KState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
TranslationBlock *tb;
- CPUM68KState *saved_env;
int ret;
- saved_env = env;
- env = env1;
ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
@@ -77,24 +72,23 @@ void tlb_fill(CPUM68KState *env1, target_ulong addr, int is_write, int mmu_idx,
}
cpu_loop_exit(env);
}
- env = saved_env;
}
-static void do_rte(void)
+static void do_rte(CPUM68KState *env)
{
uint32_t sp;
uint32_t fmt;
sp = env->aregs[7];
- fmt = ldl_kernel(sp);
- env->pc = ldl_kernel(sp + 4);
+ fmt = cpu_ldl_kernel(env, sp);
+ env->pc = cpu_ldl_kernel(env, sp + 4);
sp |= (fmt >> 28) & 3;
env->sr = fmt & 0xffff;
m68k_switch_sp(env);
env->aregs[7] = sp + 8;
}
-static void do_interrupt_all(int is_hw)
+static void do_interrupt_all(CPUM68KState *env, int is_hw)
{
uint32_t sp;
uint32_t fmt;
@@ -108,14 +102,14 @@ static void do_interrupt_all(int is_hw)
switch (env->exception_index) {
case EXCP_RTE:
/* Return from an exception. */
- do_rte();
+ do_rte(env);
return;
case EXCP_HALT_INSN:
if (semihosting_enabled
&& (env->sr & SR_S) != 0
&& (env->pc & 3) == 0
- && lduw_code(env->pc - 4) == 0x4e71
- && ldl_code(env->pc) == 0x4e7bf000) {
+ && cpu_lduw_code(env, env->pc - 4) == 0x4e71
+ && cpu_ldl_code(env, env->pc) == 0x4e7bf000) {
env->pc += 4;
do_m68k_semihosting(env, env->dregs[0]);
return;
@@ -151,44 +145,34 @@ static void do_interrupt_all(int is_hw)
/* ??? This could cause MMU faults. */
sp &= ~3;
sp -= 4;
- stl_kernel(sp, retaddr);
+ cpu_stl_kernel(env, sp, retaddr);
sp -= 4;
- stl_kernel(sp, fmt);
+ cpu_stl_kernel(env, sp, fmt);
env->aregs[7] = sp;
/* Jump to vector. */
- env->pc = ldl_kernel(env->vbr + vector);
+ env->pc = cpu_ldl_kernel(env, env->vbr + vector);
}
-void do_interrupt(CPUM68KState *env1)
+void do_interrupt(CPUM68KState *env)
{
- CPUM68KState *saved_env;
-
- saved_env = env;
- env = env1;
- do_interrupt_all(0);
- env = saved_env;
+ do_interrupt_all(env, 0);
}
-void do_interrupt_m68k_hardirq(CPUM68KState *env1)
+void do_interrupt_m68k_hardirq(CPUM68KState *env)
{
- CPUM68KState *saved_env;
-
- saved_env = env;
- env = env1;
- do_interrupt_all(1);
- env = saved_env;
+ do_interrupt_all(env, 1);
}
#endif
-static void raise_exception(int tt)
+static void raise_exception(CPUM68KState *env, int tt)
{
env->exception_index = tt;
cpu_loop_exit(env);
}
-void HELPER(raise_exception)(uint32_t tt)
+void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt)
{
- raise_exception(tt);
+ raise_exception(env, tt);
}
void HELPER(divu)(CPUM68KState *env, uint32_t word)
@@ -202,8 +186,9 @@ void HELPER(divu)(CPUM68KState *env, uint32_t word)
num = env->div1;
den = env->div2;
/* ??? This needs to make sure the throwing location is accurate. */
- if (den == 0)
- raise_exception(EXCP_DIV0);
+ if (den == 0) {
+ raise_exception(env, EXCP_DIV0);
+ }
quot = num / den;
rem = num % den;
flags = 0;
@@ -231,8 +216,9 @@ void HELPER(divs)(CPUM68KState *env, uint32_t word)
num = env->div1;
den = env->div2;
- if (den == 0)
- raise_exception(EXCP_DIV0);
+ if (den == 0) {
+ raise_exception(env, EXCP_DIV0);
+ }
quot = num / den;
rem = num % den;
flags = 0;
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 9fc1e31..10bb303 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -260,9 +260,9 @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
static inline uint32_t read_im32(DisasContext *s)
{
uint32_t im;
- im = ((uint32_t)lduw_code(s->pc)) << 16;
+ im = ((uint32_t)cpu_lduw_code(cpu_single_env, s->pc)) << 16;
s->pc += 2;
- im |= lduw_code(s->pc);
+ im |= cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
return im;
}
@@ -297,7 +297,7 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
uint32_t bd, od;
offset = s->pc;
- ext = lduw_code(s->pc);
+ ext = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
@@ -311,7 +311,7 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
if ((ext & 0x30) > 0x10) {
/* base displacement */
if ((ext & 0x30) == 0x20) {
- bd = (int16_t)lduw_code(s->pc);
+ bd = (int16_t)cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
} else {
bd = read_im32(s);
@@ -360,7 +360,7 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
if ((ext & 3) > 1) {
/* outer displacement */
if ((ext & 3) == 2) {
- od = (int16_t)lduw_code(s->pc);
+ od = (int16_t)cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
} else {
od = read_im32(s);
@@ -514,7 +514,7 @@ static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
case 5: /* Indirect displacement. */
reg = AREG(insn, 0);
tmp = tcg_temp_new();
- ext = lduw_code(s->pc);
+ ext = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
return tmp;
@@ -524,7 +524,7 @@ static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
case 7: /* Other */
switch (insn & 7) {
case 0: /* Absolute short. */
- offset = ldsw_code(s->pc);
+ offset = cpu_ldsw_code(cpu_single_env, s->pc);
s->pc += 2;
return tcg_const_i32(offset);
case 1: /* Absolute long. */
@@ -532,7 +532,7 @@ static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
return tcg_const_i32(offset);
case 2: /* pc displacement */
offset = s->pc;
- offset += ldsw_code(s->pc);
+ offset += cpu_ldsw_code(cpu_single_env, s->pc);
s->pc += 2;
return tcg_const_i32(offset);
case 3: /* pc index+displacement. */
@@ -638,17 +638,19 @@ static TCGv gen_ea(DisasContext *s, uint16_t insn, int opsize, TCGv val,
/* Sign extend values for consistency. */
switch (opsize) {
case OS_BYTE:
- if (what == EA_LOADS)
- offset = ldsb_code(s->pc + 1);
- else
- offset = ldub_code(s->pc + 1);
+ if (what == EA_LOADS) {
+ offset = cpu_ldsb_code(cpu_single_env, s->pc + 1);
+ } else {
+ offset = cpu_ldub_code(cpu_single_env, s->pc + 1);
+ }
s->pc += 2;
break;
case OS_WORD:
- if (what == EA_LOADS)
- offset = ldsw_code(s->pc);
- else
- offset = lduw_code(s->pc);
+ if (what == EA_LOADS) {
+ offset = cpu_ldsw_code(cpu_single_env, s->pc);
+ } else {
+ offset = cpu_lduw_code(cpu_single_env, s->pc);
+ }
s->pc += 2;
break;
case OS_LONG:
@@ -815,7 +817,7 @@ static void gen_exception(DisasContext *s, uint32_t where, int nr)
{
gen_flush_cc_op(s);
gen_jmp_im(s, where);
- gen_helper_raise_exception(tcg_const_i32(nr));
+ gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
}
static inline void gen_addr_fault(DisasContext *s)
@@ -934,7 +936,7 @@ DISAS_INSN(divl)
TCGv reg;
uint16_t ext;
- ext = lduw_code(s->pc);
+ ext = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
if (ext & 0x87f8) {
gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
@@ -1086,7 +1088,7 @@ DISAS_INSN(movem)
TCGv tmp;
int is_load;
- mask = lduw_code(s->pc);
+ mask = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
tmp = gen_lea(s, insn, OS_LONG);
if (IS_NULL_QREG(tmp)) {
@@ -1130,7 +1132,7 @@ DISAS_INSN(bitop_im)
opsize = OS_LONG;
op = (insn >> 6) & 3;
- bitnum = lduw_code(s->pc);
+ bitnum = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
if (bitnum & 0xff00) {
disas_undef(s, insn);
@@ -1383,7 +1385,7 @@ static void gen_set_sr(DisasContext *s, uint16_t insn, int ccr_only)
else if ((insn & 0x3f) == 0x3c)
{
uint16_t val;
- val = lduw_code(s->pc);
+ val = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
gen_set_sr_im(s, val, ccr_only);
}
@@ -1507,7 +1509,7 @@ DISAS_INSN(mull)
/* The upper 32 bits of the product are discarded, so
muls.l and mulu.l are functionally equivalent. */
- ext = lduw_code(s->pc);
+ ext = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
if (ext & 0x87ff) {
gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
@@ -1528,7 +1530,7 @@ DISAS_INSN(link)
TCGv reg;
TCGv tmp;
- offset = ldsw_code(s->pc);
+ offset = cpu_ldsw_code(cpu_single_env, s->pc);
s->pc += 2;
reg = AREG(insn, 0);
tmp = tcg_temp_new();
@@ -1649,7 +1651,7 @@ DISAS_INSN(branch)
op = (insn >> 8) & 0xf;
offset = (int8_t)insn;
if (offset == 0) {
- offset = ldsw_code(s->pc);
+ offset = cpu_ldsw_code(cpu_single_env, s->pc);
s->pc += 2;
} else if (offset == -1) {
offset = read_im32(s);
@@ -1934,13 +1936,13 @@ DISAS_INSN(strldsr)
uint32_t addr;
addr = s->pc - 2;
- ext = lduw_code(s->pc);
+ ext = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
if (ext != 0x46FC) {
gen_exception(s, addr, EXCP_UNSUPPORTED);
return;
}
- ext = lduw_code(s->pc);
+ ext = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
if (IS_USER(s) || (ext & SR_S) == 0) {
gen_exception(s, addr, EXCP_PRIVILEGE);
@@ -2008,7 +2010,7 @@ DISAS_INSN(stop)
return;
}
- ext = lduw_code(s->pc);
+ ext = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
gen_set_sr_im(s, ext, 0);
@@ -2035,7 +2037,7 @@ DISAS_INSN(movec)
return;
}
- ext = lduw_code(s->pc);
+ ext = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
if (ext & 0x8000) {
@@ -2100,7 +2102,7 @@ DISAS_INSN(fpu)
int set_dest;
int opsize;
- ext = lduw_code(s->pc);
+ ext = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
opmode = ext & 0x7f;
switch ((ext >> 13) & 7) {
@@ -2136,7 +2138,7 @@ DISAS_INSN(fpu)
tcg_gen_addi_i32(tmp32, tmp32, -8);
break;
case 5:
- offset = ldsw_code(s->pc);
+ offset = cpu_ldsw_code(cpu_single_env, s->pc);
s->pc += 2;
tcg_gen_addi_i32(tmp32, tmp32, offset);
break;
@@ -2250,12 +2252,12 @@ DISAS_INSN(fpu)
tcg_gen_addi_i32(tmp32, tmp32, -8);
break;
case 5:
- offset = ldsw_code(s->pc);
+ offset = cpu_ldsw_code(cpu_single_env, s->pc);
s->pc += 2;
tcg_gen_addi_i32(tmp32, tmp32, offset);
break;
case 7:
- offset = ldsw_code(s->pc);
+ offset = cpu_ldsw_code(cpu_single_env, s->pc);
offset += s->pc - 2;
s->pc += 2;
tcg_gen_addi_i32(tmp32, tmp32, offset);
@@ -2381,10 +2383,10 @@ DISAS_INSN(fbcc)
int l1;
addr = s->pc;
- offset = ldsw_code(s->pc);
+ offset = cpu_ldsw_code(cpu_single_env, s->pc);
s->pc += 2;
if (insn & (1 << 6)) {
- offset = (offset << 16) | lduw_code(s->pc);
+ offset = (offset << 16) | cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
}
@@ -2506,7 +2508,7 @@ DISAS_INSN(mac)
s->done_mac = 1;
}
- ext = lduw_code(s->pc);
+ ext = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
@@ -2941,7 +2943,7 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
{
uint16_t insn;
- insn = lduw_code(s->pc);
+ insn = cpu_lduw_code(cpu_single_env, s->pc);
s->pc += 2;
opcode_table[insn](s, insn);
@@ -3028,7 +3030,7 @@ gen_intermediate_code_internal(CPUM68KState *env, TranslationBlock *tb,
gen_flush_cc_op(dc);
tcg_gen_movi_i32(QREG_PC, dc->pc);
}
- gen_helper_raise_exception(tcg_const_i32(EXCP_DEBUG));
+ gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
} else {
switch(dc->is_jmp) {
case DISAS_NEXT:
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 15/21] target-unicore32: switch to AREG0 free mode
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (13 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 14/21] target-m68k: " Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
[not found] ` <6a5ae511448ffcecf03ce0a0a03f95af2f7c4eb9.1346606813.git.blauwirbel@gm ail.com>
2012-09-02 17:33 ` [Qemu-devel] [PATCH 16/21] target-arm: " Blue Swirl
` (6 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Guan Xuetao
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
configure | 2 +-
target-unicore32/Makefile.objs | 2 -
target-unicore32/helper.h | 26 ++++++++--------
target-unicore32/op_helper.c | 65 +++++++++++++++------------------------
target-unicore32/translate.c | 38 +++++++++++-----------
5 files changed, 58 insertions(+), 75 deletions(-)
diff --git a/configure b/configure
index 350b47c..4fd3b7f 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
case "$target_arch2" in
- alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
+ alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
;;
esac
diff --git a/target-unicore32/Makefile.objs b/target-unicore32/Makefile.objs
index 777f01f..8e143da 100644
--- a/target-unicore32/Makefile.objs
+++ b/target-unicore32/Makefile.objs
@@ -2,5 +2,3 @@ obj-y += translate.o op_helper.o helper.o cpu.o
obj-y += ucf64_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-unicore32/helper.h b/target-unicore32/helper.h
index 305318a..a4b8149 100644
--- a/target-unicore32/helper.h
+++ b/target-unicore32/helper.h
@@ -17,26 +17,26 @@ DEF_HELPER_1(cp1_putc, void, i32)
DEF_HELPER_1(clz, i32, i32)
DEF_HELPER_1(clo, i32, i32)
-DEF_HELPER_1(exception, void, i32)
+DEF_HELPER_2(exception, void, env, i32)
-DEF_HELPER_2(asr_write, void, i32, i32)
-DEF_HELPER_0(asr_read, i32)
+DEF_HELPER_3(asr_write, void, env, i32, i32)
+DEF_HELPER_1(asr_read, i32, env)
-DEF_HELPER_1(get_user_reg, i32, i32)
-DEF_HELPER_2(set_user_reg, void, i32, i32)
+DEF_HELPER_2(get_user_reg, i32, env, i32)
+DEF_HELPER_3(set_user_reg, void, env, i32, i32)
-DEF_HELPER_2(add_cc, i32, i32, i32)
-DEF_HELPER_2(adc_cc, i32, i32, i32)
-DEF_HELPER_2(sub_cc, i32, i32, i32)
-DEF_HELPER_2(sbc_cc, i32, i32, i32)
+DEF_HELPER_3(add_cc, i32, env, i32, i32)
+DEF_HELPER_3(adc_cc, i32, env, i32, i32)
+DEF_HELPER_3(sub_cc, i32, env, i32, i32)
+DEF_HELPER_3(sbc_cc, i32, env, i32, i32)
DEF_HELPER_2(shl, i32, i32, i32)
DEF_HELPER_2(shr, i32, i32, i32)
DEF_HELPER_2(sar, i32, i32, i32)
-DEF_HELPER_2(shl_cc, i32, i32, i32)
-DEF_HELPER_2(shr_cc, i32, i32, i32)
-DEF_HELPER_2(sar_cc, i32, i32, i32)
-DEF_HELPER_2(ror_cc, i32, i32, i32)
+DEF_HELPER_3(shl_cc, i32, env, i32, i32)
+DEF_HELPER_3(shr_cc, i32, env, i32, i32)
+DEF_HELPER_3(sar_cc, i32, env, i32, i32)
+DEF_HELPER_3(ror_cc, i32, env, i32, i32)
DEF_HELPER_1(ucf64_get_fpscr, i32, env)
DEF_HELPER_2(ucf64_set_fpscr, void, env, i32)
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index c63789d..f474d1b 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -9,19 +9,18 @@
* later version. See the COPYING file in the top-level directory.
*/
#include "cpu.h"
-#include "dyngen-exec.h"
#include "helper.h"
#define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63)
-void HELPER(exception)(uint32_t excp)
+void HELPER(exception)(CPUUniCore32State *env, uint32_t excp)
{
env->exception_index = excp;
cpu_loop_exit(env);
}
-static target_ulong asr_read(void)
+static target_ulong asr_read(CPUUniCore32State *env)
{
int ZF;
ZF = (env->ZF == 0);
@@ -29,24 +28,18 @@ static target_ulong asr_read(void)
(env->CF << 29) | ((env->VF & 0x80000000) >> 3);
}
-target_ulong cpu_asr_read(CPUUniCore32State *env1)
+target_ulong cpu_asr_read(CPUUniCore32State *env)
{
- CPUUniCore32State *saved_env;
- target_ulong ret;
-
- saved_env = env;
- env = env1;
- ret = asr_read();
- env = saved_env;
- return ret;
+ return asr_read(env);
}
-target_ulong HELPER(asr_read)(void)
+target_ulong HELPER(asr_read)(CPUUniCore32State *env)
{
- return asr_read();
+ return asr_read(env);
}
-static void asr_write(target_ulong val, target_ulong mask)
+static void asr_write(CPUUniCore32State *env, target_ulong val,
+ target_ulong mask)
{
if (mask & ASR_NZCV) {
env->ZF = (~val) & ASR_Z;
@@ -62,23 +55,19 @@ static void asr_write(target_ulong val, target_ulong mask)
env->uncached_asr = (env->uncached_asr & ~mask) | (val & mask);
}
-void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask)
+void cpu_asr_write(CPUUniCore32State *env, target_ulong val, target_ulong mask)
{
- CPUUniCore32State *saved_env;
-
- saved_env = env;
- env = env1;
- asr_write(val, mask);
- env = saved_env;
+ asr_write(env, val, mask);
}
-void HELPER(asr_write)(target_ulong val, target_ulong mask)
+void HELPER(asr_write)(CPUUniCore32State *env, target_ulong val,
+ target_ulong mask)
{
- asr_write(val, mask);
+ asr_write(env, val, mask);
}
/* Access to user mode registers from privileged modes. */
-uint32_t HELPER(get_user_reg)(uint32_t regno)
+uint32_t HELPER(get_user_reg)(CPUUniCore32State *env, uint32_t regno)
{
uint32_t val;
@@ -92,7 +81,7 @@ uint32_t HELPER(get_user_reg)(uint32_t regno)
return val;
}
-void HELPER(set_user_reg)(uint32_t regno, uint32_t val)
+void HELPER(set_user_reg)(CPUUniCore32State *env, uint32_t regno, uint32_t val)
{
if (regno == 29) {
env->banked_r29[0] = val;
@@ -107,7 +96,7 @@ void HELPER(set_user_reg)(uint32_t regno, uint32_t val)
The only way to do that in TCG is a conditional branch, which clobbers
all our temporaries. For now implement these as helper functions. */
-uint32_t HELPER(add_cc)(uint32_t a, uint32_t b)
+uint32_t HELPER(add_cc)(CPUUniCore32State *env, uint32_t a, uint32_t b)
{
uint32_t result;
result = a + b;
@@ -117,7 +106,7 @@ uint32_t HELPER(add_cc)(uint32_t a, uint32_t b)
return result;
}
-uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
+uint32_t HELPER(adc_cc)(CPUUniCore32State *env, uint32_t a, uint32_t b)
{
uint32_t result;
if (!env->CF) {
@@ -132,7 +121,7 @@ uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
return result;
}
-uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
+uint32_t HELPER(sub_cc)(CPUUniCore32State *env, uint32_t a, uint32_t b)
{
uint32_t result;
result = a - b;
@@ -142,7 +131,7 @@ uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
return result;
}
-uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
+uint32_t HELPER(sbc_cc)(CPUUniCore32State *env, uint32_t a, uint32_t b)
{
uint32_t result;
if (!env->CF) {
@@ -186,7 +175,7 @@ uint32_t HELPER(sar)(uint32_t x, uint32_t i)
return (int32_t)x >> shift;
}
-uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
+uint32_t HELPER(shl_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
@@ -203,7 +192,7 @@ uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
return x;
}
-uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
+uint32_t HELPER(shr_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
@@ -220,7 +209,7 @@ uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
return x;
}
-uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
+uint32_t HELPER(sar_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
@@ -233,7 +222,7 @@ uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
return x;
}
-uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
+uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
{
int shift1, shift;
shift1 = i & 0xff;
@@ -264,16 +253,13 @@ uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
#define SHIFT 3
#include "softmmu_template.h"
-void tlb_fill(CPUUniCore32State *env1, target_ulong addr, int is_write,
- int mmu_idx, uintptr_t retaddr)
+void tlb_fill(CPUUniCore32State *env, target_ulong addr, int is_write,
+ int mmu_idx, uintptr_t retaddr)
{
TranslationBlock *tb;
- CPUUniCore32State *saved_env;
unsigned long pc;
int ret;
- saved_env = env;
- env = env1;
ret = uc32_cpu_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
@@ -287,6 +273,5 @@ void tlb_fill(CPUUniCore32State *env1, target_ulong addr, int is_write,
}
cpu_loop_exit(env);
}
- env = saved_env;
}
#endif
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 188bf8c..b786a6b 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -253,7 +253,7 @@ static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s,
static inline void gen_set_asr(TCGv var, uint32_t mask)
{
TCGv tmp_mask = tcg_const_i32(mask);
- gen_helper_asr_write(var, tmp_mask);
+ gen_helper_asr_write(cpu_env, var, tmp_mask);
tcg_temp_free_i32(tmp_mask);
}
/* Set NZCV flags from the high 4 bits of var. */
@@ -263,7 +263,7 @@ static void gen_exception(int excp)
{
TCGv tmp = new_tmp();
tcg_gen_movi_i32(tmp, excp);
- gen_helper_exception(tmp);
+ gen_helper_exception(cpu_env, tmp);
dead_tmp(tmp);
}
@@ -416,16 +416,16 @@ static inline void gen_uc32_shift_reg(TCGv var, int shiftop,
if (flags) {
switch (shiftop) {
case 0:
- gen_helper_shl_cc(var, var, shift);
+ gen_helper_shl_cc(var, cpu_env, var, shift);
break;
case 1:
- gen_helper_shr_cc(var, var, shift);
+ gen_helper_shr_cc(var, cpu_env, var, shift);
break;
case 2:
- gen_helper_sar_cc(var, var, shift);
+ gen_helper_sar_cc(var, cpu_env, var, shift);
break;
case 3:
- gen_helper_ror_cc(var, var, shift);
+ gen_helper_ror_cc(var, cpu_env, var, shift);
break;
}
} else {
@@ -1323,11 +1323,11 @@ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
if (IS_USER(s)) {
ILLEGAL;
}
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
gen_exception_return(s, tmp);
} else {
if (UCOP_SET_S) {
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
} else {
tcg_gen_sub_i32(tmp, tmp, tmp2);
}
@@ -1336,7 +1336,7 @@ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
break;
case 0x03:
if (UCOP_SET_S) {
- gen_helper_sub_cc(tmp, tmp2, tmp);
+ gen_helper_sub_cc(tmp, cpu_env, tmp2, tmp);
} else {
tcg_gen_sub_i32(tmp, tmp2, tmp);
}
@@ -1344,7 +1344,7 @@ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
break;
case 0x04:
if (UCOP_SET_S) {
- gen_helper_add_cc(tmp, tmp, tmp2);
+ gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
} else {
tcg_gen_add_i32(tmp, tmp, tmp2);
}
@@ -1352,7 +1352,7 @@ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
break;
case 0x05:
if (UCOP_SET_S) {
- gen_helper_adc_cc(tmp, tmp, tmp2);
+ gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
} else {
gen_add_carry(tmp, tmp, tmp2);
}
@@ -1360,7 +1360,7 @@ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
break;
case 0x06:
if (UCOP_SET_S) {
- gen_helper_sbc_cc(tmp, tmp, tmp2);
+ gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
} else {
gen_sub_carry(tmp, tmp, tmp2);
}
@@ -1368,7 +1368,7 @@ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
break;
case 0x07:
if (UCOP_SET_S) {
- gen_helper_sbc_cc(tmp, tmp2, tmp);
+ gen_helper_sbc_cc(tmp, cpu_env, tmp2, tmp);
} else {
gen_sub_carry(tmp, tmp2, tmp);
}
@@ -1390,13 +1390,13 @@ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
break;
case 0x0a:
if (UCOP_SET_S) {
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
}
dead_tmp(tmp);
break;
case 0x0b:
if (UCOP_SET_S) {
- gen_helper_add_cc(tmp, tmp, tmp2);
+ gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
}
dead_tmp(tmp);
break;
@@ -1536,7 +1536,7 @@ static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
tmp = load_cpu_field(bsr);
} else {
tmp = new_tmp();
- gen_helper_asr_read(tmp);
+ gen_helper_asr_read(tmp, cpu_env);
}
store_reg(s, UCOP_REG_D, tmp);
return;
@@ -1760,7 +1760,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
gen_bx(s, tmp);
} else if (user) {
tmp2 = tcg_const_i32(reg);
- gen_helper_set_user_reg(tmp2, tmp);
+ gen_helper_set_user_reg(cpu_env, tmp2, tmp);
tcg_temp_free_i32(tmp2);
dead_tmp(tmp);
} else if (reg == UCOP_REG_N) {
@@ -1778,7 +1778,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
} else if (user) {
tmp = new_tmp();
tmp2 = tcg_const_i32(reg);
- gen_helper_get_user_reg(tmp, tmp2);
+ gen_helper_get_user_reg(tmp, cpu_env, tmp2);
tcg_temp_free_i32(tmp2);
} else {
tmp = load_reg(s, reg);
@@ -1861,7 +1861,7 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
{
unsigned int insn;
- insn = ldl_code(s->pc);
+ insn = cpu_ldl_code(env, s->pc);
s->pc += 4;
/* UniCore instructions class:
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (14 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 15/21] target-unicore32: " Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-03 0:01 ` Peter Maydell
2012-09-03 13:33 ` Peter Maydell
2012-09-02 17:33 ` [Qemu-devel] [PATCH 17/21] target-microblaze: " Blue Swirl
` (5 subsequent siblings)
21 siblings, 2 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Peter Maydell, Paul Brook
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
configure | 2 +-
target-arm/Makefile.objs | 2 -
target-arm/cpu.h | 10 ++-
target-arm/helper.c | 8 +-
target-arm/helper.h | 60 +++++++++---------
target-arm/op_helper.c | 92 +++++++++++++---------------
target-arm/translate.c | 148 +++++++++++++++++++++++-----------------------
7 files changed, 158 insertions(+), 164 deletions(-)
diff --git a/configure b/configure
index 4fd3b7f..efb5014 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
case "$target_arch2" in
- alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
+ alpha | arm* | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
;;
esac
diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
index f447c4f..b6f1a9e 100644
--- a/target-arm/Makefile.objs
+++ b/target-arm/Makefile.objs
@@ -2,5 +2,3 @@ obj-y += arm-semi.o
obj-$(CONFIG_SOFTMMU) += machine.o
obj-y += translate.o op_helper.o helper.o cpu.o
obj-y += neon_helper.o iwmmxt_helper.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index d7f93d9..7fac94f 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -734,9 +734,10 @@ static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
}
/* Load an instruction and return it in the standard little-endian order */
-static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
+static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
+ bool do_swap)
{
- uint32_t insn = ldl_code(addr);
+ uint32_t insn = cpu_ldl_code(env, addr);
if (do_swap) {
return bswap32(insn);
}
@@ -744,9 +745,10 @@ static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
}
/* Ditto, for a halfword (Thumb) instruction */
-static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap)
+static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr,
+ bool do_swap)
{
- uint16_t insn = lduw_code(addr);
+ uint16_t insn = cpu_lduw_code(env, addr);
if (do_swap) {
return bswap16(insn);
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index dceaa95..f4d711c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1756,7 +1756,7 @@ static void do_interrupt_v7m(CPUARMState *env)
case EXCP_BKPT:
if (semihosting_enabled) {
int nr;
- nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
+ nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
if (nr == 0xab) {
env->regs[15] += 2;
env->regs[0] = do_arm_semihosting(env);
@@ -1828,9 +1828,9 @@ void do_interrupt(CPUARMState *env)
if (semihosting_enabled) {
/* Check for semihosting interrupt. */
if (env->thumb) {
- mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
+ mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code) & 0xff;
} else {
- mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
+ mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
& 0xffffff;
}
/* Only intercept calls from privileged modes, to provide some
@@ -1851,7 +1851,7 @@ void do_interrupt(CPUARMState *env)
case EXCP_BKPT:
/* See if this is a semihosting syscall. */
if (env->thumb && semihosting_enabled) {
- mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
+ mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
if (mask == 0xab
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
env->regs[15] += 2;
diff --git a/target-arm/helper.h b/target-arm/helper.h
index 21e9cfe..afdb2b5 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -4,12 +4,12 @@ DEF_HELPER_1(clz, i32, i32)
DEF_HELPER_1(sxtb16, i32, i32)
DEF_HELPER_1(uxtb16, i32, i32)
-DEF_HELPER_2(add_setq, i32, i32, i32)
-DEF_HELPER_2(add_saturate, i32, i32, i32)
-DEF_HELPER_2(sub_saturate, i32, i32, i32)
-DEF_HELPER_2(add_usaturate, i32, i32, i32)
-DEF_HELPER_2(sub_usaturate, i32, i32, i32)
-DEF_HELPER_1(double_saturate, i32, s32)
+DEF_HELPER_3(add_setq, i32, env, i32, i32)
+DEF_HELPER_3(add_saturate, i32, env, i32, i32)
+DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
+DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
+DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
+DEF_HELPER_2(double_saturate, i32, env, s32)
DEF_HELPER_2(sdiv, s32, s32, s32)
DEF_HELPER_2(udiv, i32, i32, i32)
DEF_HELPER_1(rbit, i32, i32)
@@ -40,21 +40,21 @@ PAS_OP(uq)
PAS_OP(uh)
#undef PAS_OP
-DEF_HELPER_2(ssat, i32, i32, i32)
-DEF_HELPER_2(usat, i32, i32, i32)
-DEF_HELPER_2(ssat16, i32, i32, i32)
-DEF_HELPER_2(usat16, i32, i32, i32)
+DEF_HELPER_3(ssat, i32, env, i32, i32)
+DEF_HELPER_3(usat, i32, env, i32, i32)
+DEF_HELPER_3(ssat16, i32, env, i32, i32)
+DEF_HELPER_3(usat16, i32, env, i32, i32)
DEF_HELPER_2(usad8, i32, i32, i32)
DEF_HELPER_1(logicq_cc, i32, i64)
DEF_HELPER_3(sel_flags, i32, i32, i32, i32)
-DEF_HELPER_1(exception, void, i32)
-DEF_HELPER_0(wfi, void)
+DEF_HELPER_2(exception, void, env, i32)
+DEF_HELPER_1(wfi, void, env)
-DEF_HELPER_2(cpsr_write, void, i32, i32)
-DEF_HELPER_0(cpsr_read, i32)
+DEF_HELPER_3(cpsr_write, void, env, i32, i32)
+DEF_HELPER_1(cpsr_read, i32, env)
DEF_HELPER_3(v7m_msr, void, env, i32, i32)
DEF_HELPER_2(v7m_mrs, i32, env, i32)
@@ -67,8 +67,8 @@ DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
DEF_HELPER_2(get_r13_banked, i32, env, i32)
DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
-DEF_HELPER_1(get_user_reg, i32, i32)
-DEF_HELPER_2(set_user_reg, void, i32, i32)
+DEF_HELPER_2(get_user_reg, i32, env, i32)
+DEF_HELPER_3(set_user_reg, void, env, i32, i32)
DEF_HELPER_1(vfp_get_fpscr, i32, env)
DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
@@ -140,20 +140,20 @@ DEF_HELPER_2(recpe_f32, f32, f32, env)
DEF_HELPER_2(rsqrte_f32, f32, f32, env)
DEF_HELPER_2(recpe_u32, i32, i32, env)
DEF_HELPER_2(rsqrte_u32, i32, i32, env)
-DEF_HELPER_4(neon_tbl, i32, i32, i32, i32, i32)
-
-DEF_HELPER_2(add_cc, i32, i32, i32)
-DEF_HELPER_2(adc_cc, i32, i32, i32)
-DEF_HELPER_2(sub_cc, i32, i32, i32)
-DEF_HELPER_2(sbc_cc, i32, i32, i32)
-
-DEF_HELPER_2(shl, i32, i32, i32)
-DEF_HELPER_2(shr, i32, i32, i32)
-DEF_HELPER_2(sar, i32, i32, i32)
-DEF_HELPER_2(shl_cc, i32, i32, i32)
-DEF_HELPER_2(shr_cc, i32, i32, i32)
-DEF_HELPER_2(sar_cc, i32, i32, i32)
-DEF_HELPER_2(ror_cc, i32, i32, i32)
+DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32)
+
+DEF_HELPER_3(add_cc, i32, env, i32, i32)
+DEF_HELPER_3(adc_cc, i32, env, i32, i32)
+DEF_HELPER_3(sub_cc, i32, env, i32, i32)
+DEF_HELPER_3(sbc_cc, i32, env, i32, i32)
+
+DEF_HELPER_3(shl, i32, env, i32, i32)
+DEF_HELPER_3(shr, i32, env, i32, i32)
+DEF_HELPER_3(sar, i32, env, i32, i32)
+DEF_HELPER_3(shl_cc, i32, env, i32, i32)
+DEF_HELPER_3(shr_cc, i32, env, i32, i32)
+DEF_HELPER_3(sar_cc, i32, env, i32, i32)
+DEF_HELPER_3(ror_cc, i32, env, i32, i32)
/* neon_helper.c */
DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index d77bfab..f13fc3a 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -17,19 +17,18 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "cpu.h"
-#include "dyngen-exec.h"
#include "helper.h"
#define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63)
-static void raise_exception(int tt)
+static void raise_exception(CPUARMState *env, int tt)
{
env->exception_index = tt;
cpu_loop_exit(env);
}
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
+uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
uint32_t rn, uint32_t maxindex)
{
uint32_t val;
@@ -72,16 +71,12 @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
/* try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
TranslationBlock *tb;
- CPUARMState *saved_env;
int ret;
- saved_env = env;
- env = env1;
ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
@@ -93,15 +88,14 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
cpu_restore_state(tb, env, retaddr);
}
}
- raise_exception(env->exception_index);
+ raise_exception(env, env->exception_index);
}
- env = saved_env;
}
#endif
/* FIXME: Pass an explicit pointer to QF to CPUARMState, and move saturating
instructions into helper.c */
-uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
+uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t res = a + b;
if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
@@ -109,7 +103,7 @@ uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
return res;
}
-uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
+uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t res = a + b;
if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
@@ -119,7 +113,7 @@ uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
return res;
}
-uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
+uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t res = a - b;
if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
@@ -129,7 +123,7 @@ uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
return res;
}
-uint32_t HELPER(double_saturate)(int32_t val)
+uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
{
uint32_t res;
if (val >= 0x40000000) {
@@ -144,7 +138,7 @@ uint32_t HELPER(double_saturate)(int32_t val)
return res;
}
-uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b)
+uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t res = a + b;
if (res < a) {
@@ -154,7 +148,7 @@ uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b)
return res;
}
-uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b)
+uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t res = a - b;
if (res > a) {
@@ -165,7 +159,7 @@ uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b)
}
/* Signed saturation. */
-static inline uint32_t do_ssat(int32_t val, int shift)
+static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
{
int32_t top;
uint32_t mask;
@@ -183,7 +177,7 @@ static inline uint32_t do_ssat(int32_t val, int shift)
}
/* Unsigned saturation. */
-static inline uint32_t do_usat(int32_t val, int shift)
+static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
{
uint32_t max;
@@ -199,62 +193,62 @@ static inline uint32_t do_usat(int32_t val, int shift)
}
/* Signed saturate. */
-uint32_t HELPER(ssat)(uint32_t x, uint32_t shift)
+uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
{
- return do_ssat(x, shift);
+ return do_ssat(env, x, shift);
}
/* Dual halfword signed saturate. */
-uint32_t HELPER(ssat16)(uint32_t x, uint32_t shift)
+uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
{
uint32_t res;
- res = (uint16_t)do_ssat((int16_t)x, shift);
- res |= do_ssat(((int32_t)x) >> 16, shift) << 16;
+ res = (uint16_t)do_ssat(env, (int16_t)x, shift);
+ res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
return res;
}
/* Unsigned saturate. */
-uint32_t HELPER(usat)(uint32_t x, uint32_t shift)
+uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
{
- return do_usat(x, shift);
+ return do_usat(env, x, shift);
}
/* Dual halfword unsigned saturate. */
-uint32_t HELPER(usat16)(uint32_t x, uint32_t shift)
+uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
{
uint32_t res;
- res = (uint16_t)do_usat((int16_t)x, shift);
- res |= do_usat(((int32_t)x) >> 16, shift) << 16;
+ res = (uint16_t)do_usat(env, (int16_t)x, shift);
+ res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
return res;
}
-void HELPER(wfi)(void)
+void HELPER(wfi)(CPUARMState *env)
{
env->exception_index = EXCP_HLT;
env->halted = 1;
cpu_loop_exit(env);
}
-void HELPER(exception)(uint32_t excp)
+void HELPER(exception)(CPUARMState *env, uint32_t excp)
{
env->exception_index = excp;
cpu_loop_exit(env);
}
-uint32_t HELPER(cpsr_read)(void)
+uint32_t HELPER(cpsr_read)(CPUARMState *env)
{
return cpsr_read(env) & ~CPSR_EXEC;
}
-void HELPER(cpsr_write)(uint32_t val, uint32_t mask)
+void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
{
cpsr_write(env, val, mask);
}
/* Access to user mode registers from privileged modes. */
-uint32_t HELPER(get_user_reg)(uint32_t regno)
+uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
{
uint32_t val;
@@ -271,7 +265,7 @@ uint32_t HELPER(get_user_reg)(uint32_t regno)
return val;
}
-void HELPER(set_user_reg)(uint32_t regno, uint32_t val)
+void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
{
if (regno == 13) {
env->banked_r13[0] = val;
@@ -290,7 +284,7 @@ void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
const ARMCPRegInfo *ri = rip;
int excp = ri->writefn(env, ri, value);
if (excp) {
- raise_exception(excp);
+ raise_exception(env, excp);
}
}
@@ -300,7 +294,7 @@ uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
uint64_t value;
int excp = ri->readfn(env, ri, &value);
if (excp) {
- raise_exception(excp);
+ raise_exception(env, excp);
}
return value;
}
@@ -310,7 +304,7 @@ void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
const ARMCPRegInfo *ri = rip;
int excp = ri->writefn(env, ri, value);
if (excp) {
- raise_exception(excp);
+ raise_exception(env, excp);
}
}
@@ -320,7 +314,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
uint64_t value;
int excp = ri->readfn(env, ri, &value);
if (excp) {
- raise_exception(excp);
+ raise_exception(env, excp);
}
return value;
}
@@ -329,7 +323,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
The only way to do that in TCG is a conditional branch, which clobbers
all our temporaries. For now implement these as helper functions. */
-uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
+uint32_t HELPER (add_cc)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t result;
result = a + b;
@@ -339,7 +333,7 @@ uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
return result;
}
-uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
+uint32_t HELPER(adc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t result;
if (!env->CF) {
@@ -354,7 +348,7 @@ uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
return result;
}
-uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
+uint32_t HELPER(sub_cc)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t result;
result = a - b;
@@ -364,7 +358,7 @@ uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
return result;
}
-uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
+uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t result;
if (!env->CF) {
@@ -381,7 +375,7 @@ uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
/* Similarly for variable shift instructions. */
-uint32_t HELPER(shl)(uint32_t x, uint32_t i)
+uint32_t HELPER(shl)(CPUARMState *env, uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32)
@@ -389,7 +383,7 @@ uint32_t HELPER(shl)(uint32_t x, uint32_t i)
return x << shift;
}
-uint32_t HELPER(shr)(uint32_t x, uint32_t i)
+uint32_t HELPER(shr)(CPUARMState *env, uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32)
@@ -397,7 +391,7 @@ uint32_t HELPER(shr)(uint32_t x, uint32_t i)
return (uint32_t)x >> shift;
}
-uint32_t HELPER(sar)(uint32_t x, uint32_t i)
+uint32_t HELPER(sar)(CPUARMState *env, uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32)
@@ -405,7 +399,7 @@ uint32_t HELPER(sar)(uint32_t x, uint32_t i)
return (int32_t)x >> shift;
}
-uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
+uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
@@ -421,7 +415,7 @@ uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
return x;
}
-uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
+uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
@@ -437,7 +431,7 @@ uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
return x;
}
-uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
+uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
@@ -450,7 +444,7 @@ uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
return x;
}
-uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
+uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
{
int shift1, shift;
shift1 = i & 0xff;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index edef79a..f4b447a 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -199,7 +199,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
static inline void gen_set_cpsr(TCGv var, uint32_t mask)
{
TCGv tmp_mask = tcg_const_i32(mask);
- gen_helper_cpsr_write(var, tmp_mask);
+ gen_helper_cpsr_write(cpu_env, var, tmp_mask);
tcg_temp_free_i32(tmp_mask);
}
/* Set NZCV flags from the high 4 bits of var. */
@@ -209,7 +209,7 @@ static void gen_exception(int excp)
{
TCGv tmp = tcg_temp_new_i32();
tcg_gen_movi_i32(tmp, excp);
- gen_helper_exception(tmp);
+ gen_helper_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
}
@@ -490,16 +490,16 @@ static inline void gen_arm_shift_reg(TCGv var, int shiftop,
{
if (flags) {
switch (shiftop) {
- case 0: gen_helper_shl_cc(var, var, shift); break;
- case 1: gen_helper_shr_cc(var, var, shift); break;
- case 2: gen_helper_sar_cc(var, var, shift); break;
- case 3: gen_helper_ror_cc(var, var, shift); break;
+ case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break;
+ case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break;
+ case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break;
+ case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break;
}
} else {
switch (shiftop) {
- case 0: gen_helper_shl(var, var, shift); break;
- case 1: gen_helper_shr(var, var, shift); break;
- case 2: gen_helper_sar(var, var, shift); break;
+ case 0: gen_helper_shl(var, cpu_env, var, shift); break;
+ case 1: gen_helper_shr(var, cpu_env, var, shift); break;
+ case 2: gen_helper_sar(var, cpu_env, var, shift); break;
case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
tcg_gen_rotr_i32(var, var, shift); break;
}
@@ -6121,7 +6121,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
tmp2 = neon_load_reg(rm, 0);
tmp4 = tcg_const_i32(rn);
tmp5 = tcg_const_i32(n);
- gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
+ gen_helper_neon_tbl(tmp2, cpu_env, tmp2, tmp, tmp4, tmp5);
tcg_temp_free_i32(tmp);
if (insn & (1 << 6)) {
tmp = neon_load_reg(rd, 1);
@@ -6130,7 +6130,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
tcg_gen_movi_i32(tmp, 0);
}
tmp3 = neon_load_reg(rm, 1);
- gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
+ gen_helper_neon_tbl(tmp3, cpu_env, tmp3, tmp, tmp4, tmp5);
tcg_temp_free_i32(tmp5);
tcg_temp_free_i32(tmp4);
neon_store_reg(rd, 0, tmp2);
@@ -6534,7 +6534,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
TCGv addr;
TCGv_i64 tmp64;
- insn = arm_ldl_code(s->pc, s->bswap_code);
+ insn = arm_ldl_code(env, s->pc, s->bswap_code);
s->pc += 4;
/* M variants do not implement ARM mode. */
@@ -6818,7 +6818,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
tmp = load_cpu_field(spsr);
} else {
tmp = tcg_temp_new_i32();
- gen_helper_cpsr_read(tmp);
+ gen_helper_cpsr_read(tmp, cpu_env);
}
store_reg(s, rd, tmp);
}
@@ -6869,11 +6869,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
tmp = load_reg(s, rm);
tmp2 = load_reg(s, rn);
if (op1 & 2)
- gen_helper_double_saturate(tmp2, tmp2);
+ gen_helper_double_saturate(tmp2, cpu_env, tmp2);
if (op1 & 1)
- gen_helper_sub_saturate(tmp, tmp, tmp2);
+ gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
else
- gen_helper_add_saturate(tmp, tmp, tmp2);
+ gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
store_reg(s, rd, tmp);
break;
@@ -6911,7 +6911,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
tcg_temp_free_i64(tmp64);
if ((sh & 2) == 0) {
tmp2 = load_reg(s, rn);
- gen_helper_add_setq(tmp, tmp, tmp2);
+ gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
}
store_reg(s, rd, tmp);
@@ -6931,7 +6931,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
} else {
if (op1 == 0) {
tmp2 = load_reg(s, rn);
- gen_helper_add_setq(tmp, tmp, tmp2);
+ gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
}
store_reg(s, rd, tmp);
@@ -7005,11 +7005,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
if (IS_USER(s)) {
goto illegal_op;
}
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
gen_exception_return(s, tmp);
} else {
if (set_cc) {
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
} else {
tcg_gen_sub_i32(tmp, tmp, tmp2);
}
@@ -7018,7 +7018,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
break;
case 0x03:
if (set_cc) {
- gen_helper_sub_cc(tmp, tmp2, tmp);
+ gen_helper_sub_cc(tmp, cpu_env, tmp2, tmp);
} else {
tcg_gen_sub_i32(tmp, tmp2, tmp);
}
@@ -7026,7 +7026,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
break;
case 0x04:
if (set_cc) {
- gen_helper_add_cc(tmp, tmp, tmp2);
+ gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
} else {
tcg_gen_add_i32(tmp, tmp, tmp2);
}
@@ -7034,7 +7034,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
break;
case 0x05:
if (set_cc) {
- gen_helper_adc_cc(tmp, tmp, tmp2);
+ gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
} else {
gen_add_carry(tmp, tmp, tmp2);
}
@@ -7042,7 +7042,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
break;
case 0x06:
if (set_cc) {
- gen_helper_sbc_cc(tmp, tmp, tmp2);
+ gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
} else {
gen_sub_carry(tmp, tmp, tmp2);
}
@@ -7050,7 +7050,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
break;
case 0x07:
if (set_cc) {
- gen_helper_sbc_cc(tmp, tmp2, tmp);
+ gen_helper_sbc_cc(tmp, cpu_env, tmp2, tmp);
} else {
gen_sub_carry(tmp, tmp2, tmp);
}
@@ -7072,13 +7072,13 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
break;
case 0x0a:
if (set_cc) {
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
}
tcg_temp_free_i32(tmp);
break;
case 0x0b:
if (set_cc) {
- gen_helper_add_cc(tmp, tmp, tmp2);
+ gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
}
tcg_temp_free_i32(tmp);
break;
@@ -7395,9 +7395,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
sh = (insn >> 16) & 0x1f;
tmp2 = tcg_const_i32(sh);
if (insn & (1 << 22))
- gen_helper_usat(tmp, tmp, tmp2);
+ gen_helper_usat(tmp, cpu_env, tmp, tmp2);
else
- gen_helper_ssat(tmp, tmp, tmp2);
+ gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
store_reg(s, rd, tmp);
} else if ((insn & 0x00300fe0) == 0x00200f20) {
@@ -7406,9 +7406,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
sh = (insn >> 16) & 0x1f;
tmp2 = tcg_const_i32(sh);
if (insn & (1 << 22))
- gen_helper_usat16(tmp, tmp, tmp2);
+ gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
else
- gen_helper_ssat16(tmp, tmp, tmp2);
+ gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
store_reg(s, rd, tmp);
} else if ((insn & 0x00700fe0) == 0x00000fa0) {
@@ -7518,7 +7518,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
* however it may overflow considered as a signed
* operation, in which case we must set the Q flag.
*/
- gen_helper_add_setq(tmp, tmp, tmp2);
+ gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
}
tcg_temp_free_i32(tmp2);
if (insn & (1 << 22)) {
@@ -7534,7 +7534,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
if (rd != 15)
{
tmp2 = load_reg(s, rd);
- gen_helper_add_setq(tmp, tmp, tmp2);
+ gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
}
store_reg(s, rn, tmp);
@@ -7719,7 +7719,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
tmp = gen_ld32(addr, IS_USER(s));
if (user) {
tmp2 = tcg_const_i32(i);
- gen_helper_set_user_reg(tmp2, tmp);
+ gen_helper_set_user_reg(cpu_env, tmp2, tmp);
tcg_temp_free_i32(tmp2);
tcg_temp_free_i32(tmp);
} else if (i == rn) {
@@ -7738,7 +7738,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
} else if (user) {
tmp = tcg_temp_new_i32();
tmp2 = tcg_const_i32(i);
- gen_helper_get_user_reg(tmp, tmp2);
+ gen_helper_get_user_reg(tmp, cpu_env, tmp2);
tcg_temp_free_i32(tmp2);
} else {
tmp = load_reg(s, i);
@@ -7865,31 +7865,31 @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCG
break;
case 8: /* add */
if (conds)
- gen_helper_add_cc(t0, t0, t1);
+ gen_helper_add_cc(t0, cpu_env, t0, t1);
else
tcg_gen_add_i32(t0, t0, t1);
break;
case 10: /* adc */
if (conds)
- gen_helper_adc_cc(t0, t0, t1);
+ gen_helper_adc_cc(t0, cpu_env, t0, t1);
else
gen_adc(t0, t1);
break;
case 11: /* sbc */
if (conds)
- gen_helper_sbc_cc(t0, t0, t1);
+ gen_helper_sbc_cc(t0, cpu_env, t0, t1);
else
gen_sub_carry(t0, t0, t1);
break;
case 13: /* sub */
if (conds)
- gen_helper_sub_cc(t0, t0, t1);
+ gen_helper_sub_cc(t0, cpu_env, t0, t1);
else
tcg_gen_sub_i32(t0, t0, t1);
break;
case 14: /* rsb */
if (conds)
- gen_helper_sub_cc(t0, t1, t0);
+ gen_helper_sub_cc(t0, cpu_env, t1, t0);
else
tcg_gen_sub_i32(t0, t1, t0);
break;
@@ -7962,7 +7962,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
/* Fall through to 32-bit decode. */
}
- insn = arm_lduw_code(s->pc, s->bswap_code);
+ insn = arm_lduw_code(env, s->pc, s->bswap_code);
s->pc += 2;
insn |= (uint32_t)insn_hw1 << 16;
@@ -8111,7 +8111,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
gen_st32(tmp, addr, 0);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_helper_cpsr_read(tmp);
+ gen_helper_cpsr_read(tmp, cpu_env);
gen_st32(tmp, addr, 0);
if (insn & (1 << 21)) {
if ((insn & (1 << 24)) == 0) {
@@ -8293,11 +8293,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
tmp = load_reg(s, rn);
tmp2 = load_reg(s, rm);
if (op & 1)
- gen_helper_double_saturate(tmp, tmp);
+ gen_helper_double_saturate(tmp, cpu_env, tmp);
if (op & 2)
- gen_helper_sub_saturate(tmp, tmp2, tmp);
+ gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
else
- gen_helper_add_saturate(tmp, tmp, tmp2);
+ gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
} else {
tmp = load_reg(s, rn);
@@ -8353,7 +8353,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
tcg_temp_free_i32(tmp2);
if (rs != 15) {
tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, tmp, tmp2);
+ gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
}
break;
@@ -8370,13 +8370,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
* however it may overflow considered as a signed
* operation, in which case we must set the Q flag.
*/
- gen_helper_add_setq(tmp, tmp, tmp2);
+ gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
}
tcg_temp_free_i32(tmp2);
if (rs != 15)
{
tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, tmp, tmp2);
+ gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
}
break;
@@ -8393,7 +8393,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
if (rs != 15)
{
tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, tmp, tmp2);
+ gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
}
break;
@@ -8632,7 +8632,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
gen_helper_v7m_mrs(tmp, cpu_env, addr);
tcg_temp_free_i32(addr);
} else {
- gen_helper_cpsr_read(tmp);
+ gen_helper_cpsr_read(tmp, cpu_env);
}
store_reg(s, rd, tmp);
break;
@@ -8721,15 +8721,15 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
if (op & 4) {
/* Unsigned. */
if ((op & 1) && shift == 0)
- gen_helper_usat16(tmp, tmp, tmp2);
+ gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
else
- gen_helper_usat(tmp, tmp, tmp2);
+ gen_helper_usat(tmp, cpu_env, tmp, tmp2);
} else {
/* Signed. */
if ((op & 1) && shift == 0)
- gen_helper_ssat16(tmp, tmp, tmp2);
+ gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
else
- gen_helper_ssat(tmp, tmp, tmp2);
+ gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
}
tcg_temp_free_i32(tmp2);
break;
@@ -8992,7 +8992,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
}
}
- insn = arm_lduw_code(s->pc, s->bswap_code);
+ insn = arm_lduw_code(env, s->pc, s->bswap_code);
s->pc += 2;
switch (insn >> 12) {
@@ -9017,12 +9017,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (s->condexec_mask)
tcg_gen_sub_i32(tmp, tmp, tmp2);
else
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
} else {
if (s->condexec_mask)
tcg_gen_add_i32(tmp, tmp, tmp2);
else
- gen_helper_add_cc(tmp, tmp, tmp2);
+ gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
}
tcg_temp_free_i32(tmp2);
store_reg(s, rd, tmp);
@@ -9053,7 +9053,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
tcg_gen_movi_i32(tmp2, insn & 0xff);
switch (op) {
case 1: /* cmp */
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(tmp2);
break;
@@ -9061,7 +9061,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (s->condexec_mask)
tcg_gen_add_i32(tmp, tmp, tmp2);
else
- gen_helper_add_cc(tmp, tmp, tmp2);
+ gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
store_reg(s, rd, tmp);
break;
@@ -9069,7 +9069,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (s->condexec_mask)
tcg_gen_sub_i32(tmp, tmp, tmp2);
else
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
store_reg(s, rd, tmp);
break;
@@ -9105,7 +9105,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
case 1: /* cmp */
tmp = load_reg(s, rd);
tmp2 = load_reg(s, rm);
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
tcg_temp_free_i32(tmp2);
tcg_temp_free_i32(tmp);
break;
@@ -9166,25 +9166,25 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
break;
case 0x2: /* lsl */
if (s->condexec_mask) {
- gen_helper_shl(tmp2, tmp2, tmp);
+ gen_helper_shl(tmp2, cpu_env, tmp2, tmp);
} else {
- gen_helper_shl_cc(tmp2, tmp2, tmp);
+ gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp);
gen_logic_CC(tmp2);
}
break;
case 0x3: /* lsr */
if (s->condexec_mask) {
- gen_helper_shr(tmp2, tmp2, tmp);
+ gen_helper_shr(tmp2, cpu_env, tmp2, tmp);
} else {
- gen_helper_shr_cc(tmp2, tmp2, tmp);
+ gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp);
gen_logic_CC(tmp2);
}
break;
case 0x4: /* asr */
if (s->condexec_mask) {
- gen_helper_sar(tmp2, tmp2, tmp);
+ gen_helper_sar(tmp2, cpu_env, tmp2, tmp);
} else {
- gen_helper_sar_cc(tmp2, tmp2, tmp);
+ gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp);
gen_logic_CC(tmp2);
}
break;
@@ -9192,20 +9192,20 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (s->condexec_mask)
gen_adc(tmp, tmp2);
else
- gen_helper_adc_cc(tmp, tmp, tmp2);
+ gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
break;
case 0x6: /* sbc */
if (s->condexec_mask)
gen_sub_carry(tmp, tmp, tmp2);
else
- gen_helper_sbc_cc(tmp, tmp, tmp2);
+ gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
break;
case 0x7: /* ror */
if (s->condexec_mask) {
tcg_gen_andi_i32(tmp, tmp, 0x1f);
tcg_gen_rotr_i32(tmp2, tmp2, tmp);
} else {
- gen_helper_ror_cc(tmp2, tmp2, tmp);
+ gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp);
gen_logic_CC(tmp2);
}
break;
@@ -9218,14 +9218,14 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (s->condexec_mask)
tcg_gen_neg_i32(tmp, tmp2);
else
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
break;
case 0xa: /* cmp */
- gen_helper_sub_cc(tmp, tmp, tmp2);
+ gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
rd = 16;
break;
case 0xb: /* cmn */
- gen_helper_add_cc(tmp, tmp, tmp2);
+ gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
rd = 16;
break;
case 0xc: /* orr */
@@ -9913,7 +9913,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
/* nothing more to generate */
break;
case DISAS_WFI:
- gen_helper_wfi();
+ gen_helper_wfi(cpu_env);
break;
case DISAS_SWI:
gen_exception(EXCP_SWI);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode
2012-09-02 17:33 ` [Qemu-devel] [PATCH 16/21] target-arm: " Blue Swirl
@ 2012-09-03 0:01 ` Peter Maydell
2012-09-03 0:03 ` Peter Maydell
2012-09-03 13:33 ` Peter Maydell
1 sibling, 1 reply; 64+ messages in thread
From: Peter Maydell @ 2012-09-03 0:01 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel, Paul Brook
On 2 September 2012 18:33, Blue Swirl <blauwirbel@gmail.com> wrote:
> Add an explicit CPUState parameter instead of relying on AREG0
> and switch to AREG0 free mode.
>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> ---
> configure | 2 +-
> target-arm/Makefile.objs | 2 -
> target-arm/cpu.h | 10 ++-
> target-arm/helper.c | 8 +-
> target-arm/helper.h | 60 +++++++++---------
> target-arm/op_helper.c | 92 +++++++++++++---------------
> target-arm/translate.c | 148 +++++++++++++++++++++++-----------------------
> 7 files changed, 158 insertions(+), 164 deletions(-)
This is too big to easily review -- it's making a change to a lot
of helpers, and in each case that change affects three places
(callers, declaration, implementation). That'
> diff --git a/configure b/configure
> index 4fd3b7f..efb5014 100755
> --- a/configure
> +++ b/configure
> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
>
>
> case "$target_arch2" in
> - alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> + alpha | arm* | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
> ;;
> esac
> diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
> index f447c4f..b6f1a9e 100644
> --- a/target-arm/Makefile.objs
> +++ b/target-arm/Makefile.objs
> @@ -2,5 +2,3 @@ obj-y += arm-semi.o
> obj-$(CONFIG_SOFTMMU) += machine.o
> obj-y += translate.o op_helper.o helper.o cpu.o
> obj-y += neon_helper.o iwmmxt_helper.o
> -
> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index d7f93d9..7fac94f 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -734,9 +734,10 @@ static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
> }
>
> /* Load an instruction and return it in the standard little-endian order */
> -static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
> +static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
> + bool do_swap)
> {
> - uint32_t insn = ldl_code(addr);
> + uint32_t insn = cpu_ldl_code(env, addr);
> if (do_swap) {
> return bswap32(insn);
> }
> @@ -744,9 +745,10 @@ static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
> }
>
> /* Ditto, for a halfword (Thumb) instruction */
> -static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap)
> +static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr,
> + bool do_swap)
> {
> - uint16_t insn = lduw_code(addr);
> + uint16_t insn = cpu_lduw_code(env, addr);
> if (do_swap) {
> return bswap16(insn);
> }
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index dceaa95..f4d711c 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1756,7 +1756,7 @@ static void do_interrupt_v7m(CPUARMState *env)
> case EXCP_BKPT:
> if (semihosting_enabled) {
> int nr;
> - nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
> + nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
> if (nr == 0xab) {
> env->regs[15] += 2;
> env->regs[0] = do_arm_semihosting(env);
> @@ -1828,9 +1828,9 @@ void do_interrupt(CPUARMState *env)
> if (semihosting_enabled) {
> /* Check for semihosting interrupt. */
> if (env->thumb) {
> - mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
> + mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code) & 0xff;
> } else {
> - mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
> + mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
> & 0xffffff;
> }
> /* Only intercept calls from privileged modes, to provide some
> @@ -1851,7 +1851,7 @@ void do_interrupt(CPUARMState *env)
> case EXCP_BKPT:
> /* See if this is a semihosting syscall. */
> if (env->thumb && semihosting_enabled) {
> - mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
> + mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
> if (mask == 0xab
> && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
> env->regs[15] += 2;
> diff --git a/target-arm/helper.h b/target-arm/helper.h
> index 21e9cfe..afdb2b5 100644
> --- a/target-arm/helper.h
> +++ b/target-arm/helper.h
> @@ -4,12 +4,12 @@ DEF_HELPER_1(clz, i32, i32)
> DEF_HELPER_1(sxtb16, i32, i32)
> DEF_HELPER_1(uxtb16, i32, i32)
>
> -DEF_HELPER_2(add_setq, i32, i32, i32)
> -DEF_HELPER_2(add_saturate, i32, i32, i32)
> -DEF_HELPER_2(sub_saturate, i32, i32, i32)
> -DEF_HELPER_2(add_usaturate, i32, i32, i32)
> -DEF_HELPER_2(sub_usaturate, i32, i32, i32)
> -DEF_HELPER_1(double_saturate, i32, s32)
> +DEF_HELPER_3(add_setq, i32, env, i32, i32)
> +DEF_HELPER_3(add_saturate, i32, env, i32, i32)
> +DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
> +DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
> +DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
> +DEF_HELPER_2(double_saturate, i32, env, s32)
> DEF_HELPER_2(sdiv, s32, s32, s32)
> DEF_HELPER_2(udiv, i32, i32, i32)
> DEF_HELPER_1(rbit, i32, i32)
> @@ -40,21 +40,21 @@ PAS_OP(uq)
> PAS_OP(uh)
> #undef PAS_OP
>
> -DEF_HELPER_2(ssat, i32, i32, i32)
> -DEF_HELPER_2(usat, i32, i32, i32)
> -DEF_HELPER_2(ssat16, i32, i32, i32)
> -DEF_HELPER_2(usat16, i32, i32, i32)
> +DEF_HELPER_3(ssat, i32, env, i32, i32)
> +DEF_HELPER_3(usat, i32, env, i32, i32)
> +DEF_HELPER_3(ssat16, i32, env, i32, i32)
> +DEF_HELPER_3(usat16, i32, env, i32, i32)
>
> DEF_HELPER_2(usad8, i32, i32, i32)
>
> DEF_HELPER_1(logicq_cc, i32, i64)
>
> DEF_HELPER_3(sel_flags, i32, i32, i32, i32)
> -DEF_HELPER_1(exception, void, i32)
> -DEF_HELPER_0(wfi, void)
> +DEF_HELPER_2(exception, void, env, i32)
> +DEF_HELPER_1(wfi, void, env)
>
> -DEF_HELPER_2(cpsr_write, void, i32, i32)
> -DEF_HELPER_0(cpsr_read, i32)
> +DEF_HELPER_3(cpsr_write, void, env, i32, i32)
> +DEF_HELPER_1(cpsr_read, i32, env)
>
> DEF_HELPER_3(v7m_msr, void, env, i32, i32)
> DEF_HELPER_2(v7m_mrs, i32, env, i32)
> @@ -67,8 +67,8 @@ DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
> DEF_HELPER_2(get_r13_banked, i32, env, i32)
> DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
>
> -DEF_HELPER_1(get_user_reg, i32, i32)
> -DEF_HELPER_2(set_user_reg, void, i32, i32)
> +DEF_HELPER_2(get_user_reg, i32, env, i32)
> +DEF_HELPER_3(set_user_reg, void, env, i32, i32)
>
> DEF_HELPER_1(vfp_get_fpscr, i32, env)
> DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
> @@ -140,20 +140,20 @@ DEF_HELPER_2(recpe_f32, f32, f32, env)
> DEF_HELPER_2(rsqrte_f32, f32, f32, env)
> DEF_HELPER_2(recpe_u32, i32, i32, env)
> DEF_HELPER_2(rsqrte_u32, i32, i32, env)
> -DEF_HELPER_4(neon_tbl, i32, i32, i32, i32, i32)
> -
> -DEF_HELPER_2(add_cc, i32, i32, i32)
> -DEF_HELPER_2(adc_cc, i32, i32, i32)
> -DEF_HELPER_2(sub_cc, i32, i32, i32)
> -DEF_HELPER_2(sbc_cc, i32, i32, i32)
> -
> -DEF_HELPER_2(shl, i32, i32, i32)
> -DEF_HELPER_2(shr, i32, i32, i32)
> -DEF_HELPER_2(sar, i32, i32, i32)
> -DEF_HELPER_2(shl_cc, i32, i32, i32)
> -DEF_HELPER_2(shr_cc, i32, i32, i32)
> -DEF_HELPER_2(sar_cc, i32, i32, i32)
> -DEF_HELPER_2(ror_cc, i32, i32, i32)
> +DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32)
> +
> +DEF_HELPER_3(add_cc, i32, env, i32, i32)
> +DEF_HELPER_3(adc_cc, i32, env, i32, i32)
> +DEF_HELPER_3(sub_cc, i32, env, i32, i32)
> +DEF_HELPER_3(sbc_cc, i32, env, i32, i32)
> +
> +DEF_HELPER_3(shl, i32, env, i32, i32)
> +DEF_HELPER_3(shr, i32, env, i32, i32)
> +DEF_HELPER_3(sar, i32, env, i32, i32)
> +DEF_HELPER_3(shl_cc, i32, env, i32, i32)
> +DEF_HELPER_3(shr_cc, i32, env, i32, i32)
> +DEF_HELPER_3(sar_cc, i32, env, i32, i32)
> +DEF_HELPER_3(ror_cc, i32, env, i32, i32)
>
> /* neon_helper.c */
> DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32)
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index d77bfab..f13fc3a 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -17,19 +17,18 @@
> * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> */
> #include "cpu.h"
> -#include "dyngen-exec.h"
> #include "helper.h"
>
> #define SIGNBIT (uint32_t)0x80000000
> #define SIGNBIT64 ((uint64_t)1 << 63)
>
> -static void raise_exception(int tt)
> +static void raise_exception(CPUARMState *env, int tt)
> {
> env->exception_index = tt;
> cpu_loop_exit(env);
> }
>
> -uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
> +uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
> uint32_t rn, uint32_t maxindex)
> {
> uint32_t val;
> @@ -72,16 +71,12 @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
> /* try to fill the TLB and return an exception if error. If retaddr is
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> -/* XXX: fix it to restore all registers */
> -void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> TranslationBlock *tb;
> - CPUARMState *saved_env;
> int ret;
>
> - saved_env = env;
> - env = env1;
> ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> @@ -93,15 +88,14 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
> cpu_restore_state(tb, env, retaddr);
> }
> }
> - raise_exception(env->exception_index);
> + raise_exception(env, env->exception_index);
> }
> - env = saved_env;
> }
> #endif
>
> /* FIXME: Pass an explicit pointer to QF to CPUARMState, and move saturating
> instructions into helper.c */
> -uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
> +uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t res = a + b;
> if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
> @@ -109,7 +103,7 @@ uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
> return res;
> }
>
> -uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
> +uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t res = a + b;
> if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
> @@ -119,7 +113,7 @@ uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
> return res;
> }
>
> -uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
> +uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t res = a - b;
> if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
> @@ -129,7 +123,7 @@ uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
> return res;
> }
>
> -uint32_t HELPER(double_saturate)(int32_t val)
> +uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
> {
> uint32_t res;
> if (val >= 0x40000000) {
> @@ -144,7 +138,7 @@ uint32_t HELPER(double_saturate)(int32_t val)
> return res;
> }
>
> -uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b)
> +uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t res = a + b;
> if (res < a) {
> @@ -154,7 +148,7 @@ uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b)
> return res;
> }
>
> -uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b)
> +uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t res = a - b;
> if (res > a) {
> @@ -165,7 +159,7 @@ uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b)
> }
>
> /* Signed saturation. */
> -static inline uint32_t do_ssat(int32_t val, int shift)
> +static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
> {
> int32_t top;
> uint32_t mask;
> @@ -183,7 +177,7 @@ static inline uint32_t do_ssat(int32_t val, int shift)
> }
>
> /* Unsigned saturation. */
> -static inline uint32_t do_usat(int32_t val, int shift)
> +static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
> {
> uint32_t max;
>
> @@ -199,62 +193,62 @@ static inline uint32_t do_usat(int32_t val, int shift)
> }
>
> /* Signed saturate. */
> -uint32_t HELPER(ssat)(uint32_t x, uint32_t shift)
> +uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
> {
> - return do_ssat(x, shift);
> + return do_ssat(env, x, shift);
> }
>
> /* Dual halfword signed saturate. */
> -uint32_t HELPER(ssat16)(uint32_t x, uint32_t shift)
> +uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
> {
> uint32_t res;
>
> - res = (uint16_t)do_ssat((int16_t)x, shift);
> - res |= do_ssat(((int32_t)x) >> 16, shift) << 16;
> + res = (uint16_t)do_ssat(env, (int16_t)x, shift);
> + res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
> return res;
> }
>
> /* Unsigned saturate. */
> -uint32_t HELPER(usat)(uint32_t x, uint32_t shift)
> +uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
> {
> - return do_usat(x, shift);
> + return do_usat(env, x, shift);
> }
>
> /* Dual halfword unsigned saturate. */
> -uint32_t HELPER(usat16)(uint32_t x, uint32_t shift)
> +uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
> {
> uint32_t res;
>
> - res = (uint16_t)do_usat((int16_t)x, shift);
> - res |= do_usat(((int32_t)x) >> 16, shift) << 16;
> + res = (uint16_t)do_usat(env, (int16_t)x, shift);
> + res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
> return res;
> }
>
> -void HELPER(wfi)(void)
> +void HELPER(wfi)(CPUARMState *env)
> {
> env->exception_index = EXCP_HLT;
> env->halted = 1;
> cpu_loop_exit(env);
> }
>
> -void HELPER(exception)(uint32_t excp)
> +void HELPER(exception)(CPUARMState *env, uint32_t excp)
> {
> env->exception_index = excp;
> cpu_loop_exit(env);
> }
>
> -uint32_t HELPER(cpsr_read)(void)
> +uint32_t HELPER(cpsr_read)(CPUARMState *env)
> {
> return cpsr_read(env) & ~CPSR_EXEC;
> }
>
> -void HELPER(cpsr_write)(uint32_t val, uint32_t mask)
> +void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
> {
> cpsr_write(env, val, mask);
> }
>
> /* Access to user mode registers from privileged modes. */
> -uint32_t HELPER(get_user_reg)(uint32_t regno)
> +uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
> {
> uint32_t val;
>
> @@ -271,7 +265,7 @@ uint32_t HELPER(get_user_reg)(uint32_t regno)
> return val;
> }
>
> -void HELPER(set_user_reg)(uint32_t regno, uint32_t val)
> +void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
> {
> if (regno == 13) {
> env->banked_r13[0] = val;
> @@ -290,7 +284,7 @@ void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
> const ARMCPRegInfo *ri = rip;
> int excp = ri->writefn(env, ri, value);
> if (excp) {
> - raise_exception(excp);
> + raise_exception(env, excp);
> }
> }
>
> @@ -300,7 +294,7 @@ uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
> uint64_t value;
> int excp = ri->readfn(env, ri, &value);
> if (excp) {
> - raise_exception(excp);
> + raise_exception(env, excp);
> }
> return value;
> }
> @@ -310,7 +304,7 @@ void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
> const ARMCPRegInfo *ri = rip;
> int excp = ri->writefn(env, ri, value);
> if (excp) {
> - raise_exception(excp);
> + raise_exception(env, excp);
> }
> }
>
> @@ -320,7 +314,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
> uint64_t value;
> int excp = ri->readfn(env, ri, &value);
> if (excp) {
> - raise_exception(excp);
> + raise_exception(env, excp);
> }
> return value;
> }
> @@ -329,7 +323,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
> The only way to do that in TCG is a conditional branch, which clobbers
> all our temporaries. For now implement these as helper functions. */
>
> -uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
> +uint32_t HELPER (add_cc)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t result;
> result = a + b;
> @@ -339,7 +333,7 @@ uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
> return result;
> }
>
> -uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
> +uint32_t HELPER(adc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t result;
> if (!env->CF) {
> @@ -354,7 +348,7 @@ uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
> return result;
> }
>
> -uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
> +uint32_t HELPER(sub_cc)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t result;
> result = a - b;
> @@ -364,7 +358,7 @@ uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
> return result;
> }
>
> -uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
> +uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
> {
> uint32_t result;
> if (!env->CF) {
> @@ -381,7 +375,7 @@ uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
>
> /* Similarly for variable shift instructions. */
>
> -uint32_t HELPER(shl)(uint32_t x, uint32_t i)
> +uint32_t HELPER(shl)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32)
> @@ -389,7 +383,7 @@ uint32_t HELPER(shl)(uint32_t x, uint32_t i)
> return x << shift;
> }
>
> -uint32_t HELPER(shr)(uint32_t x, uint32_t i)
> +uint32_t HELPER(shr)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32)
> @@ -397,7 +391,7 @@ uint32_t HELPER(shr)(uint32_t x, uint32_t i)
> return (uint32_t)x >> shift;
> }
>
> -uint32_t HELPER(sar)(uint32_t x, uint32_t i)
> +uint32_t HELPER(sar)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32)
> @@ -405,7 +399,7 @@ uint32_t HELPER(sar)(uint32_t x, uint32_t i)
> return (int32_t)x >> shift;
> }
>
> -uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
> +uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32) {
> @@ -421,7 +415,7 @@ uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
> return x;
> }
>
> -uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
> +uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32) {
> @@ -437,7 +431,7 @@ uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
> return x;
> }
>
> -uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
> +uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift = i & 0xff;
> if (shift >= 32) {
> @@ -450,7 +444,7 @@ uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
> return x;
> }
>
> -uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
> +uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
> {
> int shift1, shift;
> shift1 = i & 0xff;
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index edef79a..f4b447a 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -199,7 +199,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
> static inline void gen_set_cpsr(TCGv var, uint32_t mask)
> {
> TCGv tmp_mask = tcg_const_i32(mask);
> - gen_helper_cpsr_write(var, tmp_mask);
> + gen_helper_cpsr_write(cpu_env, var, tmp_mask);
> tcg_temp_free_i32(tmp_mask);
> }
> /* Set NZCV flags from the high 4 bits of var. */
> @@ -209,7 +209,7 @@ static void gen_exception(int excp)
> {
> TCGv tmp = tcg_temp_new_i32();
> tcg_gen_movi_i32(tmp, excp);
> - gen_helper_exception(tmp);
> + gen_helper_exception(cpu_env, tmp);
> tcg_temp_free_i32(tmp);
> }
>
> @@ -490,16 +490,16 @@ static inline void gen_arm_shift_reg(TCGv var, int shiftop,
> {
> if (flags) {
> switch (shiftop) {
> - case 0: gen_helper_shl_cc(var, var, shift); break;
> - case 1: gen_helper_shr_cc(var, var, shift); break;
> - case 2: gen_helper_sar_cc(var, var, shift); break;
> - case 3: gen_helper_ror_cc(var, var, shift); break;
> + case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break;
> + case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break;
> + case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break;
> + case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break;
> }
> } else {
> switch (shiftop) {
> - case 0: gen_helper_shl(var, var, shift); break;
> - case 1: gen_helper_shr(var, var, shift); break;
> - case 2: gen_helper_sar(var, var, shift); break;
> + case 0: gen_helper_shl(var, cpu_env, var, shift); break;
> + case 1: gen_helper_shr(var, cpu_env, var, shift); break;
> + case 2: gen_helper_sar(var, cpu_env, var, shift); break;
> case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
> tcg_gen_rotr_i32(var, var, shift); break;
> }
> @@ -6121,7 +6121,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
> tmp2 = neon_load_reg(rm, 0);
> tmp4 = tcg_const_i32(rn);
> tmp5 = tcg_const_i32(n);
> - gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
> + gen_helper_neon_tbl(tmp2, cpu_env, tmp2, tmp, tmp4, tmp5);
> tcg_temp_free_i32(tmp);
> if (insn & (1 << 6)) {
> tmp = neon_load_reg(rd, 1);
> @@ -6130,7 +6130,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
> tcg_gen_movi_i32(tmp, 0);
> }
> tmp3 = neon_load_reg(rm, 1);
> - gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
> + gen_helper_neon_tbl(tmp3, cpu_env, tmp3, tmp, tmp4, tmp5);
> tcg_temp_free_i32(tmp5);
> tcg_temp_free_i32(tmp4);
> neon_store_reg(rd, 0, tmp2);
> @@ -6534,7 +6534,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> TCGv addr;
> TCGv_i64 tmp64;
>
> - insn = arm_ldl_code(s->pc, s->bswap_code);
> + insn = arm_ldl_code(env, s->pc, s->bswap_code);
> s->pc += 4;
>
> /* M variants do not implement ARM mode. */
> @@ -6818,7 +6818,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> tmp = load_cpu_field(spsr);
> } else {
> tmp = tcg_temp_new_i32();
> - gen_helper_cpsr_read(tmp);
> + gen_helper_cpsr_read(tmp, cpu_env);
> }
> store_reg(s, rd, tmp);
> }
> @@ -6869,11 +6869,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> tmp = load_reg(s, rm);
> tmp2 = load_reg(s, rn);
> if (op1 & 2)
> - gen_helper_double_saturate(tmp2, tmp2);
> + gen_helper_double_saturate(tmp2, cpu_env, tmp2);
> if (op1 & 1)
> - gen_helper_sub_saturate(tmp, tmp, tmp2);
> + gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
> else
> - gen_helper_add_saturate(tmp, tmp, tmp2);
> + gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> break;
> @@ -6911,7 +6911,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> tcg_temp_free_i64(tmp64);
> if ((sh & 2) == 0) {
> tmp2 = load_reg(s, rn);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> store_reg(s, rd, tmp);
> @@ -6931,7 +6931,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> } else {
> if (op1 == 0) {
> tmp2 = load_reg(s, rn);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> store_reg(s, rd, tmp);
> @@ -7005,11 +7005,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> if (IS_USER(s)) {
> goto illegal_op;
> }
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> gen_exception_return(s, tmp);
> } else {
> if (set_cc) {
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> } else {
> tcg_gen_sub_i32(tmp, tmp, tmp2);
> }
> @@ -7018,7 +7018,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> break;
> case 0x03:
> if (set_cc) {
> - gen_helper_sub_cc(tmp, tmp2, tmp);
> + gen_helper_sub_cc(tmp, cpu_env, tmp2, tmp);
> } else {
> tcg_gen_sub_i32(tmp, tmp2, tmp);
> }
> @@ -7026,7 +7026,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> break;
> case 0x04:
> if (set_cc) {
> - gen_helper_add_cc(tmp, tmp, tmp2);
> + gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
> } else {
> tcg_gen_add_i32(tmp, tmp, tmp2);
> }
> @@ -7034,7 +7034,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> break;
> case 0x05:
> if (set_cc) {
> - gen_helper_adc_cc(tmp, tmp, tmp2);
> + gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
> } else {
> gen_add_carry(tmp, tmp, tmp2);
> }
> @@ -7042,7 +7042,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> break;
> case 0x06:
> if (set_cc) {
> - gen_helper_sbc_cc(tmp, tmp, tmp2);
> + gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
> } else {
> gen_sub_carry(tmp, tmp, tmp2);
> }
> @@ -7050,7 +7050,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> break;
> case 0x07:
> if (set_cc) {
> - gen_helper_sbc_cc(tmp, tmp2, tmp);
> + gen_helper_sbc_cc(tmp, cpu_env, tmp2, tmp);
> } else {
> gen_sub_carry(tmp, tmp2, tmp);
> }
> @@ -7072,13 +7072,13 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> break;
> case 0x0a:
> if (set_cc) {
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp);
> break;
> case 0x0b:
> if (set_cc) {
> - gen_helper_add_cc(tmp, tmp, tmp2);
> + gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp);
> break;
> @@ -7395,9 +7395,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> sh = (insn >> 16) & 0x1f;
> tmp2 = tcg_const_i32(sh);
> if (insn & (1 << 22))
> - gen_helper_usat(tmp, tmp, tmp2);
> + gen_helper_usat(tmp, cpu_env, tmp, tmp2);
> else
> - gen_helper_ssat(tmp, tmp, tmp2);
> + gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> } else if ((insn & 0x00300fe0) == 0x00200f20) {
> @@ -7406,9 +7406,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> sh = (insn >> 16) & 0x1f;
> tmp2 = tcg_const_i32(sh);
> if (insn & (1 << 22))
> - gen_helper_usat16(tmp, tmp, tmp2);
> + gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
> else
> - gen_helper_ssat16(tmp, tmp, tmp2);
> + gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> } else if ((insn & 0x00700fe0) == 0x00000fa0) {
> @@ -7518,7 +7518,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> * however it may overflow considered as a signed
> * operation, in which case we must set the Q flag.
> */
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp2);
> if (insn & (1 << 22)) {
> @@ -7534,7 +7534,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> if (rd != 15)
> {
> tmp2 = load_reg(s, rd);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> store_reg(s, rn, tmp);
> @@ -7719,7 +7719,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> tmp = gen_ld32(addr, IS_USER(s));
> if (user) {
> tmp2 = tcg_const_i32(i);
> - gen_helper_set_user_reg(tmp2, tmp);
> + gen_helper_set_user_reg(cpu_env, tmp2, tmp);
> tcg_temp_free_i32(tmp2);
> tcg_temp_free_i32(tmp);
> } else if (i == rn) {
> @@ -7738,7 +7738,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
> } else if (user) {
> tmp = tcg_temp_new_i32();
> tmp2 = tcg_const_i32(i);
> - gen_helper_get_user_reg(tmp, tmp2);
> + gen_helper_get_user_reg(tmp, cpu_env, tmp2);
> tcg_temp_free_i32(tmp2);
> } else {
> tmp = load_reg(s, i);
> @@ -7865,31 +7865,31 @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCG
> break;
> case 8: /* add */
> if (conds)
> - gen_helper_add_cc(t0, t0, t1);
> + gen_helper_add_cc(t0, cpu_env, t0, t1);
> else
> tcg_gen_add_i32(t0, t0, t1);
> break;
> case 10: /* adc */
> if (conds)
> - gen_helper_adc_cc(t0, t0, t1);
> + gen_helper_adc_cc(t0, cpu_env, t0, t1);
> else
> gen_adc(t0, t1);
> break;
> case 11: /* sbc */
> if (conds)
> - gen_helper_sbc_cc(t0, t0, t1);
> + gen_helper_sbc_cc(t0, cpu_env, t0, t1);
> else
> gen_sub_carry(t0, t0, t1);
> break;
> case 13: /* sub */
> if (conds)
> - gen_helper_sub_cc(t0, t0, t1);
> + gen_helper_sub_cc(t0, cpu_env, t0, t1);
> else
> tcg_gen_sub_i32(t0, t0, t1);
> break;
> case 14: /* rsb */
> if (conds)
> - gen_helper_sub_cc(t0, t1, t0);
> + gen_helper_sub_cc(t0, cpu_env, t1, t0);
> else
> tcg_gen_sub_i32(t0, t1, t0);
> break;
> @@ -7962,7 +7962,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
> /* Fall through to 32-bit decode. */
> }
>
> - insn = arm_lduw_code(s->pc, s->bswap_code);
> + insn = arm_lduw_code(env, s->pc, s->bswap_code);
> s->pc += 2;
> insn |= (uint32_t)insn_hw1 << 16;
>
> @@ -8111,7 +8111,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
> gen_st32(tmp, addr, 0);
> tcg_gen_addi_i32(addr, addr, 4);
> tmp = tcg_temp_new_i32();
> - gen_helper_cpsr_read(tmp);
> + gen_helper_cpsr_read(tmp, cpu_env);
> gen_st32(tmp, addr, 0);
> if (insn & (1 << 21)) {
> if ((insn & (1 << 24)) == 0) {
> @@ -8293,11 +8293,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
> tmp = load_reg(s, rn);
> tmp2 = load_reg(s, rm);
> if (op & 1)
> - gen_helper_double_saturate(tmp, tmp);
> + gen_helper_double_saturate(tmp, cpu_env, tmp);
> if (op & 2)
> - gen_helper_sub_saturate(tmp, tmp2, tmp);
> + gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
> else
> - gen_helper_add_saturate(tmp, tmp, tmp2);
> + gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> } else {
> tmp = load_reg(s, rn);
> @@ -8353,7 +8353,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
> tcg_temp_free_i32(tmp2);
> if (rs != 15) {
> tmp2 = load_reg(s, rs);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> break;
> @@ -8370,13 +8370,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
> * however it may overflow considered as a signed
> * operation, in which case we must set the Q flag.
> */
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp2);
> if (rs != 15)
> {
> tmp2 = load_reg(s, rs);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> break;
> @@ -8393,7 +8393,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
> if (rs != 15)
> {
> tmp2 = load_reg(s, rs);
> - gen_helper_add_setq(tmp, tmp, tmp2);
> + gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> }
> break;
> @@ -8632,7 +8632,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
> gen_helper_v7m_mrs(tmp, cpu_env, addr);
> tcg_temp_free_i32(addr);
> } else {
> - gen_helper_cpsr_read(tmp);
> + gen_helper_cpsr_read(tmp, cpu_env);
> }
> store_reg(s, rd, tmp);
> break;
> @@ -8721,15 +8721,15 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
> if (op & 4) {
> /* Unsigned. */
> if ((op & 1) && shift == 0)
> - gen_helper_usat16(tmp, tmp, tmp2);
> + gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
> else
> - gen_helper_usat(tmp, tmp, tmp2);
> + gen_helper_usat(tmp, cpu_env, tmp, tmp2);
> } else {
> /* Signed. */
> if ((op & 1) && shift == 0)
> - gen_helper_ssat16(tmp, tmp, tmp2);
> + gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
> else
> - gen_helper_ssat(tmp, tmp, tmp2);
> + gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp2);
> break;
> @@ -8992,7 +8992,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
> }
> }
>
> - insn = arm_lduw_code(s->pc, s->bswap_code);
> + insn = arm_lduw_code(env, s->pc, s->bswap_code);
> s->pc += 2;
>
> switch (insn >> 12) {
> @@ -9017,12 +9017,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
> if (s->condexec_mask)
> tcg_gen_sub_i32(tmp, tmp, tmp2);
> else
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> } else {
> if (s->condexec_mask)
> tcg_gen_add_i32(tmp, tmp, tmp2);
> else
> - gen_helper_add_cc(tmp, tmp, tmp2);
> + gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
> }
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> @@ -9053,7 +9053,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
> tcg_gen_movi_i32(tmp2, insn & 0xff);
> switch (op) {
> case 1: /* cmp */
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp);
> tcg_temp_free_i32(tmp2);
> break;
> @@ -9061,7 +9061,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
> if (s->condexec_mask)
> tcg_gen_add_i32(tmp, tmp, tmp2);
> else
> - gen_helper_add_cc(tmp, tmp, tmp2);
> + gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> break;
> @@ -9069,7 +9069,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
> if (s->condexec_mask)
> tcg_gen_sub_i32(tmp, tmp, tmp2);
> else
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> break;
> @@ -9105,7 +9105,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
> case 1: /* cmp */
> tmp = load_reg(s, rd);
> tmp2 = load_reg(s, rm);
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> tcg_temp_free_i32(tmp2);
> tcg_temp_free_i32(tmp);
> break;
> @@ -9166,25 +9166,25 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
> break;
> case 0x2: /* lsl */
> if (s->condexec_mask) {
> - gen_helper_shl(tmp2, tmp2, tmp);
> + gen_helper_shl(tmp2, cpu_env, tmp2, tmp);
> } else {
> - gen_helper_shl_cc(tmp2, tmp2, tmp);
> + gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp);
> gen_logic_CC(tmp2);
> }
> break;
> case 0x3: /* lsr */
> if (s->condexec_mask) {
> - gen_helper_shr(tmp2, tmp2, tmp);
> + gen_helper_shr(tmp2, cpu_env, tmp2, tmp);
> } else {
> - gen_helper_shr_cc(tmp2, tmp2, tmp);
> + gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp);
> gen_logic_CC(tmp2);
> }
> break;
> case 0x4: /* asr */
> if (s->condexec_mask) {
> - gen_helper_sar(tmp2, tmp2, tmp);
> + gen_helper_sar(tmp2, cpu_env, tmp2, tmp);
> } else {
> - gen_helper_sar_cc(tmp2, tmp2, tmp);
> + gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp);
> gen_logic_CC(tmp2);
> }
> break;
> @@ -9192,20 +9192,20 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
> if (s->condexec_mask)
> gen_adc(tmp, tmp2);
> else
> - gen_helper_adc_cc(tmp, tmp, tmp2);
> + gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
> break;
> case 0x6: /* sbc */
> if (s->condexec_mask)
> gen_sub_carry(tmp, tmp, tmp2);
> else
> - gen_helper_sbc_cc(tmp, tmp, tmp2);
> + gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
> break;
> case 0x7: /* ror */
> if (s->condexec_mask) {
> tcg_gen_andi_i32(tmp, tmp, 0x1f);
> tcg_gen_rotr_i32(tmp2, tmp2, tmp);
> } else {
> - gen_helper_ror_cc(tmp2, tmp2, tmp);
> + gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp);
> gen_logic_CC(tmp2);
> }
> break;
> @@ -9218,14 +9218,14 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
> if (s->condexec_mask)
> tcg_gen_neg_i32(tmp, tmp2);
> else
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> break;
> case 0xa: /* cmp */
> - gen_helper_sub_cc(tmp, tmp, tmp2);
> + gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
> rd = 16;
> break;
> case 0xb: /* cmn */
> - gen_helper_add_cc(tmp, tmp, tmp2);
> + gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
> rd = 16;
> break;
> case 0xc: /* orr */
> @@ -9913,7 +9913,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
> /* nothing more to generate */
> break;
> case DISAS_WFI:
> - gen_helper_wfi();
> + gen_helper_wfi(cpu_env);
> break;
> case DISAS_SWI:
> gen_exception(EXCP_SWI);
> --
> 1.7.2.5
>
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode
2012-09-03 0:01 ` Peter Maydell
@ 2012-09-03 0:03 ` Peter Maydell
2012-09-03 18:58 ` Blue Swirl
0 siblings, 1 reply; 64+ messages in thread
From: Peter Maydell @ 2012-09-03 0:03 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel, Paul Brook
On 3 September 2012 01:01, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 2 September 2012 18:33, Blue Swirl <blauwirbel@gmail.com> wrote:
>> Add an explicit CPUState parameter instead of relying on AREG0
>> and switch to AREG0 free mode.
>>
>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>> ---
>> configure | 2 +-
>> target-arm/Makefile.objs | 2 -
>> target-arm/cpu.h | 10 ++-
>> target-arm/helper.c | 8 +-
>> target-arm/helper.h | 60 +++++++++---------
>> target-arm/op_helper.c | 92 +++++++++++++---------------
>> target-arm/translate.c | 148 +++++++++++++++++++++++-----------------------
>> 7 files changed, 158 insertions(+), 164 deletions(-)
>
> This is too big to easily review -- it's making a change to a lot
> of helpers, and in each case that change affects three places
> (callers, declaration, implementation). That'
Sorry, finger slip meant I sent that half finished. To continue...
That's quite hard to cross-reference when the patch is this big.
I think it would be helpful if you could split it up into patches
touching smaller groups of helpers at once rather than having a
single patch that does them all at once.
thanks
-- PMM
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode
2012-09-03 0:03 ` Peter Maydell
@ 2012-09-03 18:58 ` Blue Swirl
2012-09-03 19:54 ` Peter Maydell
0 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-03 18:58 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, Paul Brook
On Mon, Sep 3, 2012 at 12:03 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 3 September 2012 01:01, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 2 September 2012 18:33, Blue Swirl <blauwirbel@gmail.com> wrote:
>>> Add an explicit CPUState parameter instead of relying on AREG0
>>> and switch to AREG0 free mode.
>>>
>>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>>> ---
>>> configure | 2 +-
>>> target-arm/Makefile.objs | 2 -
>>> target-arm/cpu.h | 10 ++-
>>> target-arm/helper.c | 8 +-
>>> target-arm/helper.h | 60 +++++++++---------
>>> target-arm/op_helper.c | 92 +++++++++++++---------------
>>> target-arm/translate.c | 148 +++++++++++++++++++++++-----------------------
>>> 7 files changed, 158 insertions(+), 164 deletions(-)
>>
>> This is too big to easily review -- it's making a change to a lot
>> of helpers, and in each case that change affects three places
>> (callers, declaration, implementation). That'
>
> Sorry, finger slip meant I sent that half finished. To continue...
>
> That's quite hard to cross-reference when the patch is this big.
> I think it would be helpful if you could split it up into patches
> touching smaller groups of helpers at once rather than having a
> single patch that does them all at once.
For x86, Sparc and s390x I used the approach of splitting op_helper.c
to smaller files first. I didn't do it for ARM since
target-arm/op_helper.c is alread pretty small (<500 lines). It could
be split to saturating ops, condition code setting arithmetic ops and
misc ops, between 100 and 200 lines each. Would that be OK?
It looks like helper.c should be split too (maybe VFP, MMU, CPU init,
CPR), but that's starting to get beyond the scope of the series.
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode
2012-09-03 18:58 ` Blue Swirl
@ 2012-09-03 19:54 ` Peter Maydell
2012-09-03 20:10 ` Blue Swirl
0 siblings, 1 reply; 64+ messages in thread
From: Peter Maydell @ 2012-09-03 19:54 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel, Paul Brook
On 3 September 2012 19:58, Blue Swirl <blauwirbel@gmail.com> wrote:
> On Mon, Sep 3, 2012 at 12:03 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 3 September 2012 01:01, Peter Maydell <peter.maydell@linaro.org> wrote:
>> That's quite hard to cross-reference when the patch is this big.
>> I think it would be helpful if you could split it up into patches
>> touching smaller groups of helpers at once rather than having a
>> single patch that does them all at once.
>
> For x86, Sparc and s390x I used the approach of splitting op_helper.c
> to smaller files first. I didn't do it for ARM since
> target-arm/op_helper.c is alread pretty small (<500 lines). It could
> be split to saturating ops, condition code setting arithmetic ops and
> misc ops, between 100 and 200 lines each. Would that be OK?
I don't want the *file* split, I'd just like to see this *patch*
as 4 or 5 separate patches, not one big one.
(Patch-splitting is a personal preference thing; I generally favour
lots of little patches over big ones.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode
2012-09-03 19:54 ` Peter Maydell
@ 2012-09-03 20:10 ` Blue Swirl
2012-09-03 20:15 ` Peter Maydell
0 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-03 20:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, Paul Brook
On Mon, Sep 3, 2012 at 7:54 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 3 September 2012 19:58, Blue Swirl <blauwirbel@gmail.com> wrote:
>> On Mon, Sep 3, 2012 at 12:03 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>>> On 3 September 2012 01:01, Peter Maydell <peter.maydell@linaro.org> wrote:
>>> That's quite hard to cross-reference when the patch is this big.
>>> I think it would be helpful if you could split it up into patches
>>> touching smaller groups of helpers at once rather than having a
>>> single patch that does them all at once.
>>
>> For x86, Sparc and s390x I used the approach of splitting op_helper.c
>> to smaller files first. I didn't do it for ARM since
>> target-arm/op_helper.c is alread pretty small (<500 lines). It could
>> be split to saturating ops, condition code setting arithmetic ops and
>> misc ops, between 100 and 200 lines each. Would that be OK?
>
> I don't want the *file* split, I'd just like to see this *patch*
> as 4 or 5 separate patches, not one big one.
While converting, it's easier to work on whole files but maybe the
resulting patch can be still split.
>
> (Patch-splitting is a personal preference thing; I generally favour
> lots of little patches over big ones.)
That's just common sense. The conversion logic is just not very helpful here.
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode
2012-09-03 20:10 ` Blue Swirl
@ 2012-09-03 20:15 ` Peter Maydell
0 siblings, 0 replies; 64+ messages in thread
From: Peter Maydell @ 2012-09-03 20:15 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel, Paul Brook
On 3 September 2012 21:10, Blue Swirl <blauwirbel@gmail.com> wrote:
> On Mon, Sep 3, 2012 at 7:54 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> I don't want the *file* split, I'd just like to see this *patch*
>> as 4 or 5 separate patches, not one big one.
>
> While converting, it's easier to work on whole files but maybe the
> resulting patch can be still split.
If it really doesn't seem splittable let me know and I'll wade
through this big patch.
-- PMM
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 16/21] target-arm: switch to AREG0 free mode
2012-09-02 17:33 ` [Qemu-devel] [PATCH 16/21] target-arm: " Blue Swirl
2012-09-03 0:01 ` Peter Maydell
@ 2012-09-03 13:33 ` Peter Maydell
1 sibling, 0 replies; 64+ messages in thread
From: Peter Maydell @ 2012-09-03 13:33 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel, Paul Brook
On 2 September 2012 18:33, Blue Swirl <blauwirbel@gmail.com> wrote:
> Add an explicit CPUState parameter instead of relying on AREG0
> and switch to AREG0 free mode.
My cheesy test harness for running a popular embedded benchmark
in system mode (x86-64 host, ARM guest) shows mostly slowdowns of
between 2 and 3% with this patch applied. I think that falls into
"not fantastic but acceptable for the cleanup".
-- PMM
^ permalink raw reply [flat|nested] 64+ messages in thread
* [Qemu-devel] [PATCH 17/21] target-microblaze: switch to AREG0 free mode
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (15 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 16/21] target-arm: " Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-06 15:38 ` Aurelien Jarno
2012-09-02 17:33 ` [Qemu-devel] [PATCH 18/21] target-cris: " Blue Swirl
` (4 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Edgar E. Iglesias
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
configure | 2 +-
target-microblaze/Makefile.objs | 2 -
target-microblaze/helper.h | 48 ++++++++--------
target-microblaze/op_helper.c | 115 ++++++++++++++++++---------------------
target-microblaze/translate.c | 56 +++++++++++---------
5 files changed, 108 insertions(+), 115 deletions(-)
diff --git a/configure b/configure
index efb5014..e464d2f 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
case "$target_arch2" in
- alpha | arm* | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
+ alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
;;
esac
diff --git a/target-microblaze/Makefile.objs b/target-microblaze/Makefile.objs
index 4b09e8c..afb87bc 100644
--- a/target-microblaze/Makefile.objs
+++ b/target-microblaze/Makefile.objs
@@ -1,4 +1,2 @@
obj-y += translate.o op_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-microblaze/helper.h b/target-microblaze/helper.h
index 9dcfb0f..a1a732c 100644
--- a/target-microblaze/helper.h
+++ b/target-microblaze/helper.h
@@ -1,39 +1,39 @@
#include "def-helper.h"
-DEF_HELPER_1(raise_exception, void, i32)
-DEF_HELPER_0(debug, void)
+DEF_HELPER_2(raise_exception, void, env, i32)
+DEF_HELPER_1(debug, void, env)
DEF_HELPER_FLAGS_3(carry, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32, i32, i32)
DEF_HELPER_2(cmp, i32, i32, i32)
DEF_HELPER_2(cmpu, i32, i32, i32)
DEF_HELPER_FLAGS_1(clz, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32)
-DEF_HELPER_2(divs, i32, i32, i32)
-DEF_HELPER_2(divu, i32, i32, i32)
-
-DEF_HELPER_2(fadd, i32, i32, i32)
-DEF_HELPER_2(frsub, i32, i32, i32)
-DEF_HELPER_2(fmul, i32, i32, i32)
-DEF_HELPER_2(fdiv, i32, i32, i32)
-DEF_HELPER_1(flt, i32, i32)
-DEF_HELPER_1(fint, i32, i32)
-DEF_HELPER_1(fsqrt, i32, i32)
-
-DEF_HELPER_2(fcmp_un, i32, i32, i32)
-DEF_HELPER_2(fcmp_lt, i32, i32, i32)
-DEF_HELPER_2(fcmp_eq, i32, i32, i32)
-DEF_HELPER_2(fcmp_le, i32, i32, i32)
-DEF_HELPER_2(fcmp_gt, i32, i32, i32)
-DEF_HELPER_2(fcmp_ne, i32, i32, i32)
-DEF_HELPER_2(fcmp_ge, i32, i32, i32)
+DEF_HELPER_3(divs, i32, env, i32, i32)
+DEF_HELPER_3(divu, i32, env, i32, i32)
+
+DEF_HELPER_3(fadd, i32, env, i32, i32)
+DEF_HELPER_3(frsub, i32, env, i32, i32)
+DEF_HELPER_3(fmul, i32, env, i32, i32)
+DEF_HELPER_3(fdiv, i32, env, i32, i32)
+DEF_HELPER_2(flt, i32, env, i32)
+DEF_HELPER_2(fint, i32, env, i32)
+DEF_HELPER_2(fsqrt, i32, env, i32)
+
+DEF_HELPER_3(fcmp_un, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_lt, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_eq, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_le, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_gt, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_ne, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_ge, i32, env, i32, i32)
DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32, i32)
#if !defined(CONFIG_USER_ONLY)
-DEF_HELPER_1(mmu_read, i32, i32)
-DEF_HELPER_2(mmu_write, void, i32, i32)
+DEF_HELPER_2(mmu_read, i32, env, i32)
+DEF_HELPER_3(mmu_write, void, env, i32, i32)
#endif
-DEF_HELPER_4(memalign, void, i32, i32, i32, i32)
-DEF_HELPER_1(stackprot, void, i32)
+DEF_HELPER_5(memalign, void, env, i32, i32, i32, i32)
+DEF_HELPER_2(stackprot, void, env, i32)
DEF_HELPER_2(get, i32, i32, i32)
DEF_HELPER_3(put, void, i32, i32, i32)
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 3b1f072..c9789f4 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -20,7 +20,6 @@
#include <assert.h>
#include "cpu.h"
-#include "dyngen-exec.h"
#include "helper.h"
#include "host-utils.h"
@@ -42,17 +41,12 @@
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
TranslationBlock *tb;
- CPUMBState *saved_env;
int ret;
- saved_env = env;
- env = env1;
-
ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
@@ -66,7 +60,6 @@ void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx,
}
cpu_loop_exit(env);
}
- env = saved_env;
}
#endif
@@ -105,13 +98,13 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
return 0xdead0000 | id;
}
-void helper_raise_exception(uint32_t index)
+void helper_raise_exception(CPUMBState *env, uint32_t index)
{
env->exception_index = index;
cpu_loop_exit(env);
}
-void helper_debug(void)
+void helper_debug(CPUMBState *env)
{
int i;
@@ -176,7 +169,7 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
return ncf;
}
-static inline int div_prepare(uint32_t a, uint32_t b)
+static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
{
if (b == 0) {
env->sregs[SR_MSR] |= MSR_DZ;
@@ -184,7 +177,7 @@ static inline int div_prepare(uint32_t a, uint32_t b)
if ((env->sregs[SR_MSR] & MSR_EE)
&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
env->sregs[SR_ESR] = ESR_EC_DIVZERO;
- helper_raise_exception(EXCP_HW_EXCP);
+ helper_raise_exception(env, EXCP_HW_EXCP);
}
return 0;
}
@@ -192,28 +185,30 @@ static inline int div_prepare(uint32_t a, uint32_t b)
return 1;
}
-uint32_t helper_divs(uint32_t a, uint32_t b)
+uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
{
- if (!div_prepare(a, b))
+ if (!div_prepare(env, a, b)) {
return 0;
+ }
return (int32_t)a / (int32_t)b;
}
-uint32_t helper_divu(uint32_t a, uint32_t b)
+uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
{
- if (!div_prepare(a, b))
+ if (!div_prepare(env, a, b)) {
return 0;
+ }
return a / b;
}
/* raise FPU exception. */
-static void raise_fpu_exception(void)
+static void raise_fpu_exception(CPUMBState *env)
{
env->sregs[SR_ESR] = ESR_EC_FPU;
- helper_raise_exception(EXCP_HW_EXCP);
+ helper_raise_exception(env, EXCP_HW_EXCP);
}
-static void update_fpu_flags(int flags)
+static void update_fpu_flags(CPUMBState *env, int flags)
{
int raise = 0;
@@ -236,11 +231,11 @@ static void update_fpu_flags(int flags)
if (raise
&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
&& (env->sregs[SR_MSR] & MSR_EE)) {
- raise_fpu_exception();
+ raise_fpu_exception(env);
}
}
-uint32_t helper_fadd(uint32_t a, uint32_t b)
+uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fd, fa, fb;
int flags;
@@ -251,11 +246,11 @@ uint32_t helper_fadd(uint32_t a, uint32_t b)
fd.f = float32_add(fa.f, fb.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags);
+ update_fpu_flags(env, flags);
return fd.l;
}
-uint32_t helper_frsub(uint32_t a, uint32_t b)
+uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fd, fa, fb;
int flags;
@@ -265,11 +260,11 @@ uint32_t helper_frsub(uint32_t a, uint32_t b)
fb.l = b;
fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags);
+ update_fpu_flags(env, flags);
return fd.l;
}
-uint32_t helper_fmul(uint32_t a, uint32_t b)
+uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fd, fa, fb;
int flags;
@@ -279,12 +274,12 @@ uint32_t helper_fmul(uint32_t a, uint32_t b)
fb.l = b;
fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags);
+ update_fpu_flags(env, flags);
return fd.l;
}
-uint32_t helper_fdiv(uint32_t a, uint32_t b)
+uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fd, fa, fb;
int flags;
@@ -294,12 +289,12 @@ uint32_t helper_fdiv(uint32_t a, uint32_t b)
fb.l = b;
fd.f = float32_div(fb.f, fa.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags);
+ update_fpu_flags(env, flags);
return fd.l;
}
-uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
+uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fa, fb;
uint32_t r = 0;
@@ -308,7 +303,7 @@ uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
fb.l = b;
if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
- update_fpu_flags(float_flag_invalid);
+ update_fpu_flags(env, float_flag_invalid);
r = 1;
}
@@ -319,7 +314,7 @@ uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
return r;
}
-uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
+uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fa, fb;
int r;
@@ -330,12 +325,12 @@ uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
fb.l = b;
r = float32_lt(fb.f, fa.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags & float_flag_invalid);
+ update_fpu_flags(env, flags & float_flag_invalid);
return r;
}
-uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
+uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fa, fb;
int flags;
@@ -346,12 +341,12 @@ uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
fb.l = b;
r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags & float_flag_invalid);
+ update_fpu_flags(env, flags & float_flag_invalid);
return r;
}
-uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
+uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fa, fb;
int flags;
@@ -362,13 +357,13 @@ uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
set_float_exception_flags(0, &env->fp_status);
r = float32_le(fa.f, fb.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags & float_flag_invalid);
+ update_fpu_flags(env, flags & float_flag_invalid);
return r;
}
-uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
+uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fa, fb;
int flags, r;
@@ -378,11 +373,11 @@ uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
set_float_exception_flags(0, &env->fp_status);
r = float32_lt(fa.f, fb.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags & float_flag_invalid);
+ update_fpu_flags(env, flags & float_flag_invalid);
return r;
}
-uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
+uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fa, fb;
int flags, r;
@@ -392,12 +387,12 @@ uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
set_float_exception_flags(0, &env->fp_status);
r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags & float_flag_invalid);
+ update_fpu_flags(env, flags & float_flag_invalid);
return r;
}
-uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
+uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fa, fb;
int flags, r;
@@ -407,12 +402,12 @@ uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
set_float_exception_flags(0, &env->fp_status);
r = !float32_lt(fa.f, fb.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags & float_flag_invalid);
+ update_fpu_flags(env, flags & float_flag_invalid);
return r;
}
-uint32_t helper_flt(uint32_t a)
+uint32_t helper_flt(CPUMBState *env, uint32_t a)
{
CPU_FloatU fd, fa;
@@ -421,7 +416,7 @@ uint32_t helper_flt(uint32_t a)
return fd.l;
}
-uint32_t helper_fint(uint32_t a)
+uint32_t helper_fint(CPUMBState *env, uint32_t a)
{
CPU_FloatU fa;
uint32_t r;
@@ -431,12 +426,12 @@ uint32_t helper_fint(uint32_t a)
fa.l = a;
r = float32_to_int32(fa.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags);
+ update_fpu_flags(env, flags);
return r;
}
-uint32_t helper_fsqrt(uint32_t a)
+uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
{
CPU_FloatU fd, fa;
int flags;
@@ -445,7 +440,7 @@ uint32_t helper_fsqrt(uint32_t a)
fa.l = a;
fd.l = float32_sqrt(fa.f, &env->fp_status);
flags = get_float_exception_flags(&env->fp_status);
- update_fpu_flags(flags);
+ update_fpu_flags(env, flags);
return fd.l;
}
@@ -463,7 +458,8 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
return 0;
}
-void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
+void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
+ uint32_t mask)
{
if (addr & mask) {
qemu_log_mask(CPU_LOG_INT,
@@ -478,45 +474,39 @@ void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
if (!(env->sregs[SR_MSR] & MSR_EE)) {
return;
}
- helper_raise_exception(EXCP_HW_EXCP);
+ helper_raise_exception(env, EXCP_HW_EXCP);
}
}
-void helper_stackprot(uint32_t addr)
+void helper_stackprot(CPUMBState *env, uint32_t addr)
{
if (addr < env->slr || addr > env->shr) {
qemu_log("Stack protector violation at %x %x %x\n",
addr, env->slr, env->shr);
env->sregs[SR_EAR] = addr;
env->sregs[SR_ESR] = ESR_EC_STACKPROT;
- helper_raise_exception(EXCP_HW_EXCP);
+ helper_raise_exception(env, EXCP_HW_EXCP);
}
}
#if !defined(CONFIG_USER_ONLY)
/* Writes/reads to the MMU's special regs end up here. */
-uint32_t helper_mmu_read(uint32_t rn)
+uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
{
return mmu_read(env, rn);
}
-void helper_mmu_write(uint32_t rn, uint32_t v)
+void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
mmu_write(env, rn, v);
}
-void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUMBState *env, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size)
{
- CPUMBState *saved_env;
-
- saved_env = env;
- env = env1;
-
qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
addr, is_write, is_exec);
if (!(env->sregs[SR_MSR] & MSR_EE)) {
- env = saved_env;
return;
}
@@ -524,14 +514,13 @@ void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
if (is_exec) {
if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
- helper_raise_exception(EXCP_HW_EXCP);
+ helper_raise_exception(env, EXCP_HW_EXCP);
}
} else {
if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
- helper_raise_exception(EXCP_HW_EXCP);
+ helper_raise_exception(env, EXCP_HW_EXCP);
}
}
- env = saved_env;
}
#endif
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 7470149..7c25530 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -126,7 +126,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
t_sync_flags(dc);
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
- gen_helper_raise_exception(tmp);
+ gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
dc->is_jmp = DISAS_UPDATE;
}
@@ -503,9 +503,9 @@ static void dec_msr(DisasContext *dc)
sr &= 7;
LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
if (to)
- gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
+ gen_helper_mmu_write(cpu_env, tcg_const_tl(sr), cpu_R[dc->ra]);
else
- gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
+ gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_tl(sr));
return;
}
#endif
@@ -704,9 +704,11 @@ static void dec_div(DisasContext *dc)
}
if (u)
- gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
+ gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
+ cpu_R[dc->ra]);
else
- gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
+ gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
+ cpu_R[dc->ra]);
if (!dc->rd)
tcg_gen_movi_tl(cpu_R[dc->rd], 0);
}
@@ -912,7 +914,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
if (stackprot) {
- gen_helper_stackprot(*t);
+ gen_helper_stackprot(cpu_env, *t);
}
return t;
}
@@ -930,7 +932,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
}
if (stackprot) {
- gen_helper_stackprot(*t);
+ gen_helper_stackprot(cpu_env, *t);
}
return t;
}
@@ -1056,7 +1058,7 @@ static void dec_load(DisasContext *dc)
gen_load(dc, v, *addr, size);
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
- gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
+ gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
tcg_const_tl(0), tcg_const_tl(size - 1));
if (dc->rd) {
if (rev) {
@@ -1218,7 +1220,7 @@ static void dec_store(DisasContext *dc)
* the alignment checks in between the probe and the mem
* access.
*/
- gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
+ gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
tcg_const_tl(1), tcg_const_tl(size - 1));
}
@@ -1493,49 +1495,53 @@ static void dec_fpu(DisasContext *dc)
switch (fpu_insn) {
case 0:
- gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
+ gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
+ cpu_R[dc->rb]);
break;
case 1:
- gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
+ gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
+ cpu_R[dc->rb]);
break;
case 2:
- gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
+ gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
+ cpu_R[dc->rb]);
break;
case 3:
- gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
+ gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
+ cpu_R[dc->rb]);
break;
case 4:
switch ((dc->ir >> 4) & 7) {
case 0:
- gen_helper_fcmp_un(cpu_R[dc->rd],
+ gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env,
cpu_R[dc->ra], cpu_R[dc->rb]);
break;
case 1:
- gen_helper_fcmp_lt(cpu_R[dc->rd],
+ gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env,
cpu_R[dc->ra], cpu_R[dc->rb]);
break;
case 2:
- gen_helper_fcmp_eq(cpu_R[dc->rd],
+ gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env,
cpu_R[dc->ra], cpu_R[dc->rb]);
break;
case 3:
- gen_helper_fcmp_le(cpu_R[dc->rd],
+ gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env,
cpu_R[dc->ra], cpu_R[dc->rb]);
break;
case 4:
- gen_helper_fcmp_gt(cpu_R[dc->rd],
+ gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env,
cpu_R[dc->ra], cpu_R[dc->rb]);
break;
case 5:
- gen_helper_fcmp_ne(cpu_R[dc->rd],
+ gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env,
cpu_R[dc->ra], cpu_R[dc->rb]);
break;
case 6:
- gen_helper_fcmp_ge(cpu_R[dc->rd],
+ gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env,
cpu_R[dc->ra], cpu_R[dc->rb]);
break;
default:
@@ -1552,21 +1558,21 @@ static void dec_fpu(DisasContext *dc)
if (!dec_check_fpuv2(dc)) {
return;
}
- gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]);
+ gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
break;
case 6:
if (!dec_check_fpuv2(dc)) {
return;
}
- gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]);
+ gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
break;
case 7:
if (!dec_check_fpuv2(dc)) {
return;
}
- gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]);
+ gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
break;
default:
@@ -1662,7 +1668,7 @@ static inline void decode(DisasContext *dc)
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
tcg_gen_debug_insn_start(dc->pc);
- dc->ir = ir = ldl_code(dc->pc);
+ dc->ir = ir = cpu_ldl_code(cpu_single_env, dc->pc);
LOG_DIS("%8.8x\t", dc->ir);
if (dc->ir)
@@ -1871,7 +1877,7 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
if (dc->is_jmp != DISAS_JUMP) {
tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
}
- gen_helper_raise_exception(tmp);
+ gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
} else {
switch(dc->is_jmp) {
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 17/21] target-microblaze: switch to AREG0 free mode
2012-09-02 17:33 ` [Qemu-devel] [PATCH 17/21] target-microblaze: " Blue Swirl
@ 2012-09-06 15:38 ` Aurelien Jarno
2012-09-08 7:36 ` Blue Swirl
0 siblings, 1 reply; 64+ messages in thread
From: Aurelien Jarno @ 2012-09-06 15:38 UTC (permalink / raw)
To: Blue Swirl; +Cc: Edgar E. Iglesias, qemu-devel
On Sun, Sep 02, 2012 at 05:33:46PM +0000, Blue Swirl wrote:
> Add an explicit CPUState parameter instead of relying on AREG0
> and switch to AREG0 free mode.
>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> ---
> configure | 2 +-
> target-microblaze/Makefile.objs | 2 -
> target-microblaze/helper.h | 48 ++++++++--------
> target-microblaze/op_helper.c | 115 ++++++++++++++++++---------------------
> target-microblaze/translate.c | 56 +++++++++++---------
> 5 files changed, 108 insertions(+), 115 deletions(-)
>
> diff --git a/configure b/configure
> index efb5014..e464d2f 100755
> --- a/configure
> +++ b/configure
> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
>
>
> case "$target_arch2" in
> - alpha | arm* | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> + alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
> ;;
> esac
> diff --git a/target-microblaze/Makefile.objs b/target-microblaze/Makefile.objs
> index 4b09e8c..afb87bc 100644
> --- a/target-microblaze/Makefile.objs
> +++ b/target-microblaze/Makefile.objs
> @@ -1,4 +1,2 @@
> obj-y += translate.o op_helper.o helper.o cpu.o
> obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
> -
> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> diff --git a/target-microblaze/helper.h b/target-microblaze/helper.h
> index 9dcfb0f..a1a732c 100644
> --- a/target-microblaze/helper.h
> +++ b/target-microblaze/helper.h
> @@ -1,39 +1,39 @@
> #include "def-helper.h"
>
> -DEF_HELPER_1(raise_exception, void, i32)
> -DEF_HELPER_0(debug, void)
> +DEF_HELPER_2(raise_exception, void, env, i32)
> +DEF_HELPER_1(debug, void, env)
> DEF_HELPER_FLAGS_3(carry, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32, i32, i32)
> DEF_HELPER_2(cmp, i32, i32, i32)
> DEF_HELPER_2(cmpu, i32, i32, i32)
> DEF_HELPER_FLAGS_1(clz, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32)
>
> -DEF_HELPER_2(divs, i32, i32, i32)
> -DEF_HELPER_2(divu, i32, i32, i32)
> -
> -DEF_HELPER_2(fadd, i32, i32, i32)
> -DEF_HELPER_2(frsub, i32, i32, i32)
> -DEF_HELPER_2(fmul, i32, i32, i32)
> -DEF_HELPER_2(fdiv, i32, i32, i32)
> -DEF_HELPER_1(flt, i32, i32)
> -DEF_HELPER_1(fint, i32, i32)
> -DEF_HELPER_1(fsqrt, i32, i32)
> -
> -DEF_HELPER_2(fcmp_un, i32, i32, i32)
> -DEF_HELPER_2(fcmp_lt, i32, i32, i32)
> -DEF_HELPER_2(fcmp_eq, i32, i32, i32)
> -DEF_HELPER_2(fcmp_le, i32, i32, i32)
> -DEF_HELPER_2(fcmp_gt, i32, i32, i32)
> -DEF_HELPER_2(fcmp_ne, i32, i32, i32)
> -DEF_HELPER_2(fcmp_ge, i32, i32, i32)
> +DEF_HELPER_3(divs, i32, env, i32, i32)
> +DEF_HELPER_3(divu, i32, env, i32, i32)
> +
> +DEF_HELPER_3(fadd, i32, env, i32, i32)
> +DEF_HELPER_3(frsub, i32, env, i32, i32)
> +DEF_HELPER_3(fmul, i32, env, i32, i32)
> +DEF_HELPER_3(fdiv, i32, env, i32, i32)
> +DEF_HELPER_2(flt, i32, env, i32)
> +DEF_HELPER_2(fint, i32, env, i32)
> +DEF_HELPER_2(fsqrt, i32, env, i32)
> +
> +DEF_HELPER_3(fcmp_un, i32, env, i32, i32)
> +DEF_HELPER_3(fcmp_lt, i32, env, i32, i32)
> +DEF_HELPER_3(fcmp_eq, i32, env, i32, i32)
> +DEF_HELPER_3(fcmp_le, i32, env, i32, i32)
> +DEF_HELPER_3(fcmp_gt, i32, env, i32, i32)
> +DEF_HELPER_3(fcmp_ne, i32, env, i32, i32)
> +DEF_HELPER_3(fcmp_ge, i32, env, i32, i32)
>
> DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32, i32)
> #if !defined(CONFIG_USER_ONLY)
> -DEF_HELPER_1(mmu_read, i32, i32)
> -DEF_HELPER_2(mmu_write, void, i32, i32)
> +DEF_HELPER_2(mmu_read, i32, env, i32)
> +DEF_HELPER_3(mmu_write, void, env, i32, i32)
> #endif
>
> -DEF_HELPER_4(memalign, void, i32, i32, i32, i32)
> -DEF_HELPER_1(stackprot, void, i32)
> +DEF_HELPER_5(memalign, void, env, i32, i32, i32, i32)
> +DEF_HELPER_2(stackprot, void, env, i32)
>
> DEF_HELPER_2(get, i32, i32, i32)
> DEF_HELPER_3(put, void, i32, i32, i32)
> diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
> index 3b1f072..c9789f4 100644
> --- a/target-microblaze/op_helper.c
> +++ b/target-microblaze/op_helper.c
> @@ -20,7 +20,6 @@
>
> #include <assert.h>
> #include "cpu.h"
> -#include "dyngen-exec.h"
> #include "helper.h"
> #include "host-utils.h"
>
> @@ -42,17 +41,12 @@
> /* Try to fill the TLB and return an exception if error. If retaddr is
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> -/* XXX: fix it to restore all registers */
> -void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> TranslationBlock *tb;
> - CPUMBState *saved_env;
> int ret;
>
> - saved_env = env;
> - env = env1;
> -
> ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> @@ -66,7 +60,6 @@ void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx,
> }
> cpu_loop_exit(env);
> }
> - env = saved_env;
> }
> #endif
>
> @@ -105,13 +98,13 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
> return 0xdead0000 | id;
> }
>
> -void helper_raise_exception(uint32_t index)
> +void helper_raise_exception(CPUMBState *env, uint32_t index)
> {
> env->exception_index = index;
> cpu_loop_exit(env);
> }
>
> -void helper_debug(void)
> +void helper_debug(CPUMBState *env)
> {
> int i;
>
> @@ -176,7 +169,7 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
> return ncf;
> }
>
> -static inline int div_prepare(uint32_t a, uint32_t b)
> +static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
> {
> if (b == 0) {
> env->sregs[SR_MSR] |= MSR_DZ;
> @@ -184,7 +177,7 @@ static inline int div_prepare(uint32_t a, uint32_t b)
> if ((env->sregs[SR_MSR] & MSR_EE)
> && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
> env->sregs[SR_ESR] = ESR_EC_DIVZERO;
> - helper_raise_exception(EXCP_HW_EXCP);
> + helper_raise_exception(env, EXCP_HW_EXCP);
> }
> return 0;
> }
> @@ -192,28 +185,30 @@ static inline int div_prepare(uint32_t a, uint32_t b)
> return 1;
> }
>
> -uint32_t helper_divs(uint32_t a, uint32_t b)
> +uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
> {
> - if (!div_prepare(a, b))
> + if (!div_prepare(env, a, b)) {
> return 0;
> + }
> return (int32_t)a / (int32_t)b;
> }
>
> -uint32_t helper_divu(uint32_t a, uint32_t b)
> +uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
> {
> - if (!div_prepare(a, b))
> + if (!div_prepare(env, a, b)) {
> return 0;
> + }
> return a / b;
> }
>
> /* raise FPU exception. */
> -static void raise_fpu_exception(void)
> +static void raise_fpu_exception(CPUMBState *env)
> {
> env->sregs[SR_ESR] = ESR_EC_FPU;
> - helper_raise_exception(EXCP_HW_EXCP);
> + helper_raise_exception(env, EXCP_HW_EXCP);
> }
>
> -static void update_fpu_flags(int flags)
> +static void update_fpu_flags(CPUMBState *env, int flags)
> {
> int raise = 0;
>
> @@ -236,11 +231,11 @@ static void update_fpu_flags(int flags)
> if (raise
> && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
> && (env->sregs[SR_MSR] & MSR_EE)) {
> - raise_fpu_exception();
> + raise_fpu_exception(env);
> }
> }
>
> -uint32_t helper_fadd(uint32_t a, uint32_t b)
> +uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
> {
> CPU_FloatU fd, fa, fb;
> int flags;
> @@ -251,11 +246,11 @@ uint32_t helper_fadd(uint32_t a, uint32_t b)
> fd.f = float32_add(fa.f, fb.f, &env->fp_status);
>
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags);
> + update_fpu_flags(env, flags);
> return fd.l;
> }
>
> -uint32_t helper_frsub(uint32_t a, uint32_t b)
> +uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
> {
> CPU_FloatU fd, fa, fb;
> int flags;
> @@ -265,11 +260,11 @@ uint32_t helper_frsub(uint32_t a, uint32_t b)
> fb.l = b;
> fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags);
> + update_fpu_flags(env, flags);
> return fd.l;
> }
>
> -uint32_t helper_fmul(uint32_t a, uint32_t b)
> +uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
> {
> CPU_FloatU fd, fa, fb;
> int flags;
> @@ -279,12 +274,12 @@ uint32_t helper_fmul(uint32_t a, uint32_t b)
> fb.l = b;
> fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags);
> + update_fpu_flags(env, flags);
>
> return fd.l;
> }
>
> -uint32_t helper_fdiv(uint32_t a, uint32_t b)
> +uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
> {
> CPU_FloatU fd, fa, fb;
> int flags;
> @@ -294,12 +289,12 @@ uint32_t helper_fdiv(uint32_t a, uint32_t b)
> fb.l = b;
> fd.f = float32_div(fb.f, fa.f, &env->fp_status);
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags);
> + update_fpu_flags(env, flags);
>
> return fd.l;
> }
>
> -uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
> +uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
> {
> CPU_FloatU fa, fb;
> uint32_t r = 0;
> @@ -308,7 +303,7 @@ uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
> fb.l = b;
>
> if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
> - update_fpu_flags(float_flag_invalid);
> + update_fpu_flags(env, float_flag_invalid);
> r = 1;
> }
>
> @@ -319,7 +314,7 @@ uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
> return r;
> }
>
> -uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
> +uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
> {
> CPU_FloatU fa, fb;
> int r;
> @@ -330,12 +325,12 @@ uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
> fb.l = b;
> r = float32_lt(fb.f, fa.f, &env->fp_status);
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags & float_flag_invalid);
> + update_fpu_flags(env, flags & float_flag_invalid);
>
> return r;
> }
>
> -uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
> +uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
> {
> CPU_FloatU fa, fb;
> int flags;
> @@ -346,12 +341,12 @@ uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
> fb.l = b;
> r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags & float_flag_invalid);
> + update_fpu_flags(env, flags & float_flag_invalid);
>
> return r;
> }
>
> -uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
> +uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
> {
> CPU_FloatU fa, fb;
> int flags;
> @@ -362,13 +357,13 @@ uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
> set_float_exception_flags(0, &env->fp_status);
> r = float32_le(fa.f, fb.f, &env->fp_status);
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags & float_flag_invalid);
> + update_fpu_flags(env, flags & float_flag_invalid);
>
>
> return r;
> }
>
> -uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
> +uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
> {
> CPU_FloatU fa, fb;
> int flags, r;
> @@ -378,11 +373,11 @@ uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
> set_float_exception_flags(0, &env->fp_status);
> r = float32_lt(fa.f, fb.f, &env->fp_status);
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags & float_flag_invalid);
> + update_fpu_flags(env, flags & float_flag_invalid);
> return r;
> }
>
> -uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
> +uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
> {
> CPU_FloatU fa, fb;
> int flags, r;
> @@ -392,12 +387,12 @@ uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
> set_float_exception_flags(0, &env->fp_status);
> r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags & float_flag_invalid);
> + update_fpu_flags(env, flags & float_flag_invalid);
>
> return r;
> }
>
> -uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
> +uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
> {
> CPU_FloatU fa, fb;
> int flags, r;
> @@ -407,12 +402,12 @@ uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
> set_float_exception_flags(0, &env->fp_status);
> r = !float32_lt(fa.f, fb.f, &env->fp_status);
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags & float_flag_invalid);
> + update_fpu_flags(env, flags & float_flag_invalid);
>
> return r;
> }
>
> -uint32_t helper_flt(uint32_t a)
> +uint32_t helper_flt(CPUMBState *env, uint32_t a)
> {
> CPU_FloatU fd, fa;
>
> @@ -421,7 +416,7 @@ uint32_t helper_flt(uint32_t a)
> return fd.l;
> }
>
> -uint32_t helper_fint(uint32_t a)
> +uint32_t helper_fint(CPUMBState *env, uint32_t a)
> {
> CPU_FloatU fa;
> uint32_t r;
> @@ -431,12 +426,12 @@ uint32_t helper_fint(uint32_t a)
> fa.l = a;
> r = float32_to_int32(fa.f, &env->fp_status);
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags);
> + update_fpu_flags(env, flags);
>
> return r;
> }
>
> -uint32_t helper_fsqrt(uint32_t a)
> +uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
> {
> CPU_FloatU fd, fa;
> int flags;
> @@ -445,7 +440,7 @@ uint32_t helper_fsqrt(uint32_t a)
> fa.l = a;
> fd.l = float32_sqrt(fa.f, &env->fp_status);
> flags = get_float_exception_flags(&env->fp_status);
> - update_fpu_flags(flags);
> + update_fpu_flags(env, flags);
>
> return fd.l;
> }
> @@ -463,7 +458,8 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
> return 0;
> }
>
> -void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
> +void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
> + uint32_t mask)
> {
> if (addr & mask) {
> qemu_log_mask(CPU_LOG_INT,
> @@ -478,45 +474,39 @@ void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
> if (!(env->sregs[SR_MSR] & MSR_EE)) {
> return;
> }
> - helper_raise_exception(EXCP_HW_EXCP);
> + helper_raise_exception(env, EXCP_HW_EXCP);
> }
> }
>
> -void helper_stackprot(uint32_t addr)
> +void helper_stackprot(CPUMBState *env, uint32_t addr)
> {
> if (addr < env->slr || addr > env->shr) {
> qemu_log("Stack protector violation at %x %x %x\n",
> addr, env->slr, env->shr);
> env->sregs[SR_EAR] = addr;
> env->sregs[SR_ESR] = ESR_EC_STACKPROT;
> - helper_raise_exception(EXCP_HW_EXCP);
> + helper_raise_exception(env, EXCP_HW_EXCP);
> }
> }
>
> #if !defined(CONFIG_USER_ONLY)
> /* Writes/reads to the MMU's special regs end up here. */
> -uint32_t helper_mmu_read(uint32_t rn)
> +uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
> {
> return mmu_read(env, rn);
> }
>
> -void helper_mmu_write(uint32_t rn, uint32_t v)
> +void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
> {
> mmu_write(env, rn, v);
> }
>
> -void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
> +void cpu_unassigned_access(CPUMBState *env, target_phys_addr_t addr,
> int is_write, int is_exec, int is_asi, int size)
> {
> - CPUMBState *saved_env;
> -
> - saved_env = env;
> - env = env1;
> -
> qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
> addr, is_write, is_exec);
> if (!(env->sregs[SR_MSR] & MSR_EE)) {
> - env = saved_env;
> return;
> }
>
> @@ -524,14 +514,13 @@ void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
> if (is_exec) {
> if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
> env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
> - helper_raise_exception(EXCP_HW_EXCP);
> + helper_raise_exception(env, EXCP_HW_EXCP);
> }
> } else {
> if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
> env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
> - helper_raise_exception(EXCP_HW_EXCP);
> + helper_raise_exception(env, EXCP_HW_EXCP);
> }
> }
> - env = saved_env;
> }
> #endif
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index 7470149..7c25530 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -126,7 +126,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
>
> t_sync_flags(dc);
> tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
> - gen_helper_raise_exception(tmp);
> + gen_helper_raise_exception(cpu_env, tmp);
> tcg_temp_free_i32(tmp);
> dc->is_jmp = DISAS_UPDATE;
> }
> @@ -503,9 +503,9 @@ static void dec_msr(DisasContext *dc)
> sr &= 7;
> LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
> if (to)
> - gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
> + gen_helper_mmu_write(cpu_env, tcg_const_tl(sr), cpu_R[dc->ra]);
> else
> - gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
> + gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_tl(sr));
> return;
> }
> #endif
> @@ -704,9 +704,11 @@ static void dec_div(DisasContext *dc)
> }
>
> if (u)
> - gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
> + gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
> + cpu_R[dc->ra]);
> else
> - gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
> + gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
> + cpu_R[dc->ra]);
> if (!dc->rd)
> tcg_gen_movi_tl(cpu_R[dc->rd], 0);
> }
> @@ -912,7 +914,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
> tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
>
> if (stackprot) {
> - gen_helper_stackprot(*t);
> + gen_helper_stackprot(cpu_env, *t);
> }
> return t;
> }
> @@ -930,7 +932,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
> }
>
> if (stackprot) {
> - gen_helper_stackprot(*t);
> + gen_helper_stackprot(cpu_env, *t);
> }
> return t;
> }
> @@ -1056,7 +1058,7 @@ static void dec_load(DisasContext *dc)
> gen_load(dc, v, *addr, size);
>
> tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
> - gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
> + gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
> tcg_const_tl(0), tcg_const_tl(size - 1));
> if (dc->rd) {
> if (rev) {
> @@ -1218,7 +1220,7 @@ static void dec_store(DisasContext *dc)
> * the alignment checks in between the probe and the mem
> * access.
> */
> - gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
> + gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
> tcg_const_tl(1), tcg_const_tl(size - 1));
> }
>
> @@ -1493,49 +1495,53 @@ static void dec_fpu(DisasContext *dc)
>
> switch (fpu_insn) {
> case 0:
> - gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
> + gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
> + cpu_R[dc->rb]);
> break;
>
> case 1:
> - gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
> + gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
> + cpu_R[dc->rb]);
> break;
>
> case 2:
> - gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
> + gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
> + cpu_R[dc->rb]);
> break;
>
> case 3:
> - gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
> + gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
> + cpu_R[dc->rb]);
> break;
>
> case 4:
> switch ((dc->ir >> 4) & 7) {
> case 0:
> - gen_helper_fcmp_un(cpu_R[dc->rd],
> + gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env,
> cpu_R[dc->ra], cpu_R[dc->rb]);
> break;
> case 1:
> - gen_helper_fcmp_lt(cpu_R[dc->rd],
> + gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env,
> cpu_R[dc->ra], cpu_R[dc->rb]);
> break;
> case 2:
> - gen_helper_fcmp_eq(cpu_R[dc->rd],
> + gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env,
> cpu_R[dc->ra], cpu_R[dc->rb]);
> break;
> case 3:
> - gen_helper_fcmp_le(cpu_R[dc->rd],
> + gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env,
> cpu_R[dc->ra], cpu_R[dc->rb]);
> break;
> case 4:
> - gen_helper_fcmp_gt(cpu_R[dc->rd],
> + gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env,
> cpu_R[dc->ra], cpu_R[dc->rb]);
> break;
> case 5:
> - gen_helper_fcmp_ne(cpu_R[dc->rd],
> + gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env,
> cpu_R[dc->ra], cpu_R[dc->rb]);
> break;
> case 6:
> - gen_helper_fcmp_ge(cpu_R[dc->rd],
> + gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env,
> cpu_R[dc->ra], cpu_R[dc->rb]);
> break;
> default:
> @@ -1552,21 +1558,21 @@ static void dec_fpu(DisasContext *dc)
> if (!dec_check_fpuv2(dc)) {
> return;
> }
> - gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]);
> + gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
> break;
>
> case 6:
> if (!dec_check_fpuv2(dc)) {
> return;
> }
> - gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]);
> + gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
> break;
>
> case 7:
> if (!dec_check_fpuv2(dc)) {
> return;
> }
> - gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]);
> + gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
> break;
>
> default:
> @@ -1662,7 +1668,7 @@ static inline void decode(DisasContext *dc)
> if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
> tcg_gen_debug_insn_start(dc->pc);
>
> - dc->ir = ir = ldl_code(dc->pc);
> + dc->ir = ir = cpu_ldl_code(cpu_single_env, dc->pc);
> LOG_DIS("%8.8x\t", dc->ir);
Similarly to the sh4 patch, it should be quite easy to just pass env to
decode() and use it there instead of cpu_single_env.
> if (dc->ir)
> @@ -1871,7 +1877,7 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
> if (dc->is_jmp != DISAS_JUMP) {
> tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
> }
> - gen_helper_raise_exception(tmp);
> + gen_helper_raise_exception(cpu_env, tmp);
> tcg_temp_free_i32(tmp);
> } else {
> switch(dc->is_jmp) {
> --
> 1.7.2.5
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 17/21] target-microblaze: switch to AREG0 free mode
2012-09-06 15:38 ` Aurelien Jarno
@ 2012-09-08 7:36 ` Blue Swirl
0 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-08 7:36 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: Edgar E. Iglesias, qemu-devel
On Thu, Sep 6, 2012 at 3:38 PM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Sun, Sep 02, 2012 at 05:33:46PM +0000, Blue Swirl wrote:
>> Add an explicit CPUState parameter instead of relying on AREG0
>> and switch to AREG0 free mode.
>>
>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>> ---
>> configure | 2 +-
>> target-microblaze/Makefile.objs | 2 -
>> target-microblaze/helper.h | 48 ++++++++--------
>> target-microblaze/op_helper.c | 115 ++++++++++++++++++---------------------
>> target-microblaze/translate.c | 56 +++++++++++---------
>> 5 files changed, 108 insertions(+), 115 deletions(-)
>>
>> diff --git a/configure b/configure
>> index efb5014..e464d2f 100755
>> --- a/configure
>> +++ b/configure
>> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
>>
>>
>> case "$target_arch2" in
>> - alpha | arm* | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
>> + alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
>> echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
>> ;;
>> esac
>> diff --git a/target-microblaze/Makefile.objs b/target-microblaze/Makefile.objs
>> index 4b09e8c..afb87bc 100644
>> --- a/target-microblaze/Makefile.objs
>> +++ b/target-microblaze/Makefile.objs
>> @@ -1,4 +1,2 @@
>> obj-y += translate.o op_helper.o helper.o cpu.o
>> obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
>> -
>> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
>> diff --git a/target-microblaze/helper.h b/target-microblaze/helper.h
>> index 9dcfb0f..a1a732c 100644
>> --- a/target-microblaze/helper.h
>> +++ b/target-microblaze/helper.h
>> @@ -1,39 +1,39 @@
>> #include "def-helper.h"
>>
>> -DEF_HELPER_1(raise_exception, void, i32)
>> -DEF_HELPER_0(debug, void)
>> +DEF_HELPER_2(raise_exception, void, env, i32)
>> +DEF_HELPER_1(debug, void, env)
>> DEF_HELPER_FLAGS_3(carry, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32, i32, i32)
>> DEF_HELPER_2(cmp, i32, i32, i32)
>> DEF_HELPER_2(cmpu, i32, i32, i32)
>> DEF_HELPER_FLAGS_1(clz, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32)
>>
>> -DEF_HELPER_2(divs, i32, i32, i32)
>> -DEF_HELPER_2(divu, i32, i32, i32)
>> -
>> -DEF_HELPER_2(fadd, i32, i32, i32)
>> -DEF_HELPER_2(frsub, i32, i32, i32)
>> -DEF_HELPER_2(fmul, i32, i32, i32)
>> -DEF_HELPER_2(fdiv, i32, i32, i32)
>> -DEF_HELPER_1(flt, i32, i32)
>> -DEF_HELPER_1(fint, i32, i32)
>> -DEF_HELPER_1(fsqrt, i32, i32)
>> -
>> -DEF_HELPER_2(fcmp_un, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_lt, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_eq, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_le, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_gt, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_ne, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_ge, i32, i32, i32)
>> +DEF_HELPER_3(divs, i32, env, i32, i32)
>> +DEF_HELPER_3(divu, i32, env, i32, i32)
>> +
>> +DEF_HELPER_3(fadd, i32, env, i32, i32)
>> +DEF_HELPER_3(frsub, i32, env, i32, i32)
>> +DEF_HELPER_3(fmul, i32, env, i32, i32)
>> +DEF_HELPER_3(fdiv, i32, env, i32, i32)
>> +DEF_HELPER_2(flt, i32, env, i32)
>> +DEF_HELPER_2(fint, i32, env, i32)
>> +DEF_HELPER_2(fsqrt, i32, env, i32)
>> +
>> +DEF_HELPER_3(fcmp_un, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_lt, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_eq, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_le, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_gt, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_ne, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_ge, i32, env, i32, i32)
>>
>> DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32, i32)
>> #if !defined(CONFIG_USER_ONLY)
>> -DEF_HELPER_1(mmu_read, i32, i32)
>> -DEF_HELPER_2(mmu_write, void, i32, i32)
>> +DEF_HELPER_2(mmu_read, i32, env, i32)
>> +DEF_HELPER_3(mmu_write, void, env, i32, i32)
>> #endif
>>
>> -DEF_HELPER_4(memalign, void, i32, i32, i32, i32)
>> -DEF_HELPER_1(stackprot, void, i32)
>> +DEF_HELPER_5(memalign, void, env, i32, i32, i32, i32)
>> +DEF_HELPER_2(stackprot, void, env, i32)
>>
>> DEF_HELPER_2(get, i32, i32, i32)
>> DEF_HELPER_3(put, void, i32, i32, i32)
>> diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
>> index 3b1f072..c9789f4 100644
>> --- a/target-microblaze/op_helper.c
>> +++ b/target-microblaze/op_helper.c
>> @@ -20,7 +20,6 @@
>>
>> #include <assert.h>
>> #include "cpu.h"
>> -#include "dyngen-exec.h"
>> #include "helper.h"
>> #include "host-utils.h"
>>
>> @@ -42,17 +41,12 @@
>> /* Try to fill the TLB and return an exception if error. If retaddr is
>> NULL, it means that the function was called in C code (i.e. not
>> from generated code or from helper.c) */
>> -/* XXX: fix it to restore all registers */
>> -void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx,
>> +void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
>> uintptr_t retaddr)
>> {
>> TranslationBlock *tb;
>> - CPUMBState *saved_env;
>> int ret;
>>
>> - saved_env = env;
>> - env = env1;
>> -
>> ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
>> if (unlikely(ret)) {
>> if (retaddr) {
>> @@ -66,7 +60,6 @@ void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx,
>> }
>> cpu_loop_exit(env);
>> }
>> - env = saved_env;
>> }
>> #endif
>>
>> @@ -105,13 +98,13 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
>> return 0xdead0000 | id;
>> }
>>
>> -void helper_raise_exception(uint32_t index)
>> +void helper_raise_exception(CPUMBState *env, uint32_t index)
>> {
>> env->exception_index = index;
>> cpu_loop_exit(env);
>> }
>>
>> -void helper_debug(void)
>> +void helper_debug(CPUMBState *env)
>> {
>> int i;
>>
>> @@ -176,7 +169,7 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
>> return ncf;
>> }
>>
>> -static inline int div_prepare(uint32_t a, uint32_t b)
>> +static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> if (b == 0) {
>> env->sregs[SR_MSR] |= MSR_DZ;
>> @@ -184,7 +177,7 @@ static inline int div_prepare(uint32_t a, uint32_t b)
>> if ((env->sregs[SR_MSR] & MSR_EE)
>> && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
>> env->sregs[SR_ESR] = ESR_EC_DIVZERO;
>> - helper_raise_exception(EXCP_HW_EXCP);
>> + helper_raise_exception(env, EXCP_HW_EXCP);
>> }
>> return 0;
>> }
>> @@ -192,28 +185,30 @@ static inline int div_prepare(uint32_t a, uint32_t b)
>> return 1;
>> }
>>
>> -uint32_t helper_divs(uint32_t a, uint32_t b)
>> +uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> - if (!div_prepare(a, b))
>> + if (!div_prepare(env, a, b)) {
>> return 0;
>> + }
>> return (int32_t)a / (int32_t)b;
>> }
>>
>> -uint32_t helper_divu(uint32_t a, uint32_t b)
>> +uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> - if (!div_prepare(a, b))
>> + if (!div_prepare(env, a, b)) {
>> return 0;
>> + }
>> return a / b;
>> }
>>
>> /* raise FPU exception. */
>> -static void raise_fpu_exception(void)
>> +static void raise_fpu_exception(CPUMBState *env)
>> {
>> env->sregs[SR_ESR] = ESR_EC_FPU;
>> - helper_raise_exception(EXCP_HW_EXCP);
>> + helper_raise_exception(env, EXCP_HW_EXCP);
>> }
>>
>> -static void update_fpu_flags(int flags)
>> +static void update_fpu_flags(CPUMBState *env, int flags)
>> {
>> int raise = 0;
>>
>> @@ -236,11 +231,11 @@ static void update_fpu_flags(int flags)
>> if (raise
>> && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
>> && (env->sregs[SR_MSR] & MSR_EE)) {
>> - raise_fpu_exception();
>> + raise_fpu_exception(env);
>> }
>> }
>>
>> -uint32_t helper_fadd(uint32_t a, uint32_t b)
>> +uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> CPU_FloatU fd, fa, fb;
>> int flags;
>> @@ -251,11 +246,11 @@ uint32_t helper_fadd(uint32_t a, uint32_t b)
>> fd.f = float32_add(fa.f, fb.f, &env->fp_status);
>>
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags);
>> + update_fpu_flags(env, flags);
>> return fd.l;
>> }
>>
>> -uint32_t helper_frsub(uint32_t a, uint32_t b)
>> +uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> CPU_FloatU fd, fa, fb;
>> int flags;
>> @@ -265,11 +260,11 @@ uint32_t helper_frsub(uint32_t a, uint32_t b)
>> fb.l = b;
>> fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags);
>> + update_fpu_flags(env, flags);
>> return fd.l;
>> }
>>
>> -uint32_t helper_fmul(uint32_t a, uint32_t b)
>> +uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> CPU_FloatU fd, fa, fb;
>> int flags;
>> @@ -279,12 +274,12 @@ uint32_t helper_fmul(uint32_t a, uint32_t b)
>> fb.l = b;
>> fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags);
>> + update_fpu_flags(env, flags);
>>
>> return fd.l;
>> }
>>
>> -uint32_t helper_fdiv(uint32_t a, uint32_t b)
>> +uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> CPU_FloatU fd, fa, fb;
>> int flags;
>> @@ -294,12 +289,12 @@ uint32_t helper_fdiv(uint32_t a, uint32_t b)
>> fb.l = b;
>> fd.f = float32_div(fb.f, fa.f, &env->fp_status);
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags);
>> + update_fpu_flags(env, flags);
>>
>> return fd.l;
>> }
>>
>> -uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
>> +uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> CPU_FloatU fa, fb;
>> uint32_t r = 0;
>> @@ -308,7 +303,7 @@ uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
>> fb.l = b;
>>
>> if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
>> - update_fpu_flags(float_flag_invalid);
>> + update_fpu_flags(env, float_flag_invalid);
>> r = 1;
>> }
>>
>> @@ -319,7 +314,7 @@ uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
>> return r;
>> }
>>
>> -uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
>> +uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> CPU_FloatU fa, fb;
>> int r;
>> @@ -330,12 +325,12 @@ uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
>> fb.l = b;
>> r = float32_lt(fb.f, fa.f, &env->fp_status);
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags & float_flag_invalid);
>> + update_fpu_flags(env, flags & float_flag_invalid);
>>
>> return r;
>> }
>>
>> -uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
>> +uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> CPU_FloatU fa, fb;
>> int flags;
>> @@ -346,12 +341,12 @@ uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
>> fb.l = b;
>> r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags & float_flag_invalid);
>> + update_fpu_flags(env, flags & float_flag_invalid);
>>
>> return r;
>> }
>>
>> -uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
>> +uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> CPU_FloatU fa, fb;
>> int flags;
>> @@ -362,13 +357,13 @@ uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
>> set_float_exception_flags(0, &env->fp_status);
>> r = float32_le(fa.f, fb.f, &env->fp_status);
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags & float_flag_invalid);
>> + update_fpu_flags(env, flags & float_flag_invalid);
>>
>>
>> return r;
>> }
>>
>> -uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
>> +uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> CPU_FloatU fa, fb;
>> int flags, r;
>> @@ -378,11 +373,11 @@ uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
>> set_float_exception_flags(0, &env->fp_status);
>> r = float32_lt(fa.f, fb.f, &env->fp_status);
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags & float_flag_invalid);
>> + update_fpu_flags(env, flags & float_flag_invalid);
>> return r;
>> }
>>
>> -uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
>> +uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> CPU_FloatU fa, fb;
>> int flags, r;
>> @@ -392,12 +387,12 @@ uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
>> set_float_exception_flags(0, &env->fp_status);
>> r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags & float_flag_invalid);
>> + update_fpu_flags(env, flags & float_flag_invalid);
>>
>> return r;
>> }
>>
>> -uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
>> +uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
>> {
>> CPU_FloatU fa, fb;
>> int flags, r;
>> @@ -407,12 +402,12 @@ uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
>> set_float_exception_flags(0, &env->fp_status);
>> r = !float32_lt(fa.f, fb.f, &env->fp_status);
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags & float_flag_invalid);
>> + update_fpu_flags(env, flags & float_flag_invalid);
>>
>> return r;
>> }
>>
>> -uint32_t helper_flt(uint32_t a)
>> +uint32_t helper_flt(CPUMBState *env, uint32_t a)
>> {
>> CPU_FloatU fd, fa;
>>
>> @@ -421,7 +416,7 @@ uint32_t helper_flt(uint32_t a)
>> return fd.l;
>> }
>>
>> -uint32_t helper_fint(uint32_t a)
>> +uint32_t helper_fint(CPUMBState *env, uint32_t a)
>> {
>> CPU_FloatU fa;
>> uint32_t r;
>> @@ -431,12 +426,12 @@ uint32_t helper_fint(uint32_t a)
>> fa.l = a;
>> r = float32_to_int32(fa.f, &env->fp_status);
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags);
>> + update_fpu_flags(env, flags);
>>
>> return r;
>> }
>>
>> -uint32_t helper_fsqrt(uint32_t a)
>> +uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
>> {
>> CPU_FloatU fd, fa;
>> int flags;
>> @@ -445,7 +440,7 @@ uint32_t helper_fsqrt(uint32_t a)
>> fa.l = a;
>> fd.l = float32_sqrt(fa.f, &env->fp_status);
>> flags = get_float_exception_flags(&env->fp_status);
>> - update_fpu_flags(flags);
>> + update_fpu_flags(env, flags);
>>
>> return fd.l;
>> }
>> @@ -463,7 +458,8 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
>> return 0;
>> }
>>
>> -void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
>> +void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
>> + uint32_t mask)
>> {
>> if (addr & mask) {
>> qemu_log_mask(CPU_LOG_INT,
>> @@ -478,45 +474,39 @@ void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
>> if (!(env->sregs[SR_MSR] & MSR_EE)) {
>> return;
>> }
>> - helper_raise_exception(EXCP_HW_EXCP);
>> + helper_raise_exception(env, EXCP_HW_EXCP);
>> }
>> }
>>
>> -void helper_stackprot(uint32_t addr)
>> +void helper_stackprot(CPUMBState *env, uint32_t addr)
>> {
>> if (addr < env->slr || addr > env->shr) {
>> qemu_log("Stack protector violation at %x %x %x\n",
>> addr, env->slr, env->shr);
>> env->sregs[SR_EAR] = addr;
>> env->sregs[SR_ESR] = ESR_EC_STACKPROT;
>> - helper_raise_exception(EXCP_HW_EXCP);
>> + helper_raise_exception(env, EXCP_HW_EXCP);
>> }
>> }
>>
>> #if !defined(CONFIG_USER_ONLY)
>> /* Writes/reads to the MMU's special regs end up here. */
>> -uint32_t helper_mmu_read(uint32_t rn)
>> +uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
>> {
>> return mmu_read(env, rn);
>> }
>>
>> -void helper_mmu_write(uint32_t rn, uint32_t v)
>> +void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
>> {
>> mmu_write(env, rn, v);
>> }
>>
>> -void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
>> +void cpu_unassigned_access(CPUMBState *env, target_phys_addr_t addr,
>> int is_write, int is_exec, int is_asi, int size)
>> {
>> - CPUMBState *saved_env;
>> -
>> - saved_env = env;
>> - env = env1;
>> -
>> qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
>> addr, is_write, is_exec);
>> if (!(env->sregs[SR_MSR] & MSR_EE)) {
>> - env = saved_env;
>> return;
>> }
>>
>> @@ -524,14 +514,13 @@ void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
>> if (is_exec) {
>> if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
>> env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
>> - helper_raise_exception(EXCP_HW_EXCP);
>> + helper_raise_exception(env, EXCP_HW_EXCP);
>> }
>> } else {
>> if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
>> env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
>> - helper_raise_exception(EXCP_HW_EXCP);
>> + helper_raise_exception(env, EXCP_HW_EXCP);
>> }
>> }
>> - env = saved_env;
>> }
>> #endif
>> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
>> index 7470149..7c25530 100644
>> --- a/target-microblaze/translate.c
>> +++ b/target-microblaze/translate.c
>> @@ -126,7 +126,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
>>
>> t_sync_flags(dc);
>> tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
>> - gen_helper_raise_exception(tmp);
>> + gen_helper_raise_exception(cpu_env, tmp);
>> tcg_temp_free_i32(tmp);
>> dc->is_jmp = DISAS_UPDATE;
>> }
>> @@ -503,9 +503,9 @@ static void dec_msr(DisasContext *dc)
>> sr &= 7;
>> LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
>> if (to)
>> - gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
>> + gen_helper_mmu_write(cpu_env, tcg_const_tl(sr), cpu_R[dc->ra]);
>> else
>> - gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
>> + gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_tl(sr));
>> return;
>> }
>> #endif
>> @@ -704,9 +704,11 @@ static void dec_div(DisasContext *dc)
>> }
>>
>> if (u)
>> - gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
>> + gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
>> + cpu_R[dc->ra]);
>> else
>> - gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
>> + gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
>> + cpu_R[dc->ra]);
>> if (!dc->rd)
>> tcg_gen_movi_tl(cpu_R[dc->rd], 0);
>> }
>> @@ -912,7 +914,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
>> tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
>>
>> if (stackprot) {
>> - gen_helper_stackprot(*t);
>> + gen_helper_stackprot(cpu_env, *t);
>> }
>> return t;
>> }
>> @@ -930,7 +932,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
>> }
>>
>> if (stackprot) {
>> - gen_helper_stackprot(*t);
>> + gen_helper_stackprot(cpu_env, *t);
>> }
>> return t;
>> }
>> @@ -1056,7 +1058,7 @@ static void dec_load(DisasContext *dc)
>> gen_load(dc, v, *addr, size);
>>
>> tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
>> - gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
>> + gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
>> tcg_const_tl(0), tcg_const_tl(size - 1));
>> if (dc->rd) {
>> if (rev) {
>> @@ -1218,7 +1220,7 @@ static void dec_store(DisasContext *dc)
>> * the alignment checks in between the probe and the mem
>> * access.
>> */
>> - gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
>> + gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
>> tcg_const_tl(1), tcg_const_tl(size - 1));
>> }
>>
>> @@ -1493,49 +1495,53 @@ static void dec_fpu(DisasContext *dc)
>>
>> switch (fpu_insn) {
>> case 0:
>> - gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
>> + gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
>> + cpu_R[dc->rb]);
>> break;
>>
>> case 1:
>> - gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
>> + gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
>> + cpu_R[dc->rb]);
>> break;
>>
>> case 2:
>> - gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
>> + gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
>> + cpu_R[dc->rb]);
>> break;
>>
>> case 3:
>> - gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
>> + gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
>> + cpu_R[dc->rb]);
>> break;
>>
>> case 4:
>> switch ((dc->ir >> 4) & 7) {
>> case 0:
>> - gen_helper_fcmp_un(cpu_R[dc->rd],
>> + gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env,
>> cpu_R[dc->ra], cpu_R[dc->rb]);
>> break;
>> case 1:
>> - gen_helper_fcmp_lt(cpu_R[dc->rd],
>> + gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env,
>> cpu_R[dc->ra], cpu_R[dc->rb]);
>> break;
>> case 2:
>> - gen_helper_fcmp_eq(cpu_R[dc->rd],
>> + gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env,
>> cpu_R[dc->ra], cpu_R[dc->rb]);
>> break;
>> case 3:
>> - gen_helper_fcmp_le(cpu_R[dc->rd],
>> + gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env,
>> cpu_R[dc->ra], cpu_R[dc->rb]);
>> break;
>> case 4:
>> - gen_helper_fcmp_gt(cpu_R[dc->rd],
>> + gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env,
>> cpu_R[dc->ra], cpu_R[dc->rb]);
>> break;
>> case 5:
>> - gen_helper_fcmp_ne(cpu_R[dc->rd],
>> + gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env,
>> cpu_R[dc->ra], cpu_R[dc->rb]);
>> break;
>> case 6:
>> - gen_helper_fcmp_ge(cpu_R[dc->rd],
>> + gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env,
>> cpu_R[dc->ra], cpu_R[dc->rb]);
>> break;
>> default:
>> @@ -1552,21 +1558,21 @@ static void dec_fpu(DisasContext *dc)
>> if (!dec_check_fpuv2(dc)) {
>> return;
>> }
>> - gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]);
>> + gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
>> break;
>>
>> case 6:
>> if (!dec_check_fpuv2(dc)) {
>> return;
>> }
>> - gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]);
>> + gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
>> break;
>>
>> case 7:
>> if (!dec_check_fpuv2(dc)) {
>> return;
>> }
>> - gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]);
>> + gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
>> break;
>>
>> default:
>> @@ -1662,7 +1668,7 @@ static inline void decode(DisasContext *dc)
>> if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
>> tcg_gen_debug_insn_start(dc->pc);
>>
>> - dc->ir = ir = ldl_code(dc->pc);
>> + dc->ir = ir = cpu_ldl_code(cpu_single_env, dc->pc);
>> LOG_DIS("%8.8x\t", dc->ir);
>
> Similarly to the sh4 patch, it should be quite easy to just pass env to
> decode() and use it there instead of cpu_single_env.
OK, but I'd rather pass the instruction instead of CPUState since it's
not needed elsewhere.
>
>> if (dc->ir)
>> @@ -1871,7 +1877,7 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
>> if (dc->is_jmp != DISAS_JUMP) {
>> tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
>> }
>> - gen_helper_raise_exception(tmp);
>> + gen_helper_raise_exception(cpu_env, tmp);
>> tcg_temp_free_i32(tmp);
>> } else {
>> switch(dc->is_jmp) {
>> --
>> 1.7.2.5
>>
>>
>>
>
> --
> Aurelien Jarno GPG: 1024D/F1BCDB73
> aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread
* [Qemu-devel] [PATCH 18/21] target-cris: switch to AREG0 free mode
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (16 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 17/21] target-microblaze: " Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-07 14:18 ` Aurelien Jarno
2012-09-02 17:33 ` [Qemu-devel] [PATCH 19/21] target-sh4: " Blue Swirl
` (3 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Edgar E. Iglesias
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
configure | 2 +-
target-cris/Makefile.objs | 2 -
target-cris/helper.c | 4 +-
target-cris/helper.h | 34 ++++++++--------
target-cris/op_helper.c | 89 +++++++++++++++++++++----------------------
target-cris/translate.c | 50 ++++++++++++-----------
target-cris/translate_v10.c | 22 +++++-----
7 files changed, 101 insertions(+), 102 deletions(-)
diff --git a/configure b/configure
index e464d2f..d760e07 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
case "$target_arch2" in
- alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
+ alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
;;
esac
diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
index 4b09e8c..afb87bc 100644
--- a/target-cris/Makefile.objs
+++ b/target-cris/Makefile.objs
@@ -1,4 +1,2 @@
obj-y += translate.o op_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-cris/helper.c b/target-cris/helper.c
index bfbc29e..1bdb7e2 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -151,7 +151,7 @@ static void do_interruptv10(CPUCRISState *env)
}
/* Now that we are in kernel mode, load the handlers address. */
- env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
+ env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
env->locked_irq = 1;
env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
@@ -233,7 +233,7 @@ void do_interrupt(CPUCRISState *env)
/* Now that we are in kernel mode, load the handlers address.
This load may not fault, real hw leaves that behaviour as
undefined. */
- env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
+ env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
/* Clear the excption_index to avoid spurios hw_aborts for recursive
bus faults. */
diff --git a/target-cris/helper.h b/target-cris/helper.h
index 093063a..b575524 100644
--- a/target-cris/helper.h
+++ b/target-cris/helper.h
@@ -1,26 +1,26 @@
#include "def-helper.h"
-DEF_HELPER_1(raise_exception, void, i32)
-DEF_HELPER_1(tlb_flush_pid, void, i32)
-DEF_HELPER_1(spc_write, void, i32)
+DEF_HELPER_2(raise_exception, void, env, i32)
+DEF_HELPER_2(tlb_flush_pid, void, env, i32)
+DEF_HELPER_2(spc_write, void, env, i32)
DEF_HELPER_3(dump, void, i32, i32, i32)
-DEF_HELPER_0(rfe, void);
-DEF_HELPER_0(rfn, void);
+DEF_HELPER_1(rfe, void, env);
+DEF_HELPER_1(rfn, void, env);
-DEF_HELPER_2(movl_sreg_reg, void, i32, i32)
-DEF_HELPER_2(movl_reg_sreg, void, i32, i32)
+DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32)
+DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32)
DEF_HELPER_FLAGS_1(lz, TCG_CALL_PURE, i32, i32);
-DEF_HELPER_FLAGS_3(btst, TCG_CALL_PURE, i32, i32, i32, i32);
+DEF_HELPER_FLAGS_4(btst, TCG_CALL_PURE, i32, env, i32, i32, i32);
-DEF_HELPER_FLAGS_3(evaluate_flags_muls, TCG_CALL_PURE, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_3(evaluate_flags_mulu, TCG_CALL_PURE, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_4(evaluate_flags_mcp, TCG_CALL_PURE, i32, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_4(evaluate_flags_alu_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_4(evaluate_flags_sub_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_2(evaluate_flags_move_4, TCG_CALL_PURE, i32, i32, i32)
-DEF_HELPER_FLAGS_2(evaluate_flags_move_2, TCG_CALL_PURE, i32, i32, i32)
-DEF_HELPER_0(evaluate_flags, void)
-DEF_HELPER_0(top_evaluate_flags, void)
+DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_PURE, i32, env, i32, i32, i32)
+DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_PURE, i32, env, i32, i32, i32)
+DEF_HELPER_FLAGS_5(evaluate_flags_mcp, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
+DEF_HELPER_FLAGS_5(evaluate_flags_alu_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
+DEF_HELPER_FLAGS_5(evaluate_flags_sub_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
+DEF_HELPER_FLAGS_3(evaluate_flags_move_4, TCG_CALL_PURE, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(evaluate_flags_move_2, TCG_CALL_PURE, i32, env, i32, i32)
+DEF_HELPER_1(evaluate_flags, void, env)
+DEF_HELPER_1(top_evaluate_flags, void, env)
#include "def-helper.h"
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index ac7c98c..5cce3e7 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -19,7 +19,6 @@
*/
#include "cpu.h"
-#include "dyngen-exec.h"
#include "mmu.h"
#include "helper.h"
#include "host-utils.h"
@@ -55,17 +54,12 @@
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
TranslationBlock *tb;
- CPUCRISState *saved_env;
int ret;
- saved_env = env;
- env = env1;
-
D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
env->pc, env->debug1, (void *)retaddr);
ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
@@ -79,23 +73,22 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
cpu_restore_state(tb, env, retaddr);
/* Evaluate flags after retranslation. */
- helper_top_evaluate_flags();
+ helper_top_evaluate_flags(env);
}
}
cpu_loop_exit(env);
}
- env = saved_env;
}
#endif
-void helper_raise_exception(uint32_t index)
+void helper_raise_exception(CPUCRISState *env, uint32_t index)
{
env->exception_index = index;
cpu_loop_exit(env);
}
-void helper_tlb_flush_pid(uint32_t pid)
+void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
{
#if !defined(CONFIG_USER_ONLY)
pid &= 0xff;
@@ -104,7 +97,7 @@ void helper_tlb_flush_pid(uint32_t pid)
#endif
}
-void helper_spc_write(uint32_t new_spc)
+void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
tlb_flush_page(env, env->pregs[PR_SPC]);
@@ -121,7 +114,7 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
#define EXTRACT_FIELD(src, start, end) \
(((src) >> start) & ((1 << (end - start + 1)) - 1))
-void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
+void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
{
uint32_t srs;
srs = env->pregs[PR_SRS];
@@ -171,7 +164,7 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
#endif
}
-void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
+void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
{
uint32_t srs;
env->pregs[PR_SRS] &= 3;
@@ -216,7 +209,7 @@ static void cris_ccs_rshift(CPUCRISState *env)
env->pregs[PR_CCS] = ccs;
}
-void helper_rfe(void)
+void helper_rfe(CPUCRISState *env)
{
int rflag = env->pregs[PR_CCS] & R_FLAG;
@@ -232,7 +225,7 @@ void helper_rfe(void)
env->pregs[PR_CCS] |= P_FLAG;
}
-void helper_rfn(void)
+void helper_rfn(CPUCRISState *env)
{
int rflag = env->pregs[PR_CCS] & R_FLAG;
@@ -256,7 +249,7 @@ uint32_t helper_lz(uint32_t t0)
return clz32(t0);
}
-uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
+uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
{
/* FIXME: clean this up. */
@@ -284,7 +277,8 @@ uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
return ccs;
}
-static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
+static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
+ uint32_t flags, uint32_t ccs)
{
unsigned int x, z, mask;
@@ -303,7 +297,8 @@ static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
return ccs;
}
-uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
+uint32_t helper_evaluate_flags_muls(CPUCRISState *env, uint32_t ccs,
+ uint32_t res, uint32_t mof)
{
uint32_t flags = 0;
int64_t tmp;
@@ -321,10 +316,11 @@ uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
if ((dneg && mof != -1)
|| (!dneg && mof != 0))
flags |= V_FLAG;
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
+uint32_t helper_evaluate_flags_mulu(CPUCRISState *env, uint32_t ccs,
+ uint32_t res, uint32_t mof)
{
uint32_t flags = 0;
uint64_t tmp;
@@ -339,10 +335,10 @@ uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
if (mof)
flags |= V_FLAG;
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
+uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
uint32_t flags = 0;
@@ -368,10 +364,10 @@ uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
flags |= R_FLAG;
}
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
+uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
uint32_t flags = 0;
@@ -397,10 +393,10 @@ uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
flags |= C_FLAG;
}
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
+uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
uint32_t flags = 0;
@@ -427,10 +423,11 @@ uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
}
flags ^= C_FLAG;
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
+uint32_t helper_evaluate_flags_move_4(CPUCRISState *env, uint32_t ccs,
+ uint32_t res)
{
uint32_t flags = 0;
@@ -439,9 +436,10 @@ uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
else if (res == 0L)
flags |= Z_FLAG;
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
+uint32_t helper_evaluate_flags_move_2(CPUCRISState *env, uint32_t ccs,
+ uint32_t res)
{
uint32_t flags = 0;
@@ -450,12 +448,12 @@ uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
else if (res == 0)
flags |= Z_FLAG;
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
/* TODO: This is expensive. We could split things up and only evaluate part of
CCR on a need to know basis. For now, we simply re-evaluate everything. */
-void helper_evaluate_flags(void)
+void helper_evaluate_flags(CPUCRISState *env)
{
uint32_t src, dst, res;
uint32_t flags = 0;
@@ -571,25 +569,26 @@ void helper_evaluate_flags(void)
if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
flags ^= C_FLAG;
- env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
+ env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
+ env->pregs[PR_CCS]);
}
-void helper_top_evaluate_flags(void)
+void helper_top_evaluate_flags(CPUCRISState *env)
{
switch (env->cc_op)
{
case CC_OP_MCP:
- env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
+ env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
env->pregs[PR_CCS], env->cc_src,
env->cc_dest, env->cc_result);
break;
case CC_OP_MULS:
- env->pregs[PR_CCS] = helper_evaluate_flags_muls(
+ env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
env->pregs[PR_CCS], env->cc_result,
env->pregs[PR_MOF]);
break;
case CC_OP_MULU:
- env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
+ env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
env->pregs[PR_CCS], env->cc_result,
env->pregs[PR_MOF]);
break;
@@ -604,18 +603,18 @@ void helper_top_evaluate_flags(void)
{
case 4:
env->pregs[PR_CCS] =
- helper_evaluate_flags_move_4(
+ helper_evaluate_flags_move_4(env,
env->pregs[PR_CCS],
env->cc_result);
break;
case 2:
env->pregs[PR_CCS] =
- helper_evaluate_flags_move_2(
+ helper_evaluate_flags_move_2(env,
env->pregs[PR_CCS],
env->cc_result);
break;
default:
- helper_evaluate_flags();
+ helper_evaluate_flags(env);
break;
}
break;
@@ -626,12 +625,12 @@ void helper_top_evaluate_flags(void)
case CC_OP_CMP:
if (env->cc_size == 4)
env->pregs[PR_CCS] =
- helper_evaluate_flags_sub_4(
+ helper_evaluate_flags_sub_4(env,
env->pregs[PR_CCS],
env->cc_src, env->cc_dest,
env->cc_result);
else
- helper_evaluate_flags();
+ helper_evaluate_flags(env);
break;
default:
{
@@ -639,13 +638,13 @@ void helper_top_evaluate_flags(void)
{
case 4:
env->pregs[PR_CCS] =
- helper_evaluate_flags_alu_4(
+ helper_evaluate_flags_alu_4(env,
env->pregs[PR_CCS],
env->cc_src, env->cc_dest,
env->cc_result);
break;
default:
- helper_evaluate_flags();
+ helper_evaluate_flags(env);
break;
}
}
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 1ad9ec7..5e4f7f5 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -211,9 +211,9 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
tcg_gen_andi_tl(cpu_PR[r], tn, 3);
else {
if (r == PR_PID)
- gen_helper_tlb_flush_pid(tn);
+ gen_helper_tlb_flush_pid(cpu_env, tn);
if (dc->tb_flags & S_FLAG && r == PR_SPC)
- gen_helper_spc_write(tn);
+ gen_helper_spc_write(cpu_env, tn);
else if (r == PR_CCS)
dc->cpustate_changed = 1;
tcg_gen_mov_tl(cpu_PR[r], tn);
@@ -241,24 +241,24 @@ static int cris_fetch(DisasContext *dc, uint32_t addr,
switch (size) {
case 4:
{
- r = ldl_code(addr);
+ r = cpu_ldl_code(cpu_single_env, addr);
break;
}
case 2:
{
if (sign) {
- r = ldsw_code(addr);
+ r = cpu_ldsw_code(cpu_single_env, addr);
} else {
- r = lduw_code(addr);
+ r = cpu_lduw_code(cpu_single_env, addr);
}
break;
}
case 1:
{
if (sign) {
- r = ldsb_code(addr);
+ r = cpu_ldsb_code(cpu_single_env, addr);
} else {
- r = ldub_code(addr);
+ r = cpu_ldub_code(cpu_single_env, addr);
}
break;
}
@@ -278,7 +278,7 @@ static void cris_lock_irq(DisasContext *dc)
static inline void t_gen_raise_exception(uint32_t index)
{
TCGv_i32 tmp = tcg_const_i32(index);
- gen_helper_raise_exception(tmp);
+ gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
}
@@ -624,17 +624,17 @@ static void cris_evaluate_flags(DisasContext *dc)
switch (dc->cc_op)
{
case CC_OP_MCP:
- gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_src,
cc_dest, cc_result);
break;
case CC_OP_MULS:
- gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_result,
cpu_PR[PR_MOF]);
break;
case CC_OP_MULU:
- gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_result,
cpu_PR[PR_MOF]);
break;
@@ -648,15 +648,15 @@ static void cris_evaluate_flags(DisasContext *dc)
switch (dc->cc_size)
{
case 4:
- gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_result);
break;
case 2:
- gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_result);
break;
default:
- gen_helper_evaluate_flags();
+ gen_helper_evaluate_flags(cpu_env);
break;
}
break;
@@ -666,21 +666,21 @@ static void cris_evaluate_flags(DisasContext *dc)
case CC_OP_SUB:
case CC_OP_CMP:
if (dc->cc_size == 4)
- gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
else
- gen_helper_evaluate_flags();
+ gen_helper_evaluate_flags(cpu_env);
break;
default:
switch (dc->cc_size)
{
case 4:
- gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
break;
default:
- gen_helper_evaluate_flags();
+ gen_helper_evaluate_flags(cpu_env);
break;
}
break;
@@ -1475,7 +1475,7 @@ static int dec_btstq(DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZ);
cris_evaluate_flags(dc);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
cris_alu(dc, CC_OP_MOVE,
cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
@@ -1925,7 +1925,7 @@ static int dec_btst_r(DisasContext *dc)
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_evaluate_flags(dc);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
cpu_R[dc->op1], cpu_PR[PR_CCS]);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
cpu_R[dc->op2], cpu_R[dc->op2], 4);
@@ -2135,14 +2135,16 @@ static int dec_move_rs(DisasContext *dc)
{
LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
- gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
+ gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
+ tcg_const_tl(dc->op1));
return 2;
}
static int dec_move_sr(DisasContext *dc)
{
LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
cris_cc_mask(dc, 0);
- gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
+ gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
+ tcg_const_tl(dc->op2));
return 2;
}
@@ -2906,14 +2908,14 @@ static int dec_rfe_etc(DisasContext *dc)
/* rfe. */
LOG_DIS("rfe\n");
cris_evaluate_flags(dc);
- gen_helper_rfe();
+ gen_helper_rfe(cpu_env);
dc->is_jmp = DISAS_UPDATE;
break;
case 5:
/* rfn. */
LOG_DIS("rfn\n");
cris_evaluate_flags(dc);
- gen_helper_rfn();
+ gen_helper_rfn(cpu_env);
dc->is_jmp = DISAS_UPDATE;
break;
case 6:
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 3629629..d9d6aa5 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -182,17 +182,17 @@ static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize,
if (memsize != 4) {
if (s_ext) {
if (memsize == 1)
- imm = ldsb_code(dc->pc + 2);
+ imm = cpu_ldsb_code(cpu_single_env, dc->pc + 2);
else
- imm = ldsw_code(dc->pc + 2);
+ imm = cpu_ldsw_code(cpu_single_env, dc->pc + 2);
} else {
if (memsize == 1)
- imm = ldub_code(dc->pc + 2);
+ imm = cpu_ldub_code(cpu_single_env, dc->pc + 2);
else
- imm = lduw_code(dc->pc + 2);
+ imm = cpu_lduw_code(cpu_single_env, dc->pc + 2);
}
} else
- imm = ldl_code(dc->pc + 2);
+ imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
tcg_gen_movi_tl(dst, imm);
@@ -289,7 +289,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
} else {
/* BTST */
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
tcg_const_tl(imm), cpu_PR[PR_CCS]);
}
break;
@@ -723,7 +723,7 @@ static unsigned int dec10_reg(DisasContext *dc)
LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
cpu_R[dc->src], cpu_PR[PR_CCS]);
break;
case CRISV10_REG_DSTEP:
@@ -974,7 +974,7 @@ static int dec10_dip(DisasContext *dc)
LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
dc->pc, dc->opcode, dc->src, dc->dst);
if (dc->src == 15) {
- imm = ldl_code(dc->pc + 2);
+ imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
if (dc->postinc)
insn_len += 4;
@@ -1119,7 +1119,7 @@ static unsigned int dec10_ind(DisasContext *dc)
if (dc->src == 15) {
LOG_DIS("jump.%d %d r%d r%d direct\n", size,
dc->opcode, dc->src, dc->dst);
- imm = ldl_code(dc->pc + 2);
+ imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
if (dc->mode == CRISV10_MODE_AUTOINC)
insn_len += size;
@@ -1185,7 +1185,7 @@ static unsigned int dec10_ind(DisasContext *dc)
case CRISV10_IND_BCC_M:
cris_cc_mask(dc, 0);
- imm = ldsw_code(dc->pc + 2);
+ imm = cpu_ldsw_code(cpu_single_env, dc->pc + 2);
simm = (int16_t)imm;
simm += 4;
@@ -1210,7 +1210,7 @@ static unsigned int crisv10_decoder(DisasContext *dc)
tcg_gen_debug_insn_start(dc->pc);
/* Load a halfword onto the instruction register. */
- dc->ir = lduw_code(dc->pc);
+ dc->ir = cpu_lduw_code(cpu_single_env, dc->pc);
/* Now decode it. */
dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 18/21] target-cris: switch to AREG0 free mode
2012-09-02 17:33 ` [Qemu-devel] [PATCH 18/21] target-cris: " Blue Swirl
@ 2012-09-07 14:18 ` Aurelien Jarno
2012-09-07 14:40 ` Edgar E. Iglesias
2012-09-08 8:35 ` Blue Swirl
0 siblings, 2 replies; 64+ messages in thread
From: Aurelien Jarno @ 2012-09-07 14:18 UTC (permalink / raw)
To: Blue Swirl; +Cc: Edgar E. Iglesias, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 25649 bytes --]
On Sun, Sep 02, 2012 at 05:33:47PM +0000, Blue Swirl wrote:
> Add an explicit CPUState parameter instead of relying on AREG0
> and switch to AREG0 free mode.
>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> ---
> configure | 2 +-
> target-cris/Makefile.objs | 2 -
> target-cris/helper.c | 4 +-
> target-cris/helper.h | 34 ++++++++--------
> target-cris/op_helper.c | 89 +++++++++++++++++++++----------------------
> target-cris/translate.c | 50 ++++++++++++-----------
> target-cris/translate_v10.c | 22 +++++-----
> 7 files changed, 101 insertions(+), 102 deletions(-)
>
> diff --git a/configure b/configure
> index e464d2f..d760e07 100755
> --- a/configure
> +++ b/configure
> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
>
>
> case "$target_arch2" in
> - alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> + alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
> ;;
> esac
> diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
> index 4b09e8c..afb87bc 100644
> --- a/target-cris/Makefile.objs
> +++ b/target-cris/Makefile.objs
> @@ -1,4 +1,2 @@
> obj-y += translate.o op_helper.o helper.o cpu.o
> obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
> -
> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> diff --git a/target-cris/helper.c b/target-cris/helper.c
> index bfbc29e..1bdb7e2 100644
> --- a/target-cris/helper.c
> +++ b/target-cris/helper.c
> @@ -151,7 +151,7 @@ static void do_interruptv10(CPUCRISState *env)
> }
>
> /* Now that we are in kernel mode, load the handlers address. */
> - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
> + env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
> env->locked_irq = 1;
> env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
>
> @@ -233,7 +233,7 @@ void do_interrupt(CPUCRISState *env)
> /* Now that we are in kernel mode, load the handlers address.
> This load may not fault, real hw leaves that behaviour as
> undefined. */
> - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
> + env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
>
> /* Clear the excption_index to avoid spurios hw_aborts for recursive
> bus faults. */
> diff --git a/target-cris/helper.h b/target-cris/helper.h
> index 093063a..b575524 100644
> --- a/target-cris/helper.h
> +++ b/target-cris/helper.h
> @@ -1,26 +1,26 @@
> #include "def-helper.h"
>
> -DEF_HELPER_1(raise_exception, void, i32)
> -DEF_HELPER_1(tlb_flush_pid, void, i32)
> -DEF_HELPER_1(spc_write, void, i32)
> +DEF_HELPER_2(raise_exception, void, env, i32)
> +DEF_HELPER_2(tlb_flush_pid, void, env, i32)
> +DEF_HELPER_2(spc_write, void, env, i32)
> DEF_HELPER_3(dump, void, i32, i32, i32)
> -DEF_HELPER_0(rfe, void);
> -DEF_HELPER_0(rfn, void);
> +DEF_HELPER_1(rfe, void, env);
> +DEF_HELPER_1(rfn, void, env);
>
> -DEF_HELPER_2(movl_sreg_reg, void, i32, i32)
> -DEF_HELPER_2(movl_reg_sreg, void, i32, i32)
> +DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32)
> +DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32)
>
> DEF_HELPER_FLAGS_1(lz, TCG_CALL_PURE, i32, i32);
> -DEF_HELPER_FLAGS_3(btst, TCG_CALL_PURE, i32, i32, i32, i32);
> +DEF_HELPER_FLAGS_4(btst, TCG_CALL_PURE, i32, env, i32, i32, i32);
>
> -DEF_HELPER_FLAGS_3(evaluate_flags_muls, TCG_CALL_PURE, i32, i32, i32, i32)
> -DEF_HELPER_FLAGS_3(evaluate_flags_mulu, TCG_CALL_PURE, i32, i32, i32, i32)
> -DEF_HELPER_FLAGS_4(evaluate_flags_mcp, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> -DEF_HELPER_FLAGS_4(evaluate_flags_alu_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> -DEF_HELPER_FLAGS_4(evaluate_flags_sub_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> -DEF_HELPER_FLAGS_2(evaluate_flags_move_4, TCG_CALL_PURE, i32, i32, i32)
> -DEF_HELPER_FLAGS_2(evaluate_flags_move_2, TCG_CALL_PURE, i32, i32, i32)
> -DEF_HELPER_0(evaluate_flags, void)
> -DEF_HELPER_0(top_evaluate_flags, void)
> +DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_PURE, i32, env, i32, i32, i32)
> +DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_PURE, i32, env, i32, i32, i32)
> +DEF_HELPER_FLAGS_5(evaluate_flags_mcp, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> +DEF_HELPER_FLAGS_5(evaluate_flags_alu_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> +DEF_HELPER_FLAGS_5(evaluate_flags_sub_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> +DEF_HELPER_FLAGS_3(evaluate_flags_move_4, TCG_CALL_PURE, i32, env, i32, i32)
> +DEF_HELPER_FLAGS_3(evaluate_flags_move_2, TCG_CALL_PURE, i32, env, i32, i32)
> +DEF_HELPER_1(evaluate_flags, void, env)
> +DEF_HELPER_1(top_evaluate_flags, void, env)
>
> #include "def-helper.h"
> diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> index ac7c98c..5cce3e7 100644
> --- a/target-cris/op_helper.c
> +++ b/target-cris/op_helper.c
> @@ -19,7 +19,6 @@
> */
>
> #include "cpu.h"
> -#include "dyngen-exec.h"
> #include "mmu.h"
> #include "helper.h"
> #include "host-utils.h"
> @@ -55,17 +54,12 @@
> /* Try to fill the TLB and return an exception if error. If retaddr is
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> -/* XXX: fix it to restore all registers */
> -void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> TranslationBlock *tb;
> - CPUCRISState *saved_env;
> int ret;
>
> - saved_env = env;
> - env = env1;
> -
> D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
> env->pc, env->debug1, (void *)retaddr);
> ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
> @@ -79,23 +73,22 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
> cpu_restore_state(tb, env, retaddr);
>
> /* Evaluate flags after retranslation. */
> - helper_top_evaluate_flags();
> + helper_top_evaluate_flags(env);
> }
> }
> cpu_loop_exit(env);
> }
> - env = saved_env;
> }
>
> #endif
>
> -void helper_raise_exception(uint32_t index)
> +void helper_raise_exception(CPUCRISState *env, uint32_t index)
> {
> env->exception_index = index;
> cpu_loop_exit(env);
> }
>
> -void helper_tlb_flush_pid(uint32_t pid)
> +void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
> {
> #if !defined(CONFIG_USER_ONLY)
> pid &= 0xff;
> @@ -104,7 +97,7 @@ void helper_tlb_flush_pid(uint32_t pid)
> #endif
> }
>
> -void helper_spc_write(uint32_t new_spc)
> +void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
> {
> #if !defined(CONFIG_USER_ONLY)
> tlb_flush_page(env, env->pregs[PR_SPC]);
> @@ -121,7 +114,7 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
> #define EXTRACT_FIELD(src, start, end) \
> (((src) >> start) & ((1 << (end - start + 1)) - 1))
>
> -void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
> +void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
> {
> uint32_t srs;
> srs = env->pregs[PR_SRS];
> @@ -171,7 +164,7 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
> #endif
> }
>
> -void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
> +void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
> {
> uint32_t srs;
> env->pregs[PR_SRS] &= 3;
> @@ -216,7 +209,7 @@ static void cris_ccs_rshift(CPUCRISState *env)
> env->pregs[PR_CCS] = ccs;
> }
>
> -void helper_rfe(void)
> +void helper_rfe(CPUCRISState *env)
> {
> int rflag = env->pregs[PR_CCS] & R_FLAG;
>
> @@ -232,7 +225,7 @@ void helper_rfe(void)
> env->pregs[PR_CCS] |= P_FLAG;
> }
>
> -void helper_rfn(void)
> +void helper_rfn(CPUCRISState *env)
> {
> int rflag = env->pregs[PR_CCS] & R_FLAG;
>
> @@ -256,7 +249,7 @@ uint32_t helper_lz(uint32_t t0)
> return clz32(t0);
> }
>
> -uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
> +uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
> {
> /* FIXME: clean this up. */
>
> @@ -284,7 +277,8 @@ uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
> return ccs;
> }
>
> -static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
> +static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
> + uint32_t flags, uint32_t ccs)
> {
> unsigned int x, z, mask;
>
> @@ -303,7 +297,8 @@ static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
> return ccs;
> }
>
> -uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
> +uint32_t helper_evaluate_flags_muls(CPUCRISState *env, uint32_t ccs,
> + uint32_t res, uint32_t mof)
> {
> uint32_t flags = 0;
> int64_t tmp;
> @@ -321,10 +316,11 @@ uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
> if ((dneg && mof != -1)
> || (!dneg && mof != 0))
> flags |= V_FLAG;
> - return evaluate_flags_writeback(flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> -uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
> +uint32_t helper_evaluate_flags_mulu(CPUCRISState *env, uint32_t ccs,
> + uint32_t res, uint32_t mof)
> {
> uint32_t flags = 0;
> uint64_t tmp;
> @@ -339,10 +335,10 @@ uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
> if (mof)
> flags |= V_FLAG;
>
> - return evaluate_flags_writeback(flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> -uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
> +uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
> uint32_t src, uint32_t dst, uint32_t res)
> {
> uint32_t flags = 0;
> @@ -368,10 +364,10 @@ uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
> flags |= R_FLAG;
> }
>
> - return evaluate_flags_writeback(flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> -uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
> +uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
> uint32_t src, uint32_t dst, uint32_t res)
> {
> uint32_t flags = 0;
> @@ -397,10 +393,10 @@ uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
> flags |= C_FLAG;
> }
>
> - return evaluate_flags_writeback(flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> -uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
> +uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
> uint32_t src, uint32_t dst, uint32_t res)
> {
> uint32_t flags = 0;
> @@ -427,10 +423,11 @@ uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
> }
>
> flags ^= C_FLAG;
> - return evaluate_flags_writeback(flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> -uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
> +uint32_t helper_evaluate_flags_move_4(CPUCRISState *env, uint32_t ccs,
> + uint32_t res)
> {
> uint32_t flags = 0;
>
> @@ -439,9 +436,10 @@ uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
> else if (res == 0L)
> flags |= Z_FLAG;
>
> - return evaluate_flags_writeback(flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
> -uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
> +uint32_t helper_evaluate_flags_move_2(CPUCRISState *env, uint32_t ccs,
> + uint32_t res)
> {
> uint32_t flags = 0;
>
> @@ -450,12 +448,12 @@ uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
> else if (res == 0)
> flags |= Z_FLAG;
>
> - return evaluate_flags_writeback(flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> /* TODO: This is expensive. We could split things up and only evaluate part of
> CCR on a need to know basis. For now, we simply re-evaluate everything. */
> -void helper_evaluate_flags(void)
> +void helper_evaluate_flags(CPUCRISState *env)
> {
> uint32_t src, dst, res;
> uint32_t flags = 0;
> @@ -571,25 +569,26 @@ void helper_evaluate_flags(void)
> if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
> flags ^= C_FLAG;
>
> - env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
> + env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
> + env->pregs[PR_CCS]);
> }
>
> -void helper_top_evaluate_flags(void)
> +void helper_top_evaluate_flags(CPUCRISState *env)
> {
> switch (env->cc_op)
> {
> case CC_OP_MCP:
> - env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
> + env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
> env->pregs[PR_CCS], env->cc_src,
> env->cc_dest, env->cc_result);
> break;
> case CC_OP_MULS:
> - env->pregs[PR_CCS] = helper_evaluate_flags_muls(
> + env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
> env->pregs[PR_CCS], env->cc_result,
> env->pregs[PR_MOF]);
> break;
> case CC_OP_MULU:
> - env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
> + env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
> env->pregs[PR_CCS], env->cc_result,
> env->pregs[PR_MOF]);
> break;
> @@ -604,18 +603,18 @@ void helper_top_evaluate_flags(void)
> {
> case 4:
> env->pregs[PR_CCS] =
> - helper_evaluate_flags_move_4(
> + helper_evaluate_flags_move_4(env,
> env->pregs[PR_CCS],
> env->cc_result);
> break;
> case 2:
> env->pregs[PR_CCS] =
> - helper_evaluate_flags_move_2(
> + helper_evaluate_flags_move_2(env,
> env->pregs[PR_CCS],
> env->cc_result);
> break;
> default:
> - helper_evaluate_flags();
> + helper_evaluate_flags(env);
> break;
> }
> break;
> @@ -626,12 +625,12 @@ void helper_top_evaluate_flags(void)
> case CC_OP_CMP:
> if (env->cc_size == 4)
> env->pregs[PR_CCS] =
> - helper_evaluate_flags_sub_4(
> + helper_evaluate_flags_sub_4(env,
> env->pregs[PR_CCS],
> env->cc_src, env->cc_dest,
> env->cc_result);
> else
> - helper_evaluate_flags();
> + helper_evaluate_flags(env);
> break;
> default:
> {
> @@ -639,13 +638,13 @@ void helper_top_evaluate_flags(void)
> {
> case 4:
> env->pregs[PR_CCS] =
> - helper_evaluate_flags_alu_4(
> + helper_evaluate_flags_alu_4(env,
> env->pregs[PR_CCS],
> env->cc_src, env->cc_dest,
> env->cc_result);
> break;
> default:
> - helper_evaluate_flags();
> + helper_evaluate_flags(env);
> break;
> }
> }
> diff --git a/target-cris/translate.c b/target-cris/translate.c
> index 1ad9ec7..5e4f7f5 100644
> --- a/target-cris/translate.c
> +++ b/target-cris/translate.c
> @@ -211,9 +211,9 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
> tcg_gen_andi_tl(cpu_PR[r], tn, 3);
> else {
> if (r == PR_PID)
> - gen_helper_tlb_flush_pid(tn);
> + gen_helper_tlb_flush_pid(cpu_env, tn);
> if (dc->tb_flags & S_FLAG && r == PR_SPC)
> - gen_helper_spc_write(tn);
> + gen_helper_spc_write(cpu_env, tn);
> else if (r == PR_CCS)
> dc->cpustate_changed = 1;
> tcg_gen_mov_tl(cpu_PR[r], tn);
> @@ -241,24 +241,24 @@ static int cris_fetch(DisasContext *dc, uint32_t addr,
> switch (size) {
> case 4:
> {
> - r = ldl_code(addr);
> + r = cpu_ldl_code(cpu_single_env, addr);
> break;
> }
> case 2:
> {
> if (sign) {
> - r = ldsw_code(addr);
> + r = cpu_ldsw_code(cpu_single_env, addr);
> } else {
> - r = lduw_code(addr);
> + r = cpu_lduw_code(cpu_single_env, addr);
> }
> break;
> }
> case 1:
> {
> if (sign) {
> - r = ldsb_code(addr);
> + r = cpu_ldsb_code(cpu_single_env, addr);
> } else {
> - r = ldub_code(addr);
> + r = cpu_ldub_code(cpu_single_env, addr);
> }
> break;
> }
> @@ -278,7 +278,7 @@ static void cris_lock_irq(DisasContext *dc)
> static inline void t_gen_raise_exception(uint32_t index)
> {
> TCGv_i32 tmp = tcg_const_i32(index);
> - gen_helper_raise_exception(tmp);
> + gen_helper_raise_exception(cpu_env, tmp);
> tcg_temp_free_i32(tmp);
> }
>
> @@ -624,17 +624,17 @@ static void cris_evaluate_flags(DisasContext *dc)
> switch (dc->cc_op)
> {
> case CC_OP_MCP:
> - gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
> + gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
> cpu_PR[PR_CCS], cc_src,
> cc_dest, cc_result);
> break;
> case CC_OP_MULS:
> - gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
> + gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
> cpu_PR[PR_CCS], cc_result,
> cpu_PR[PR_MOF]);
> break;
> case CC_OP_MULU:
> - gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
> + gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
> cpu_PR[PR_CCS], cc_result,
> cpu_PR[PR_MOF]);
> break;
> @@ -648,15 +648,15 @@ static void cris_evaluate_flags(DisasContext *dc)
> switch (dc->cc_size)
> {
> case 4:
> - gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
> + gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], cpu_env,
> cpu_PR[PR_CCS], cc_result);
> break;
> case 2:
> - gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
> + gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], cpu_env,
> cpu_PR[PR_CCS], cc_result);
> break;
> default:
> - gen_helper_evaluate_flags();
> + gen_helper_evaluate_flags(cpu_env);
> break;
> }
> break;
> @@ -666,21 +666,21 @@ static void cris_evaluate_flags(DisasContext *dc)
> case CC_OP_SUB:
> case CC_OP_CMP:
> if (dc->cc_size == 4)
> - gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
> + gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
> cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
> else
> - gen_helper_evaluate_flags();
> + gen_helper_evaluate_flags(cpu_env);
>
> break;
> default:
> switch (dc->cc_size)
> {
> case 4:
> - gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
> + gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
> cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
> break;
> default:
> - gen_helper_evaluate_flags();
> + gen_helper_evaluate_flags(cpu_env);
> break;
> }
> break;
> @@ -1475,7 +1475,7 @@ static int dec_btstq(DisasContext *dc)
>
> cris_cc_mask(dc, CC_MASK_NZ);
> cris_evaluate_flags(dc);
> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
> tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
> cris_alu(dc, CC_OP_MOVE,
> cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
> @@ -1925,7 +1925,7 @@ static int dec_btst_r(DisasContext *dc)
> dc->op1, dc->op2);
> cris_cc_mask(dc, CC_MASK_NZ);
> cris_evaluate_flags(dc);
> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
> cpu_R[dc->op1], cpu_PR[PR_CCS]);
> cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
> cpu_R[dc->op2], cpu_R[dc->op2], 4);
> @@ -2135,14 +2135,16 @@ static int dec_move_rs(DisasContext *dc)
> {
> LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
> cris_cc_mask(dc, 0);
> - gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
> + gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
> + tcg_const_tl(dc->op1));
> return 2;
> }
> static int dec_move_sr(DisasContext *dc)
> {
> LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
> cris_cc_mask(dc, 0);
> - gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
> + gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
> + tcg_const_tl(dc->op2));
> return 2;
> }
>
> @@ -2906,14 +2908,14 @@ static int dec_rfe_etc(DisasContext *dc)
> /* rfe. */
> LOG_DIS("rfe\n");
> cris_evaluate_flags(dc);
> - gen_helper_rfe();
> + gen_helper_rfe(cpu_env);
> dc->is_jmp = DISAS_UPDATE;
> break;
> case 5:
> /* rfn. */
> LOG_DIS("rfn\n");
> cris_evaluate_flags(dc);
> - gen_helper_rfn();
> + gen_helper_rfn(cpu_env);
> dc->is_jmp = DISAS_UPDATE;
> break;
> case 6:
> diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
> index 3629629..d9d6aa5 100644
> --- a/target-cris/translate_v10.c
> +++ b/target-cris/translate_v10.c
> @@ -182,17 +182,17 @@ static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize,
> if (memsize != 4) {
> if (s_ext) {
> if (memsize == 1)
> - imm = ldsb_code(dc->pc + 2);
> + imm = cpu_ldsb_code(cpu_single_env, dc->pc + 2);
> else
> - imm = ldsw_code(dc->pc + 2);
> + imm = cpu_ldsw_code(cpu_single_env, dc->pc + 2);
> } else {
> if (memsize == 1)
> - imm = ldub_code(dc->pc + 2);
> + imm = cpu_ldub_code(cpu_single_env, dc->pc + 2);
> else
> - imm = lduw_code(dc->pc + 2);
> + imm = cpu_lduw_code(cpu_single_env, dc->pc + 2);
> }
> } else
> - imm = ldl_code(dc->pc + 2);
> + imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
>
> tcg_gen_movi_tl(dst, imm);
Similarly to what I reported for the microblaze and sh4 target, I think
we should not start using cpu_single_env (a global variable) to replace
env (a global variable stored in a register).
It is possible to pass env through the subroutine, though it is more
complicated there than for other targets. I have therefore done the work
and I have attached the two resulting patches to this mail.
> @@ -289,7 +289,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
> } else {
> /* BTST */
> cris_update_cc_op(dc, CC_OP_FLAGS, 4);
> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
> tcg_const_tl(imm), cpu_PR[PR_CCS]);
> }
> break;
> @@ -723,7 +723,7 @@ static unsigned int dec10_reg(DisasContext *dc)
> LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
> cris_cc_mask(dc, CC_MASK_NZVC);
> cris_update_cc_op(dc, CC_OP_FLAGS, 4);
> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
> cpu_R[dc->src], cpu_PR[PR_CCS]);
> break;
> case CRISV10_REG_DSTEP:
> @@ -974,7 +974,7 @@ static int dec10_dip(DisasContext *dc)
> LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
> dc->pc, dc->opcode, dc->src, dc->dst);
> if (dc->src == 15) {
> - imm = ldl_code(dc->pc + 2);
> + imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
> tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
> if (dc->postinc)
> insn_len += 4;
> @@ -1119,7 +1119,7 @@ static unsigned int dec10_ind(DisasContext *dc)
> if (dc->src == 15) {
> LOG_DIS("jump.%d %d r%d r%d direct\n", size,
> dc->opcode, dc->src, dc->dst);
> - imm = ldl_code(dc->pc + 2);
> + imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
> if (dc->mode == CRISV10_MODE_AUTOINC)
> insn_len += size;
>
> @@ -1185,7 +1185,7 @@ static unsigned int dec10_ind(DisasContext *dc)
> case CRISV10_IND_BCC_M:
>
> cris_cc_mask(dc, 0);
> - imm = ldsw_code(dc->pc + 2);
> + imm = cpu_ldsw_code(cpu_single_env, dc->pc + 2);
> simm = (int16_t)imm;
> simm += 4;
>
> @@ -1210,7 +1210,7 @@ static unsigned int crisv10_decoder(DisasContext *dc)
> tcg_gen_debug_insn_start(dc->pc);
>
> /* Load a halfword onto the instruction register. */
> - dc->ir = lduw_code(dc->pc);
> + dc->ir = cpu_lduw_code(cpu_single_env, dc->pc);
>
> /* Now decode it. */
> dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
> --
> 1.7.2.5
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
[-- Attachment #2: 0001-target-cris-Avoid-AREG0-for-helpers.patch --]
[-- Type: text/x-diff, Size: 18412 bytes --]
>From 83e042ff2ce9e1d99fcc127bb5bf43e12673e30e Mon Sep 17 00:00:00 2001
From: Aurelien Jarno <aurelien@aurel32.net>
Date: Thu, 30 Aug 2012 16:56:39 +0200
Subject: [PATCH 1/2] target-cris: Avoid AREG0 for helpers
Add an explicit CPUCRISState parameter instead of relying on AREG0.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-cris/helper.h | 37 +++++++++++---------
target-cris/op_helper.c | 80 +++++++++++++++++++++++--------------------
target-cris/translate.c | 44 ++++++++++++------------
target-cris/translate_v10.c | 4 +--
4 files changed, 88 insertions(+), 77 deletions(-)
diff --git a/target-cris/helper.h b/target-cris/helper.h
index 093063a..99fb326 100644
--- a/target-cris/helper.h
+++ b/target-cris/helper.h
@@ -1,26 +1,29 @@
#include "def-helper.h"
-DEF_HELPER_1(raise_exception, void, i32)
-DEF_HELPER_1(tlb_flush_pid, void, i32)
-DEF_HELPER_1(spc_write, void, i32)
+DEF_HELPER_2(raise_exception, void, env, i32)
+DEF_HELPER_2(tlb_flush_pid, void, env, i32)
+DEF_HELPER_2(spc_write, void, env, i32)
DEF_HELPER_3(dump, void, i32, i32, i32)
-DEF_HELPER_0(rfe, void);
-DEF_HELPER_0(rfn, void);
+DEF_HELPER_1(rfe, void, env);
+DEF_HELPER_1(rfn, void, env);
-DEF_HELPER_2(movl_sreg_reg, void, i32, i32)
-DEF_HELPER_2(movl_reg_sreg, void, i32, i32)
+DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32)
+DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32)
DEF_HELPER_FLAGS_1(lz, TCG_CALL_PURE, i32, i32);
-DEF_HELPER_FLAGS_3(btst, TCG_CALL_PURE, i32, i32, i32, i32);
+DEF_HELPER_FLAGS_4(btst, TCG_CALL_PURE, i32, env, i32, i32, i32);
-DEF_HELPER_FLAGS_3(evaluate_flags_muls, TCG_CALL_PURE, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_3(evaluate_flags_mulu, TCG_CALL_PURE, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_4(evaluate_flags_mcp, TCG_CALL_PURE, i32, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_4(evaluate_flags_alu_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_4(evaluate_flags_sub_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_2(evaluate_flags_move_4, TCG_CALL_PURE, i32, i32, i32)
-DEF_HELPER_FLAGS_2(evaluate_flags_move_2, TCG_CALL_PURE, i32, i32, i32)
-DEF_HELPER_0(evaluate_flags, void)
-DEF_HELPER_0(top_evaluate_flags, void)
+DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_PURE, i32, env, i32, i32, i32)
+DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_PURE, i32, env, i32, i32, i32)
+DEF_HELPER_FLAGS_5(evaluate_flags_mcp, TCG_CALL_PURE, i32, env,
+ i32, i32, i32, i32)
+DEF_HELPER_FLAGS_5(evaluate_flags_alu_4, TCG_CALL_PURE, i32, env,
+ i32, i32, i32, i32)
+DEF_HELPER_FLAGS_5(evaluate_flags_sub_4, TCG_CALL_PURE, i32, env,
+ i32, i32, i32, i32)
+DEF_HELPER_FLAGS_3(evaluate_flags_move_4, TCG_CALL_PURE, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(evaluate_flags_move_2, TCG_CALL_PURE, i32, env, i32, i32)
+DEF_HELPER_1(evaluate_flags, void, env)
+DEF_HELPER_1(top_evaluate_flags, void, env)
#include "def-helper.h"
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index ac7c98c..5ca85a0 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -79,7 +79,7 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
cpu_restore_state(tb, env, retaddr);
/* Evaluate flags after retranslation. */
- helper_top_evaluate_flags();
+ helper_top_evaluate_flags(env);
}
}
cpu_loop_exit(env);
@@ -89,13 +89,13 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
#endif
-void helper_raise_exception(uint32_t index)
+void helper_raise_exception(CPUCRISState *env, uint32_t index)
{
env->exception_index = index;
cpu_loop_exit(env);
}
-void helper_tlb_flush_pid(uint32_t pid)
+void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
{
#if !defined(CONFIG_USER_ONLY)
pid &= 0xff;
@@ -104,7 +104,7 @@ void helper_tlb_flush_pid(uint32_t pid)
#endif
}
-void helper_spc_write(uint32_t new_spc)
+void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
tlb_flush_page(env, env->pregs[PR_SPC]);
@@ -121,7 +121,7 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
#define EXTRACT_FIELD(src, start, end) \
(((src) >> start) & ((1 << (end - start + 1)) - 1))
-void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
+void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
{
uint32_t srs;
srs = env->pregs[PR_SRS];
@@ -171,7 +171,7 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
#endif
}
-void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
+void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
{
uint32_t srs;
env->pregs[PR_SRS] &= 3;
@@ -216,7 +216,7 @@ static void cris_ccs_rshift(CPUCRISState *env)
env->pregs[PR_CCS] = ccs;
}
-void helper_rfe(void)
+void helper_rfe(CPUCRISState *env)
{
int rflag = env->pregs[PR_CCS] & R_FLAG;
@@ -232,7 +232,7 @@ void helper_rfe(void)
env->pregs[PR_CCS] |= P_FLAG;
}
-void helper_rfn(void)
+void helper_rfn(CPUCRISState *env)
{
int rflag = env->pregs[PR_CCS] & R_FLAG;
@@ -256,7 +256,7 @@ uint32_t helper_lz(uint32_t t0)
return clz32(t0);
}
-uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
+uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
{
/* FIXME: clean this up. */
@@ -284,7 +284,8 @@ uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
return ccs;
}
-static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
+static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
+ uint32_t flags, uint32_t ccs)
{
unsigned int x, z, mask;
@@ -303,7 +304,8 @@ static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
return ccs;
}
-uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
+uint32_t helper_evaluate_flags_muls(CPUCRISState *env,
+ uint32_t ccs, uint32_t res, uint32_t mof)
{
uint32_t flags = 0;
int64_t tmp;
@@ -321,10 +323,11 @@ uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
if ((dneg && mof != -1)
|| (!dneg && mof != 0))
flags |= V_FLAG;
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
+uint32_t helper_evaluate_flags_mulu(CPUCRISState *env,
+ uint32_t ccs, uint32_t res, uint32_t mof)
{
uint32_t flags = 0;
uint64_t tmp;
@@ -339,10 +342,10 @@ uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
if (mof)
flags |= V_FLAG;
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
+uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
uint32_t flags = 0;
@@ -368,10 +371,10 @@ uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
flags |= R_FLAG;
}
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
+uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
uint32_t flags = 0;
@@ -397,10 +400,10 @@ uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
flags |= C_FLAG;
}
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
+uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
uint32_t flags = 0;
@@ -427,10 +430,11 @@ uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
}
flags ^= C_FLAG;
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
+uint32_t helper_evaluate_flags_move_4(CPUCRISState *env,
+ uint32_t ccs, uint32_t res)
{
uint32_t flags = 0;
@@ -439,9 +443,10 @@ uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
else if (res == 0L)
flags |= Z_FLAG;
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
+uint32_t helper_evaluate_flags_move_2(CPUCRISState *env,
+ uint32_t ccs, uint32_t res)
{
uint32_t flags = 0;
@@ -450,12 +455,12 @@ uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
else if (res == 0)
flags |= Z_FLAG;
- return evaluate_flags_writeback(flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
/* TODO: This is expensive. We could split things up and only evaluate part of
CCR on a need to know basis. For now, we simply re-evaluate everything. */
-void helper_evaluate_flags(void)
+void helper_evaluate_flags(CPUCRISState *env)
{
uint32_t src, dst, res;
uint32_t flags = 0;
@@ -571,25 +576,26 @@ void helper_evaluate_flags(void)
if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
flags ^= C_FLAG;
- env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
+ env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
+ env->pregs[PR_CCS]);
}
-void helper_top_evaluate_flags(void)
+void helper_top_evaluate_flags(CPUCRISState *env)
{
switch (env->cc_op)
{
case CC_OP_MCP:
- env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
+ env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
env->pregs[PR_CCS], env->cc_src,
env->cc_dest, env->cc_result);
break;
case CC_OP_MULS:
- env->pregs[PR_CCS] = helper_evaluate_flags_muls(
+ env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
env->pregs[PR_CCS], env->cc_result,
env->pregs[PR_MOF]);
break;
case CC_OP_MULU:
- env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
+ env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
env->pregs[PR_CCS], env->cc_result,
env->pregs[PR_MOF]);
break;
@@ -604,18 +610,18 @@ void helper_top_evaluate_flags(void)
{
case 4:
env->pregs[PR_CCS] =
- helper_evaluate_flags_move_4(
+ helper_evaluate_flags_move_4(env,
env->pregs[PR_CCS],
env->cc_result);
break;
case 2:
env->pregs[PR_CCS] =
- helper_evaluate_flags_move_2(
+ helper_evaluate_flags_move_2(env,
env->pregs[PR_CCS],
env->cc_result);
break;
default:
- helper_evaluate_flags();
+ helper_evaluate_flags(env);
break;
}
break;
@@ -626,12 +632,12 @@ void helper_top_evaluate_flags(void)
case CC_OP_CMP:
if (env->cc_size == 4)
env->pregs[PR_CCS] =
- helper_evaluate_flags_sub_4(
+ helper_evaluate_flags_sub_4(env,
env->pregs[PR_CCS],
env->cc_src, env->cc_dest,
env->cc_result);
else
- helper_evaluate_flags();
+ helper_evaluate_flags(env);
break;
default:
{
@@ -639,13 +645,13 @@ void helper_top_evaluate_flags(void)
{
case 4:
env->pregs[PR_CCS] =
- helper_evaluate_flags_alu_4(
+ helper_evaluate_flags_alu_4(env,
env->pregs[PR_CCS],
env->cc_src, env->cc_dest,
env->cc_result);
break;
default:
- helper_evaluate_flags();
+ helper_evaluate_flags(env);
break;
}
}
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 1ad9ec7..d9759fc 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -211,9 +211,9 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
tcg_gen_andi_tl(cpu_PR[r], tn, 3);
else {
if (r == PR_PID)
- gen_helper_tlb_flush_pid(tn);
+ gen_helper_tlb_flush_pid(cpu_env, tn);
if (dc->tb_flags & S_FLAG && r == PR_SPC)
- gen_helper_spc_write(tn);
+ gen_helper_spc_write(cpu_env, tn);
else if (r == PR_CCS)
dc->cpustate_changed = 1;
tcg_gen_mov_tl(cpu_PR[r], tn);
@@ -278,7 +278,7 @@ static void cris_lock_irq(DisasContext *dc)
static inline void t_gen_raise_exception(uint32_t index)
{
TCGv_i32 tmp = tcg_const_i32(index);
- gen_helper_raise_exception(tmp);
+ gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
}
@@ -624,17 +624,17 @@ static void cris_evaluate_flags(DisasContext *dc)
switch (dc->cc_op)
{
case CC_OP_MCP:
- gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_src,
cc_dest, cc_result);
break;
case CC_OP_MULS:
- gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_result,
cpu_PR[PR_MOF]);
break;
case CC_OP_MULU:
- gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_result,
cpu_PR[PR_MOF]);
break;
@@ -648,15 +648,15 @@ static void cris_evaluate_flags(DisasContext *dc)
switch (dc->cc_size)
{
case 4:
- gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
- cpu_PR[PR_CCS], cc_result);
+ gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
+ cpu_env, cpu_PR[PR_CCS], cc_result);
break;
case 2:
- gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
- cpu_PR[PR_CCS], cc_result);
+ gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
+ cpu_env, cpu_PR[PR_CCS], cc_result);
break;
default:
- gen_helper_evaluate_flags();
+ gen_helper_evaluate_flags(cpu_env);
break;
}
break;
@@ -666,21 +666,21 @@ static void cris_evaluate_flags(DisasContext *dc)
case CC_OP_SUB:
case CC_OP_CMP:
if (dc->cc_size == 4)
- gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
else
- gen_helper_evaluate_flags();
+ gen_helper_evaluate_flags(cpu_env);
break;
default:
switch (dc->cc_size)
{
case 4:
- gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
+ gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
break;
default:
- gen_helper_evaluate_flags();
+ gen_helper_evaluate_flags(cpu_env);
break;
}
break;
@@ -1475,7 +1475,7 @@ static int dec_btstq(DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZ);
cris_evaluate_flags(dc);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
cris_alu(dc, CC_OP_MOVE,
cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
@@ -1925,7 +1925,7 @@ static int dec_btst_r(DisasContext *dc)
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_evaluate_flags(dc);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
cpu_R[dc->op1], cpu_PR[PR_CCS]);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
cpu_R[dc->op2], cpu_R[dc->op2], 4);
@@ -2135,14 +2135,16 @@ static int dec_move_rs(DisasContext *dc)
{
LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
- gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
+ gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
+ tcg_const_tl(dc->op1));
return 2;
}
static int dec_move_sr(DisasContext *dc)
{
LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
cris_cc_mask(dc, 0);
- gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
+ gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
+ tcg_const_tl(dc->op2));
return 2;
}
@@ -2906,14 +2908,14 @@ static int dec_rfe_etc(DisasContext *dc)
/* rfe. */
LOG_DIS("rfe\n");
cris_evaluate_flags(dc);
- gen_helper_rfe();
+ gen_helper_rfe(cpu_env);
dc->is_jmp = DISAS_UPDATE;
break;
case 5:
/* rfn. */
LOG_DIS("rfn\n");
cris_evaluate_flags(dc);
- gen_helper_rfn();
+ gen_helper_rfn(cpu_env);
dc->is_jmp = DISAS_UPDATE;
break;
case 6:
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 3629629..9a39c6a 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -289,7 +289,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
} else {
/* BTST */
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
tcg_const_tl(imm), cpu_PR[PR_CCS]);
}
break;
@@ -723,7 +723,7 @@ static unsigned int dec10_reg(DisasContext *dc)
LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
cpu_R[dc->src], cpu_PR[PR_CCS]);
break;
case CRISV10_REG_DSTEP:
--
1.7.10.4
[-- Attachment #3: 0002-target-cris-Switch-to-AREG0-free-mode.patch --]
[-- Type: text/x-diff, Size: 49568 bytes --]
>From 70308b3e4bed96640f776c679c08b9db07d2fd5f Mon Sep 17 00:00:00 2001
From: Aurelien Jarno <aurelien@aurel32.net>
Date: Fri, 7 Sep 2012 16:13:27 +0200
Subject: [PATCH 2/2] target-cris: Switch to AREG0 free mode
Add an explicit CPUCRISState parameter instead of relying on AREG0, and
use cpu_ld* in translation and interrupt handling. Remove AREG0 swapping
in tlb_fill(). Switch to AREG0 free mode
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
configure | 2 +-
target-cris/Makefile.objs | 2 -
target-cris/helper.c | 4 +-
target-cris/op_helper.c | 9 +-
target-cris/translate.c | 256 +++++++++++++++++++++----------------------
target-cris/translate_v10.c | 95 ++++++++--------
6 files changed, 181 insertions(+), 187 deletions(-)
diff --git a/configure b/configure
index e464d2f..34b5f78 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
case "$target_arch2" in
- alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
+ alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc* | )
echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
;;
esac
diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
index 4b09e8c..afb87bc 100644
--- a/target-cris/Makefile.objs
+++ b/target-cris/Makefile.objs
@@ -1,4 +1,2 @@
obj-y += translate.o op_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-cris/helper.c b/target-cris/helper.c
index bfbc29e..1bdb7e2 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -151,7 +151,7 @@ static void do_interruptv10(CPUCRISState *env)
}
/* Now that we are in kernel mode, load the handlers address. */
- env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
+ env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
env->locked_irq = 1;
env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
@@ -233,7 +233,7 @@ void do_interrupt(CPUCRISState *env)
/* Now that we are in kernel mode, load the handlers address.
This load may not fault, real hw leaves that behaviour as
undefined. */
- env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
+ env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
/* Clear the excption_index to avoid spurios hw_aborts for recursive
bus faults. */
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 5ca85a0..a7468d4 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -19,7 +19,6 @@
*/
#include "cpu.h"
-#include "dyngen-exec.h"
#include "mmu.h"
#include "helper.h"
#include "host-utils.h"
@@ -55,17 +54,12 @@
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
TranslationBlock *tb;
- CPUCRISState *saved_env;
int ret;
- saved_env = env;
- env = env1;
-
D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
env->pc, env->debug1, (void *)retaddr);
ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
@@ -84,7 +78,6 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
}
cpu_loop_exit(env);
}
- env = saved_env;
}
#endif
diff --git a/target-cris/translate.c b/target-cris/translate.c
index d9759fc..add7f83 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -78,7 +78,7 @@ typedef struct DisasContext {
target_ulong pc, ppc;
/* Decoder. */
- unsigned int (*decoder)(struct DisasContext *dc);
+ unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
uint32_t ir;
uint32_t opcode;
unsigned int op1;
@@ -233,7 +233,7 @@ static int sign_extend(unsigned int val, unsigned int width)
return sval;
}
-static int cris_fetch(DisasContext *dc, uint32_t addr,
+static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
unsigned int size, unsigned int sign)
{
int r;
@@ -241,24 +241,24 @@ static int cris_fetch(DisasContext *dc, uint32_t addr,
switch (size) {
case 4:
{
- r = ldl_code(addr);
+ r = cpu_ldl_code(env, addr);
break;
}
case 2:
{
if (sign) {
- r = ldsw_code(addr);
+ r = cpu_ldsw_code(env, addr);
} else {
- r = lduw_code(addr);
+ r = cpu_lduw_code(env, addr);
}
break;
}
case 1:
{
if (sign) {
- r = ldsb_code(addr);
+ r = cpu_ldsb_code(env, addr);
} else {
- r = ldub_code(addr);
+ r = cpu_ldub_code(env, addr);
}
break;
}
@@ -1304,8 +1304,8 @@ static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
t_gen_zext(dst, cpu_R[rd], size);
}
-static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
- TCGv dst)
+static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
+ int s_ext, int memsize, TCGv dst)
{
unsigned int rs;
uint32_t imm;
@@ -1321,7 +1321,7 @@ static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
if (memsize == 1)
insn_len++;
- imm = cris_fetch(dc, dc->pc + 2, memsize, s_ext);
+ imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
tcg_gen_movi_tl(dst, imm);
dc->postinc = 0;
} else {
@@ -1338,12 +1338,12 @@ static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
/* Prepare T0 and T1 for a memory + alu operation.
s_ext decides if the operand1 should be sign-extended or zero-extended when
needed. */
-static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize,
- TCGv dst, TCGv src)
+static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
+ int s_ext, int memsize, TCGv dst, TCGv src)
{
int insn_len;
- insn_len = dec_prep_move_m(dc, s_ext, memsize, src);
+ insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
return insn_len;
}
@@ -1362,7 +1362,7 @@ static const char *cc_name(int cc)
/* Start of insn decoders. */
-static int dec_bccq(DisasContext *dc)
+static int dec_bccq(CPUCRISState *env, DisasContext *dc)
{
int32_t offset;
int sign;
@@ -1382,7 +1382,7 @@ static int dec_bccq(DisasContext *dc)
cris_prepare_cc_branch (dc, offset, cond);
return 2;
}
-static int dec_addoq(DisasContext *dc)
+static int dec_addoq(CPUCRISState *env, DisasContext *dc)
{
int32_t imm;
@@ -1396,7 +1396,7 @@ static int dec_addoq(DisasContext *dc)
return 2;
}
-static int dec_addq(DisasContext *dc)
+static int dec_addq(CPUCRISState *env, DisasContext *dc)
{
LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
@@ -1408,7 +1408,7 @@ static int dec_addq(DisasContext *dc)
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
return 2;
}
-static int dec_moveq(DisasContext *dc)
+static int dec_moveq(CPUCRISState *env, DisasContext *dc)
{
uint32_t imm;
@@ -1419,7 +1419,7 @@ static int dec_moveq(DisasContext *dc)
tcg_gen_movi_tl(cpu_R[dc->op2], imm);
return 2;
}
-static int dec_subq(DisasContext *dc)
+static int dec_subq(CPUCRISState *env, DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
@@ -1430,7 +1430,7 @@ static int dec_subq(DisasContext *dc)
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
return 2;
}
-static int dec_cmpq(DisasContext *dc)
+static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
{
uint32_t imm;
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
@@ -1443,7 +1443,7 @@ static int dec_cmpq(DisasContext *dc)
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
return 2;
}
-static int dec_andq(DisasContext *dc)
+static int dec_andq(CPUCRISState *env, DisasContext *dc)
{
uint32_t imm;
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
@@ -1456,7 +1456,7 @@ static int dec_andq(DisasContext *dc)
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
return 2;
}
-static int dec_orq(DisasContext *dc)
+static int dec_orq(CPUCRISState *env, DisasContext *dc)
{
uint32_t imm;
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
@@ -1468,7 +1468,7 @@ static int dec_orq(DisasContext *dc)
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
return 2;
}
-static int dec_btstq(DisasContext *dc)
+static int dec_btstq(CPUCRISState *env, DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
@@ -1483,7 +1483,7 @@ static int dec_btstq(DisasContext *dc)
dc->flags_uptodate = 1;
return 2;
}
-static int dec_asrq(DisasContext *dc)
+static int dec_asrq(CPUCRISState *env, DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
@@ -1495,7 +1495,7 @@ static int dec_asrq(DisasContext *dc)
cpu_R[dc->op2], cpu_R[dc->op2], 4);
return 2;
}
-static int dec_lslq(DisasContext *dc)
+static int dec_lslq(CPUCRISState *env, DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
@@ -1509,7 +1509,7 @@ static int dec_lslq(DisasContext *dc)
cpu_R[dc->op2], cpu_R[dc->op2], 4);
return 2;
}
-static int dec_lsrq(DisasContext *dc)
+static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
@@ -1523,7 +1523,7 @@ static int dec_lsrq(DisasContext *dc)
return 2;
}
-static int dec_move_r(DisasContext *dc)
+static int dec_move_r(CPUCRISState *env, DisasContext *dc)
{
int size = memsize_zz(dc);
@@ -1551,7 +1551,7 @@ static int dec_move_r(DisasContext *dc)
return 2;
}
-static int dec_scc_r(DisasContext *dc)
+static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
{
int cond = dc->op2;
@@ -1594,7 +1594,7 @@ static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
}
}
-static int dec_and_r(DisasContext *dc)
+static int dec_and_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1611,7 +1611,7 @@ static int dec_and_r(DisasContext *dc)
return 2;
}
-static int dec_lz_r(DisasContext *dc)
+static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
LOG_DIS("lz $r%u, $r%u\n",
@@ -1624,7 +1624,7 @@ static int dec_lz_r(DisasContext *dc)
return 2;
}
-static int dec_lsl_r(DisasContext *dc)
+static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1641,7 +1641,7 @@ static int dec_lsl_r(DisasContext *dc)
return 2;
}
-static int dec_lsr_r(DisasContext *dc)
+static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1658,7 +1658,7 @@ static int dec_lsr_r(DisasContext *dc)
return 2;
}
-static int dec_asr_r(DisasContext *dc)
+static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1675,7 +1675,7 @@ static int dec_asr_r(DisasContext *dc)
return 2;
}
-static int dec_muls_r(DisasContext *dc)
+static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1691,7 +1691,7 @@ static int dec_muls_r(DisasContext *dc)
return 2;
}
-static int dec_mulu_r(DisasContext *dc)
+static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1708,7 +1708,7 @@ static int dec_mulu_r(DisasContext *dc)
}
-static int dec_dstep_r(DisasContext *dc)
+static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
{
LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
@@ -1717,7 +1717,7 @@ static int dec_dstep_r(DisasContext *dc)
return 2;
}
-static int dec_xor_r(DisasContext *dc)
+static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1733,7 +1733,7 @@ static int dec_xor_r(DisasContext *dc)
return 2;
}
-static int dec_bound_r(DisasContext *dc)
+static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
{
TCGv l0;
int size = memsize_zz(dc);
@@ -1747,7 +1747,7 @@ static int dec_bound_r(DisasContext *dc)
return 2;
}
-static int dec_cmp_r(DisasContext *dc)
+static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1762,7 +1762,7 @@ static int dec_cmp_r(DisasContext *dc)
return 2;
}
-static int dec_abs_r(DisasContext *dc)
+static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
@@ -1781,7 +1781,7 @@ static int dec_abs_r(DisasContext *dc)
return 2;
}
-static int dec_add_r(DisasContext *dc)
+static int dec_add_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1796,7 +1796,7 @@ static int dec_add_r(DisasContext *dc)
return 2;
}
-static int dec_addc_r(DisasContext *dc)
+static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
{
LOG_DIS("addc $r%u, $r%u\n",
dc->op1, dc->op2);
@@ -1811,7 +1811,7 @@ static int dec_addc_r(DisasContext *dc)
return 2;
}
-static int dec_mcp_r(DisasContext *dc)
+static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
{
LOG_DIS("mcp $p%u, $r%u\n",
dc->op2, dc->op1);
@@ -1838,7 +1838,7 @@ static char * swapmode_name(int mode, char *modename) {
}
#endif
-static int dec_swap_r(DisasContext *dc)
+static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
#if DISAS_CRIS
@@ -1864,7 +1864,7 @@ static int dec_swap_r(DisasContext *dc)
return 2;
}
-static int dec_or_r(DisasContext *dc)
+static int dec_or_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1878,7 +1878,7 @@ static int dec_or_r(DisasContext *dc)
return 2;
}
-static int dec_addi_r(DisasContext *dc)
+static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
LOG_DIS("addi.%c $r%u, $r%u\n",
@@ -1891,7 +1891,7 @@ static int dec_addi_r(DisasContext *dc)
return 2;
}
-static int dec_addi_acr(DisasContext *dc)
+static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
@@ -1904,7 +1904,7 @@ static int dec_addi_acr(DisasContext *dc)
return 2;
}
-static int dec_neg_r(DisasContext *dc)
+static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1919,7 +1919,7 @@ static int dec_neg_r(DisasContext *dc)
return 2;
}
-static int dec_btst_r(DisasContext *dc)
+static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
{
LOG_DIS("btst $r%u, $r%u\n",
dc->op1, dc->op2);
@@ -1934,7 +1934,7 @@ static int dec_btst_r(DisasContext *dc)
return 2;
}
-static int dec_sub_r(DisasContext *dc)
+static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
@@ -1949,7 +1949,7 @@ static int dec_sub_r(DisasContext *dc)
}
/* Zero extension. From size to dword. */
-static int dec_movu_r(DisasContext *dc)
+static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
@@ -1966,7 +1966,7 @@ static int dec_movu_r(DisasContext *dc)
}
/* Sign extension. From size to dword. */
-static int dec_movs_r(DisasContext *dc)
+static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
@@ -1985,7 +1985,7 @@ static int dec_movs_r(DisasContext *dc)
}
/* zero extension. From size to dword. */
-static int dec_addu_r(DisasContext *dc)
+static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
@@ -2004,7 +2004,7 @@ static int dec_addu_r(DisasContext *dc)
}
/* Sign extension. From size to dword. */
-static int dec_adds_r(DisasContext *dc)
+static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
@@ -2023,7 +2023,7 @@ static int dec_adds_r(DisasContext *dc)
}
/* Zero extension. From size to dword. */
-static int dec_subu_r(DisasContext *dc)
+static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
@@ -2042,7 +2042,7 @@ static int dec_subu_r(DisasContext *dc)
}
/* Sign extension. From size to dword. */
-static int dec_subs_r(DisasContext *dc)
+static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
@@ -2060,7 +2060,7 @@ static int dec_subs_r(DisasContext *dc)
return 2;
}
-static int dec_setclrf(DisasContext *dc)
+static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
{
uint32_t flags;
int set = (~dc->opcode >> 2) & 1;
@@ -2131,7 +2131,7 @@ static int dec_setclrf(DisasContext *dc)
return 2;
}
-static int dec_move_rs(DisasContext *dc)
+static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
{
LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
@@ -2139,7 +2139,7 @@ static int dec_move_rs(DisasContext *dc)
tcg_const_tl(dc->op1));
return 2;
}
-static int dec_move_sr(DisasContext *dc)
+static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
{
LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
cris_cc_mask(dc, 0);
@@ -2148,7 +2148,7 @@ static int dec_move_sr(DisasContext *dc)
return 2;
}
-static int dec_move_rp(DisasContext *dc)
+static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
@@ -2178,7 +2178,7 @@ static int dec_move_rp(DisasContext *dc)
tcg_temp_free(t[0]);
return 2;
}
-static int dec_move_pr(DisasContext *dc)
+static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
@@ -2200,7 +2200,7 @@ static int dec_move_pr(DisasContext *dc)
return 2;
}
-static int dec_move_mr(DisasContext *dc)
+static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
{
int memsize = memsize_zz(dc);
int insn_len;
@@ -2210,7 +2210,7 @@ static int dec_move_mr(DisasContext *dc)
dc->op2);
if (memsize == 4) {
- insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
+ insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
cris_cc_mask(dc, CC_MASK_NZ);
cris_update_cc_op(dc, CC_OP_MOVE, 4);
cris_update_cc_x(dc);
@@ -2220,7 +2220,7 @@ static int dec_move_mr(DisasContext *dc)
TCGv t0;
t0 = tcg_temp_new();
- insn_len = dec_prep_move_m(dc, 0, memsize, t0);
+ insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_MOVE,
cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
@@ -2242,7 +2242,7 @@ static inline void cris_alu_m_free_temps(TCGv *t)
tcg_temp_free(t[1]);
}
-static int dec_movs_m(DisasContext *dc)
+static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
@@ -2254,7 +2254,7 @@ static int dec_movs_m(DisasContext *dc)
cris_alu_m_alloc_temps(t);
/* sign extend. */
- insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_MOVE,
cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
@@ -2263,7 +2263,7 @@ static int dec_movs_m(DisasContext *dc)
return insn_len;
}
-static int dec_addu_m(DisasContext *dc)
+static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
@@ -2275,7 +2275,7 @@ static int dec_addu_m(DisasContext *dc)
cris_alu_m_alloc_temps(t);
/* sign extend. */
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_ADD,
cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
@@ -2284,7 +2284,7 @@ static int dec_addu_m(DisasContext *dc)
return insn_len;
}
-static int dec_adds_m(DisasContext *dc)
+static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
@@ -2296,7 +2296,7 @@ static int dec_adds_m(DisasContext *dc)
cris_alu_m_alloc_temps(t);
/* sign extend. */
- insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
do_postinc(dc, memsize);
@@ -2304,7 +2304,7 @@ static int dec_adds_m(DisasContext *dc)
return insn_len;
}
-static int dec_subu_m(DisasContext *dc)
+static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
@@ -2316,7 +2316,7 @@ static int dec_subu_m(DisasContext *dc)
cris_alu_m_alloc_temps(t);
/* sign extend. */
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
do_postinc(dc, memsize);
@@ -2324,7 +2324,7 @@ static int dec_subu_m(DisasContext *dc)
return insn_len;
}
-static int dec_subs_m(DisasContext *dc)
+static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
@@ -2336,7 +2336,7 @@ static int dec_subs_m(DisasContext *dc)
cris_alu_m_alloc_temps(t);
/* sign extend. */
- insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
do_postinc(dc, memsize);
@@ -2344,7 +2344,7 @@ static int dec_subs_m(DisasContext *dc)
return insn_len;
}
-static int dec_movu_m(DisasContext *dc)
+static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
@@ -2356,7 +2356,7 @@ static int dec_movu_m(DisasContext *dc)
dc->op2);
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
do_postinc(dc, memsize);
@@ -2364,7 +2364,7 @@ static int dec_movu_m(DisasContext *dc)
return insn_len;
}
-static int dec_cmpu_m(DisasContext *dc)
+static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
@@ -2375,7 +2375,7 @@ static int dec_cmpu_m(DisasContext *dc)
dc->op2);
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
do_postinc(dc, memsize);
@@ -2383,7 +2383,7 @@ static int dec_cmpu_m(DisasContext *dc)
return insn_len;
}
-static int dec_cmps_m(DisasContext *dc)
+static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
@@ -2394,7 +2394,7 @@ static int dec_cmps_m(DisasContext *dc)
dc->op2);
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_CMP,
cpu_R[dc->op2], cpu_R[dc->op2], t[1],
@@ -2404,7 +2404,7 @@ static int dec_cmps_m(DisasContext *dc)
return insn_len;
}
-static int dec_cmp_m(DisasContext *dc)
+static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
@@ -2415,7 +2415,7 @@ static int dec_cmp_m(DisasContext *dc)
dc->op2);
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_CMP,
cpu_R[dc->op2], cpu_R[dc->op2], t[1],
@@ -2425,7 +2425,7 @@ static int dec_cmp_m(DisasContext *dc)
return insn_len;
}
-static int dec_test_m(DisasContext *dc)
+static int dec_test_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
@@ -2438,7 +2438,7 @@ static int dec_test_m(DisasContext *dc)
cris_evaluate_flags(dc);
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZ);
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
@@ -2449,7 +2449,7 @@ static int dec_test_m(DisasContext *dc)
return insn_len;
}
-static int dec_and_m(DisasContext *dc)
+static int dec_and_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
@@ -2460,7 +2460,7 @@ static int dec_and_m(DisasContext *dc)
dc->op2);
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
do_postinc(dc, memsize);
@@ -2468,7 +2468,7 @@ static int dec_and_m(DisasContext *dc)
return insn_len;
}
-static int dec_add_m(DisasContext *dc)
+static int dec_add_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
@@ -2479,7 +2479,7 @@ static int dec_add_m(DisasContext *dc)
dc->op2);
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_ADD,
cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
@@ -2488,7 +2488,7 @@ static int dec_add_m(DisasContext *dc)
return insn_len;
}
-static int dec_addo_m(DisasContext *dc)
+static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
@@ -2499,7 +2499,7 @@ static int dec_addo_m(DisasContext *dc)
dc->op2);
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
cris_cc_mask(dc, 0);
cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
do_postinc(dc, memsize);
@@ -2507,7 +2507,7 @@ static int dec_addo_m(DisasContext *dc)
return insn_len;
}
-static int dec_bound_m(DisasContext *dc)
+static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
{
TCGv l[2];
int memsize = memsize_zz(dc);
@@ -2519,7 +2519,7 @@ static int dec_bound_m(DisasContext *dc)
l[0] = tcg_temp_local_new();
l[1] = tcg_temp_local_new();
- insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
do_postinc(dc, memsize);
@@ -2528,7 +2528,7 @@ static int dec_bound_m(DisasContext *dc)
return insn_len;
}
-static int dec_addc_mr(DisasContext *dc)
+static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int insn_len = 2;
@@ -2543,7 +2543,7 @@ static int dec_addc_mr(DisasContext *dc)
dc->flags_x = X_FLAG;
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
do_postinc(dc, 4);
@@ -2551,7 +2551,7 @@ static int dec_addc_mr(DisasContext *dc)
return insn_len;
}
-static int dec_sub_m(DisasContext *dc)
+static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
@@ -2562,7 +2562,7 @@ static int dec_sub_m(DisasContext *dc)
dc->op2, dc->ir, dc->zzsize);
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
do_postinc(dc, memsize);
@@ -2570,7 +2570,7 @@ static int dec_sub_m(DisasContext *dc)
return insn_len;
}
-static int dec_or_m(DisasContext *dc)
+static int dec_or_m(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
@@ -2581,7 +2581,7 @@ static int dec_or_m(DisasContext *dc)
dc->op2, dc->pc);
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_OR,
cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
@@ -2590,7 +2590,7 @@ static int dec_or_m(DisasContext *dc)
return insn_len;
}
-static int dec_move_mp(DisasContext *dc)
+static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
@@ -2603,7 +2603,7 @@ static int dec_move_mp(DisasContext *dc)
dc->op2);
cris_alu_m_alloc_temps(t);
- insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
+ insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
cris_cc_mask(dc, 0);
if (dc->op2 == PR_CCS) {
cris_evaluate_flags(dc);
@@ -2622,7 +2622,7 @@ static int dec_move_mp(DisasContext *dc)
return insn_len;
}
-static int dec_move_pm(DisasContext *dc)
+static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
{
TCGv t0;
int memsize;
@@ -2648,7 +2648,7 @@ static int dec_move_pm(DisasContext *dc)
return 2;
}
-static int dec_movem_mr(DisasContext *dc)
+static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
{
TCGv_i64 tmp[16];
TCGv tmp32;
@@ -2695,7 +2695,7 @@ static int dec_movem_mr(DisasContext *dc)
return 2;
}
-static int dec_movem_rm(DisasContext *dc)
+static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
{
TCGv tmp;
TCGv addr;
@@ -2724,7 +2724,7 @@ static int dec_movem_rm(DisasContext *dc)
return 2;
}
-static int dec_move_rm(DisasContext *dc)
+static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
{
int memsize;
@@ -2743,7 +2743,7 @@ static int dec_move_rm(DisasContext *dc)
return 2;
}
-static int dec_lapcq(DisasContext *dc)
+static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
{
LOG_DIS("lapcq %x, $r%u\n",
dc->pc + dc->op1*2, dc->op2);
@@ -2752,7 +2752,7 @@ static int dec_lapcq(DisasContext *dc)
return 2;
}
-static int dec_lapc_im(DisasContext *dc)
+static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
{
unsigned int rd;
int32_t imm;
@@ -2761,7 +2761,7 @@ static int dec_lapc_im(DisasContext *dc)
rd = dc->op2;
cris_cc_mask(dc, 0);
- imm = cris_fetch(dc, dc->pc + 2, 4, 0);
+ imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
pc = dc->pc;
@@ -2771,7 +2771,7 @@ static int dec_lapc_im(DisasContext *dc)
}
/* Jump to special reg. */
-static int dec_jump_p(DisasContext *dc)
+static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
{
LOG_DIS("jump $p%u\n", dc->op2);
@@ -2786,7 +2786,7 @@ static int dec_jump_p(DisasContext *dc)
}
/* Jump and save. */
-static int dec_jas_r(DisasContext *dc)
+static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
{
LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
@@ -2800,11 +2800,11 @@ static int dec_jas_r(DisasContext *dc)
return 2;
}
-static int dec_jas_im(DisasContext *dc)
+static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
{
uint32_t imm;
- imm = cris_fetch(dc, dc->pc + 2, 4, 0);
+ imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
LOG_DIS("jas 0x%x\n", imm);
cris_cc_mask(dc, 0);
@@ -2816,11 +2816,11 @@ static int dec_jas_im(DisasContext *dc)
return 6;
}
-static int dec_jasc_im(DisasContext *dc)
+static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
{
uint32_t imm;
- imm = cris_fetch(dc, dc->pc + 2, 4, 0);
+ imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
LOG_DIS("jasc 0x%x\n", imm);
cris_cc_mask(dc, 0);
@@ -2832,7 +2832,7 @@ static int dec_jasc_im(DisasContext *dc)
return 6;
}
-static int dec_jasc_r(DisasContext *dc)
+static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
{
LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
@@ -2843,12 +2843,12 @@ static int dec_jasc_r(DisasContext *dc)
return 2;
}
-static int dec_bcc_im(DisasContext *dc)
+static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
{
int32_t offset;
uint32_t cond = dc->op2;
- offset = cris_fetch(dc, dc->pc + 2, 2, 1);
+ offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
LOG_DIS("b%s %d pc=%x dst=%x\n",
cc_name(cond), offset,
@@ -2860,12 +2860,12 @@ static int dec_bcc_im(DisasContext *dc)
return 4;
}
-static int dec_bas_im(DisasContext *dc)
+static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
{
int32_t simm;
- simm = cris_fetch(dc, dc->pc + 2, 4, 0);
+ simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
@@ -2877,10 +2877,10 @@ static int dec_bas_im(DisasContext *dc)
return 6;
}
-static int dec_basc_im(DisasContext *dc)
+static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
{
int32_t simm;
- simm = cris_fetch(dc, dc->pc + 2, 4, 0);
+ simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
@@ -2892,7 +2892,7 @@ static int dec_basc_im(DisasContext *dc)
return 6;
}
-static int dec_rfe_etc(DisasContext *dc)
+static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
{
cris_cc_mask(dc, 0);
@@ -2939,17 +2939,17 @@ static int dec_rfe_etc(DisasContext *dc)
return 2;
}
-static int dec_ftag_fidx_d_m(DisasContext *dc)
+static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
{
return 2;
}
-static int dec_ftag_fidx_i_m(DisasContext *dc)
+static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
{
return 2;
}
-static int dec_null(DisasContext *dc)
+static int dec_null(CPUCRISState *env, DisasContext *dc)
{
printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
dc->pc, dc->opcode, dc->op1, dc->op2);
@@ -2963,7 +2963,7 @@ static struct decoder_info {
uint32_t bits;
uint32_t mask;
};
- int (*dec)(DisasContext *dc);
+ int (*dec)(CPUCRISState *env, DisasContext *dc);
} decinfo[] = {
/* Order matters here. */
{DEC_MOVEQ, dec_moveq},
@@ -3069,7 +3069,7 @@ static struct decoder_info {
{{0, 0}, dec_null}
};
-static unsigned int crisv32_decoder(DisasContext *dc)
+static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
{
int insn_len = 2;
int i;
@@ -3078,7 +3078,7 @@ static unsigned int crisv32_decoder(DisasContext *dc)
tcg_gen_debug_insn_start(dc->pc);
/* Load a halfword onto the instruction register. */
- dc->ir = cris_fetch(dc, dc->pc, 2, 0);
+ dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
/* Now decode it. */
dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
@@ -3092,7 +3092,7 @@ static unsigned int crisv32_decoder(DisasContext *dc)
for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
{
- insn_len = decinfo[i].dec(dc);
+ insn_len = decinfo[i].dec(env, dc);
break;
}
}
@@ -3286,7 +3286,7 @@ gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb,
gen_io_start();
dc->clear_x = 1;
- insn_len = dc->decoder(dc);
+ insn_len = dc->decoder(env, dc);
dc->ppc = dc->pc;
dc->pc += insn_len;
if (dc->clear_x)
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 9a39c6a..d2cca89 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -164,8 +164,8 @@ static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size)
return insn_len;
}
-static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize,
- TCGv dst)
+static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc,
+ int s_ext, int memsize, TCGv dst)
{
unsigned int rs;
uint32_t imm;
@@ -182,17 +182,17 @@ static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize,
if (memsize != 4) {
if (s_ext) {
if (memsize == 1)
- imm = ldsb_code(dc->pc + 2);
+ imm = cpu_ldsb_code(env, dc->pc + 2);
else
- imm = ldsw_code(dc->pc + 2);
+ imm = cpu_ldsw_code(env, dc->pc + 2);
} else {
if (memsize == 1)
- imm = ldub_code(dc->pc + 2);
+ imm = cpu_ldub_code(env, dc->pc + 2);
else
- imm = lduw_code(dc->pc + 2);
+ imm = cpu_lduw_code(env, dc->pc + 2);
}
} else
- imm = ldl_code(dc->pc + 2);
+ imm = cpu_ldl_code(env, dc->pc + 2);
tcg_gen_movi_tl(dst, imm);
@@ -752,7 +752,8 @@ static unsigned int dec10_reg(DisasContext *dc)
return insn_len;
}
-static unsigned int dec10_ind_move_m_r(DisasContext *dc, unsigned int size)
+static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc,
+ unsigned int size)
{
unsigned int insn_len = 2;
TCGv t;
@@ -762,7 +763,7 @@ static unsigned int dec10_ind_move_m_r(DisasContext *dc, unsigned int size)
cris_cc_mask(dc, CC_MASK_NZVC);
t = tcg_temp_new();
- insn_len += dec10_prep_move_m(dc, 0, size, t);
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size);
if (dc->dst == 15) {
tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
@@ -789,7 +790,7 @@ static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size)
return insn_len;
}
-static unsigned int dec10_ind_move_m_pr(DisasContext *dc)
+static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc)
{
unsigned int insn_len = 2, rd = dc->dst;
TCGv t, addr;
@@ -799,7 +800,7 @@ static unsigned int dec10_ind_move_m_pr(DisasContext *dc)
addr = tcg_temp_new();
t = tcg_temp_new();
- insn_len += dec10_prep_move_m(dc, 0, 4, t);
+ insn_len += dec10_prep_move_m(env, dc, 0, 4, t);
if (rd == 15) {
tcg_gen_mov_tl(env_btarget, t);
cris_prepare_jmp(dc, JMP_INDIRECT);
@@ -899,14 +900,15 @@ static void dec10_movem_m_r(DisasContext *dc)
tcg_temp_free(t0);
}
-static int dec10_ind_alu(DisasContext *dc, int op, unsigned int size)
+static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc,
+ int op, unsigned int size)
{
int insn_len = 0;
int rd = dc->dst;
TCGv t[2];
cris_alu_m_alloc_temps(t);
- insn_len += dec10_prep_move_m(dc, 0, size, t[0]);
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size);
if (dc->dst == 15) {
tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
@@ -920,14 +922,15 @@ static int dec10_ind_alu(DisasContext *dc, int op, unsigned int size)
return insn_len;
}
-static int dec10_ind_bound(DisasContext *dc, unsigned int size)
+static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc,
+ unsigned int size)
{
int insn_len = 0;
int rd = dc->dst;
TCGv t;
t = tcg_temp_local_new();
- insn_len += dec10_prep_move_m(dc, 0, size, t);
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t);
cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4);
if (dc->dst == 15) {
tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
@@ -940,7 +943,7 @@ static int dec10_ind_bound(DisasContext *dc, unsigned int size)
return insn_len;
}
-static int dec10_alux_m(DisasContext *dc, int op)
+static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op)
{
unsigned int size = (dc->size & 1) ? 2 : 1;
unsigned int sx = !!(dc->size & 2);
@@ -953,7 +956,7 @@ static int dec10_alux_m(DisasContext *dc, int op)
t = tcg_temp_new();
cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_prep_move_m(dc, sx, size, t);
+ insn_len += dec10_prep_move_m(env, dc, sx, size, t);
cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4);
if (dc->dst == 15) {
tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
@@ -966,7 +969,7 @@ static int dec10_alux_m(DisasContext *dc, int op)
return insn_len;
}
-static int dec10_dip(DisasContext *dc)
+static int dec10_dip(CPUCRISState *env, DisasContext *dc)
{
int insn_len = 2;
uint32_t imm;
@@ -974,7 +977,7 @@ static int dec10_dip(DisasContext *dc)
LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
dc->pc, dc->opcode, dc->src, dc->dst);
if (dc->src == 15) {
- imm = ldl_code(dc->pc + 2);
+ imm = cpu_ldl_code(env, dc->pc + 2);
tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
if (dc->postinc)
insn_len += 4;
@@ -989,7 +992,7 @@ static int dec10_dip(DisasContext *dc)
return insn_len;
}
-static int dec10_bdap_m(DisasContext *dc, int size)
+static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size)
{
int insn_len = 2;
int rd = dc->dst;
@@ -1014,13 +1017,13 @@ static int dec10_bdap_m(DisasContext *dc, int size)
}
#endif
/* Now the rest of the modes are truly indirect. */
- insn_len += dec10_prep_move_m(dc, 1, size, cpu_PR[PR_PREFIX]);
+ insn_len += dec10_prep_move_m(env, dc, 1, size, cpu_PR[PR_PREFIX]);
tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]);
cris_set_prefix(dc);
return insn_len;
}
-static unsigned int dec10_ind(DisasContext *dc)
+static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
{
unsigned int insn_len = 2;
unsigned int size = dec10_size(dc->size);
@@ -1031,7 +1034,7 @@ static unsigned int dec10_ind(DisasContext *dc)
if (dc->size != 3) {
switch (dc->opcode) {
case CRISV10_IND_MOVE_M_R:
- return dec10_ind_move_m_r(dc, size);
+ return dec10_ind_move_m_r(env, dc, size);
break;
case CRISV10_IND_MOVE_R_M:
return dec10_ind_move_r_m(dc, size);
@@ -1039,7 +1042,7 @@ static unsigned int dec10_ind(DisasContext *dc)
case CRISV10_IND_CMP:
LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_alu(dc, CC_OP_CMP, size);
+ insn_len += dec10_ind_alu(env, dc, CC_OP_CMP, size);
break;
case CRISV10_IND_TEST:
LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst);
@@ -1047,7 +1050,7 @@ static unsigned int dec10_ind(DisasContext *dc)
cris_evaluate_flags(dc);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu_m_alloc_temps(t);
- insn_len += dec10_prep_move_m(dc, 0, size, t[0]);
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
t[0], tcg_const_tl(0), size);
@@ -1056,39 +1059,39 @@ static unsigned int dec10_ind(DisasContext *dc)
case CRISV10_IND_ADD:
LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_alu(dc, CC_OP_ADD, size);
+ insn_len += dec10_ind_alu(env, dc, CC_OP_ADD, size);
break;
case CRISV10_IND_SUB:
LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_alu(dc, CC_OP_SUB, size);
+ insn_len += dec10_ind_alu(env, dc, CC_OP_SUB, size);
break;
case CRISV10_IND_BOUND:
LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_bound(dc, size);
+ insn_len += dec10_ind_bound(env, dc, size);
break;
case CRISV10_IND_AND:
LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_alu(dc, CC_OP_AND, size);
+ insn_len += dec10_ind_alu(env, dc, CC_OP_AND, size);
break;
case CRISV10_IND_OR:
LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_alu(dc, CC_OP_OR, size);
+ insn_len += dec10_ind_alu(env, dc, CC_OP_OR, size);
break;
case CRISV10_IND_MOVX:
- insn_len = dec10_alux_m(dc, CC_OP_MOVE);
+ insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
break;
case CRISV10_IND_ADDX:
- insn_len = dec10_alux_m(dc, CC_OP_ADD);
+ insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
break;
case CRISV10_IND_SUBX:
- insn_len = dec10_alux_m(dc, CC_OP_SUB);
+ insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
break;
case CRISV10_IND_CMPX:
- insn_len = dec10_alux_m(dc, CC_OP_CMP);
+ insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
break;
case CRISV10_IND_MUL:
/* This is a reg insn coded in the mem indir space. */
@@ -1097,7 +1100,7 @@ static unsigned int dec10_ind(DisasContext *dc)
dec10_reg_mul(dc, size, dc->ir & (1 << 10));
break;
case CRISV10_IND_BDAP_M:
- insn_len = dec10_bdap_m(dc, size);
+ insn_len = dec10_bdap_m(env, dc, size);
break;
default:
LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
@@ -1110,7 +1113,7 @@ static unsigned int dec10_ind(DisasContext *dc)
switch (dc->opcode) {
case CRISV10_IND_MOVE_M_SPR:
- insn_len = dec10_ind_move_m_pr(dc);
+ insn_len = dec10_ind_move_m_pr(env, dc);
break;
case CRISV10_IND_MOVE_SPR_M:
insn_len = dec10_ind_move_pr_m(dc);
@@ -1119,7 +1122,7 @@ static unsigned int dec10_ind(DisasContext *dc)
if (dc->src == 15) {
LOG_DIS("jump.%d %d r%d r%d direct\n", size,
dc->opcode, dc->src, dc->dst);
- imm = ldl_code(dc->pc + 2);
+ imm = cpu_ldl_code(env, dc->pc + 2);
if (dc->mode == CRISV10_MODE_AUTOINC)
insn_len += size;
@@ -1168,24 +1171,24 @@ static unsigned int dec10_ind(DisasContext *dc)
dc->delayed_branch--; /* v10 has no dslot here. */
break;
case CRISV10_IND_MOVX:
- insn_len = dec10_alux_m(dc, CC_OP_MOVE);
+ insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
break;
case CRISV10_IND_ADDX:
- insn_len = dec10_alux_m(dc, CC_OP_ADD);
+ insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
break;
case CRISV10_IND_SUBX:
- insn_len = dec10_alux_m(dc, CC_OP_SUB);
+ insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
break;
case CRISV10_IND_CMPX:
- insn_len = dec10_alux_m(dc, CC_OP_CMP);
+ insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
break;
case CRISV10_IND_DIP:
- insn_len = dec10_dip(dc);
+ insn_len = dec10_dip(env, dc);
break;
case CRISV10_IND_BCC_M:
cris_cc_mask(dc, 0);
- imm = ldsw_code(dc->pc + 2);
+ imm = cpu_ldsw_code(env, dc->pc + 2);
simm = (int16_t)imm;
simm += 4;
@@ -1202,7 +1205,7 @@ static unsigned int dec10_ind(DisasContext *dc)
return insn_len;
}
-static unsigned int crisv10_decoder(DisasContext *dc)
+static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
{
unsigned int insn_len = 2;
@@ -1210,7 +1213,7 @@ static unsigned int crisv10_decoder(DisasContext *dc)
tcg_gen_debug_insn_start(dc->pc);
/* Load a halfword onto the instruction register. */
- dc->ir = lduw_code(dc->pc);
+ dc->ir = cpu_lduw_code(env, dc->pc);
/* Now decode it. */
dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
@@ -1235,7 +1238,7 @@ static unsigned int crisv10_decoder(DisasContext *dc)
break;
case CRISV10_MODE_AUTOINC:
case CRISV10_MODE_INDIRECT:
- insn_len = dec10_ind(dc);
+ insn_len = dec10_ind(env, dc);
break;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 18/21] target-cris: switch to AREG0 free mode
2012-09-07 14:18 ` Aurelien Jarno
@ 2012-09-07 14:40 ` Edgar E. Iglesias
2012-09-07 14:46 ` Aurelien Jarno
2012-09-08 8:35 ` Blue Swirl
1 sibling, 1 reply; 64+ messages in thread
From: Edgar E. Iglesias @ 2012-09-07 14:40 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: Blue Swirl, qemu-devel
On Fri, Sep 07, 2012 at 04:18:41PM +0200, Aurelien Jarno wrote:
> On Sun, Sep 02, 2012 at 05:33:47PM +0000, Blue Swirl wrote:
> > Add an explicit CPUState parameter instead of relying on AREG0
> > and switch to AREG0 free mode.
> >
> > Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> > ---
> > configure | 2 +-
> > target-cris/Makefile.objs | 2 -
> > target-cris/helper.c | 4 +-
> > target-cris/helper.h | 34 ++++++++--------
> > target-cris/op_helper.c | 89 +++++++++++++++++++++----------------------
> > target-cris/translate.c | 50 ++++++++++++-----------
> > target-cris/translate_v10.c | 22 +++++-----
> > 7 files changed, 101 insertions(+), 102 deletions(-)
> >
> > diff --git a/configure b/configure
> > index e464d2f..d760e07 100755
> > --- a/configure
> > +++ b/configure
> > @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
> >
> >
> > case "$target_arch2" in
> > - alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> > + alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> > echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
> > ;;
> > esac
> > diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
> > index 4b09e8c..afb87bc 100644
> > --- a/target-cris/Makefile.objs
> > +++ b/target-cris/Makefile.objs
> > @@ -1,4 +1,2 @@
> > obj-y += translate.o op_helper.o helper.o cpu.o
> > obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
> > -
> > -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> > diff --git a/target-cris/helper.c b/target-cris/helper.c
> > index bfbc29e..1bdb7e2 100644
> > --- a/target-cris/helper.c
> > +++ b/target-cris/helper.c
> > @@ -151,7 +151,7 @@ static void do_interruptv10(CPUCRISState *env)
> > }
> >
> > /* Now that we are in kernel mode, load the handlers address. */
> > - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
> > + env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
> > env->locked_irq = 1;
> > env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
> >
> > @@ -233,7 +233,7 @@ void do_interrupt(CPUCRISState *env)
> > /* Now that we are in kernel mode, load the handlers address.
> > This load may not fault, real hw leaves that behaviour as
> > undefined. */
> > - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
> > + env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
> >
> > /* Clear the excption_index to avoid spurios hw_aborts for recursive
> > bus faults. */
> > diff --git a/target-cris/helper.h b/target-cris/helper.h
> > index 093063a..b575524 100644
> > --- a/target-cris/helper.h
> > +++ b/target-cris/helper.h
> > @@ -1,26 +1,26 @@
> > #include "def-helper.h"
> >
> > -DEF_HELPER_1(raise_exception, void, i32)
> > -DEF_HELPER_1(tlb_flush_pid, void, i32)
> > -DEF_HELPER_1(spc_write, void, i32)
> > +DEF_HELPER_2(raise_exception, void, env, i32)
> > +DEF_HELPER_2(tlb_flush_pid, void, env, i32)
> > +DEF_HELPER_2(spc_write, void, env, i32)
> > DEF_HELPER_3(dump, void, i32, i32, i32)
> > -DEF_HELPER_0(rfe, void);
> > -DEF_HELPER_0(rfn, void);
> > +DEF_HELPER_1(rfe, void, env);
> > +DEF_HELPER_1(rfn, void, env);
> >
> > -DEF_HELPER_2(movl_sreg_reg, void, i32, i32)
> > -DEF_HELPER_2(movl_reg_sreg, void, i32, i32)
> > +DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32)
> > +DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32)
> >
> > DEF_HELPER_FLAGS_1(lz, TCG_CALL_PURE, i32, i32);
> > -DEF_HELPER_FLAGS_3(btst, TCG_CALL_PURE, i32, i32, i32, i32);
> > +DEF_HELPER_FLAGS_4(btst, TCG_CALL_PURE, i32, env, i32, i32, i32);
> >
> > -DEF_HELPER_FLAGS_3(evaluate_flags_muls, TCG_CALL_PURE, i32, i32, i32, i32)
> > -DEF_HELPER_FLAGS_3(evaluate_flags_mulu, TCG_CALL_PURE, i32, i32, i32, i32)
> > -DEF_HELPER_FLAGS_4(evaluate_flags_mcp, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> > -DEF_HELPER_FLAGS_4(evaluate_flags_alu_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> > -DEF_HELPER_FLAGS_4(evaluate_flags_sub_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> > -DEF_HELPER_FLAGS_2(evaluate_flags_move_4, TCG_CALL_PURE, i32, i32, i32)
> > -DEF_HELPER_FLAGS_2(evaluate_flags_move_2, TCG_CALL_PURE, i32, i32, i32)
> > -DEF_HELPER_0(evaluate_flags, void)
> > -DEF_HELPER_0(top_evaluate_flags, void)
> > +DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_PURE, i32, env, i32, i32, i32)
> > +DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_PURE, i32, env, i32, i32, i32)
> > +DEF_HELPER_FLAGS_5(evaluate_flags_mcp, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> > +DEF_HELPER_FLAGS_5(evaluate_flags_alu_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> > +DEF_HELPER_FLAGS_5(evaluate_flags_sub_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> > +DEF_HELPER_FLAGS_3(evaluate_flags_move_4, TCG_CALL_PURE, i32, env, i32, i32)
> > +DEF_HELPER_FLAGS_3(evaluate_flags_move_2, TCG_CALL_PURE, i32, env, i32, i32)
> > +DEF_HELPER_1(evaluate_flags, void, env)
> > +DEF_HELPER_1(top_evaluate_flags, void, env)
> >
> > #include "def-helper.h"
> > diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> > index ac7c98c..5cce3e7 100644
> > --- a/target-cris/op_helper.c
> > +++ b/target-cris/op_helper.c
> > @@ -19,7 +19,6 @@
> > */
> >
> > #include "cpu.h"
> > -#include "dyngen-exec.h"
> > #include "mmu.h"
> > #include "helper.h"
> > #include "host-utils.h"
> > @@ -55,17 +54,12 @@
> > /* Try to fill the TLB and return an exception if error. If retaddr is
> > NULL, it means that the function was called in C code (i.e. not
> > from generated code or from helper.c) */
> > -/* XXX: fix it to restore all registers */
> > -void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
> > +void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
> > uintptr_t retaddr)
> > {
> > TranslationBlock *tb;
> > - CPUCRISState *saved_env;
> > int ret;
> >
> > - saved_env = env;
> > - env = env1;
> > -
> > D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
> > env->pc, env->debug1, (void *)retaddr);
> > ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
> > @@ -79,23 +73,22 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
> > cpu_restore_state(tb, env, retaddr);
> >
> > /* Evaluate flags after retranslation. */
> > - helper_top_evaluate_flags();
> > + helper_top_evaluate_flags(env);
> > }
> > }
> > cpu_loop_exit(env);
> > }
> > - env = saved_env;
> > }
> >
> > #endif
> >
> > -void helper_raise_exception(uint32_t index)
> > +void helper_raise_exception(CPUCRISState *env, uint32_t index)
> > {
> > env->exception_index = index;
> > cpu_loop_exit(env);
> > }
> >
> > -void helper_tlb_flush_pid(uint32_t pid)
> > +void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
> > {
> > #if !defined(CONFIG_USER_ONLY)
> > pid &= 0xff;
> > @@ -104,7 +97,7 @@ void helper_tlb_flush_pid(uint32_t pid)
> > #endif
> > }
> >
> > -void helper_spc_write(uint32_t new_spc)
> > +void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
> > {
> > #if !defined(CONFIG_USER_ONLY)
> > tlb_flush_page(env, env->pregs[PR_SPC]);
> > @@ -121,7 +114,7 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
> > #define EXTRACT_FIELD(src, start, end) \
> > (((src) >> start) & ((1 << (end - start + 1)) - 1))
> >
> > -void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
> > +void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
> > {
> > uint32_t srs;
> > srs = env->pregs[PR_SRS];
> > @@ -171,7 +164,7 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
> > #endif
> > }
> >
> > -void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
> > +void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
> > {
> > uint32_t srs;
> > env->pregs[PR_SRS] &= 3;
> > @@ -216,7 +209,7 @@ static void cris_ccs_rshift(CPUCRISState *env)
> > env->pregs[PR_CCS] = ccs;
> > }
> >
> > -void helper_rfe(void)
> > +void helper_rfe(CPUCRISState *env)
> > {
> > int rflag = env->pregs[PR_CCS] & R_FLAG;
> >
> > @@ -232,7 +225,7 @@ void helper_rfe(void)
> > env->pregs[PR_CCS] |= P_FLAG;
> > }
> >
> > -void helper_rfn(void)
> > +void helper_rfn(CPUCRISState *env)
> > {
> > int rflag = env->pregs[PR_CCS] & R_FLAG;
> >
> > @@ -256,7 +249,7 @@ uint32_t helper_lz(uint32_t t0)
> > return clz32(t0);
> > }
> >
> > -uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
> > +uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
> > {
> > /* FIXME: clean this up. */
> >
> > @@ -284,7 +277,8 @@ uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
> > return ccs;
> > }
> >
> > -static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
> > +static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
> > + uint32_t flags, uint32_t ccs)
> > {
> > unsigned int x, z, mask;
> >
> > @@ -303,7 +297,8 @@ static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
> > return ccs;
> > }
> >
> > -uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
> > +uint32_t helper_evaluate_flags_muls(CPUCRISState *env, uint32_t ccs,
> > + uint32_t res, uint32_t mof)
> > {
> > uint32_t flags = 0;
> > int64_t tmp;
> > @@ -321,10 +316,11 @@ uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
> > if ((dneg && mof != -1)
> > || (!dneg && mof != 0))
> > flags |= V_FLAG;
> > - return evaluate_flags_writeback(flags, ccs);
> > + return evaluate_flags_writeback(env, flags, ccs);
> > }
> >
> > -uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
> > +uint32_t helper_evaluate_flags_mulu(CPUCRISState *env, uint32_t ccs,
> > + uint32_t res, uint32_t mof)
> > {
> > uint32_t flags = 0;
> > uint64_t tmp;
> > @@ -339,10 +335,10 @@ uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
> > if (mof)
> > flags |= V_FLAG;
> >
> > - return evaluate_flags_writeback(flags, ccs);
> > + return evaluate_flags_writeback(env, flags, ccs);
> > }
> >
> > -uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
> > +uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
> > uint32_t src, uint32_t dst, uint32_t res)
> > {
> > uint32_t flags = 0;
> > @@ -368,10 +364,10 @@ uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
> > flags |= R_FLAG;
> > }
> >
> > - return evaluate_flags_writeback(flags, ccs);
> > + return evaluate_flags_writeback(env, flags, ccs);
> > }
> >
> > -uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
> > +uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
> > uint32_t src, uint32_t dst, uint32_t res)
> > {
> > uint32_t flags = 0;
> > @@ -397,10 +393,10 @@ uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
> > flags |= C_FLAG;
> > }
> >
> > - return evaluate_flags_writeback(flags, ccs);
> > + return evaluate_flags_writeback(env, flags, ccs);
> > }
> >
> > -uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
> > +uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
> > uint32_t src, uint32_t dst, uint32_t res)
> > {
> > uint32_t flags = 0;
> > @@ -427,10 +423,11 @@ uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
> > }
> >
> > flags ^= C_FLAG;
> > - return evaluate_flags_writeback(flags, ccs);
> > + return evaluate_flags_writeback(env, flags, ccs);
> > }
> >
> > -uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
> > +uint32_t helper_evaluate_flags_move_4(CPUCRISState *env, uint32_t ccs,
> > + uint32_t res)
> > {
> > uint32_t flags = 0;
> >
> > @@ -439,9 +436,10 @@ uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
> > else if (res == 0L)
> > flags |= Z_FLAG;
> >
> > - return evaluate_flags_writeback(flags, ccs);
> > + return evaluate_flags_writeback(env, flags, ccs);
> > }
> > -uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
> > +uint32_t helper_evaluate_flags_move_2(CPUCRISState *env, uint32_t ccs,
> > + uint32_t res)
> > {
> > uint32_t flags = 0;
> >
> > @@ -450,12 +448,12 @@ uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
> > else if (res == 0)
> > flags |= Z_FLAG;
> >
> > - return evaluate_flags_writeback(flags, ccs);
> > + return evaluate_flags_writeback(env, flags, ccs);
> > }
> >
> > /* TODO: This is expensive. We could split things up and only evaluate part of
> > CCR on a need to know basis. For now, we simply re-evaluate everything. */
> > -void helper_evaluate_flags(void)
> > +void helper_evaluate_flags(CPUCRISState *env)
> > {
> > uint32_t src, dst, res;
> > uint32_t flags = 0;
> > @@ -571,25 +569,26 @@ void helper_evaluate_flags(void)
> > if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
> > flags ^= C_FLAG;
> >
> > - env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
> > + env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
> > + env->pregs[PR_CCS]);
> > }
> >
> > -void helper_top_evaluate_flags(void)
> > +void helper_top_evaluate_flags(CPUCRISState *env)
> > {
> > switch (env->cc_op)
> > {
> > case CC_OP_MCP:
> > - env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
> > + env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
> > env->pregs[PR_CCS], env->cc_src,
> > env->cc_dest, env->cc_result);
> > break;
> > case CC_OP_MULS:
> > - env->pregs[PR_CCS] = helper_evaluate_flags_muls(
> > + env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
> > env->pregs[PR_CCS], env->cc_result,
> > env->pregs[PR_MOF]);
> > break;
> > case CC_OP_MULU:
> > - env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
> > + env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
> > env->pregs[PR_CCS], env->cc_result,
> > env->pregs[PR_MOF]);
> > break;
> > @@ -604,18 +603,18 @@ void helper_top_evaluate_flags(void)
> > {
> > case 4:
> > env->pregs[PR_CCS] =
> > - helper_evaluate_flags_move_4(
> > + helper_evaluate_flags_move_4(env,
> > env->pregs[PR_CCS],
> > env->cc_result);
> > break;
> > case 2:
> > env->pregs[PR_CCS] =
> > - helper_evaluate_flags_move_2(
> > + helper_evaluate_flags_move_2(env,
> > env->pregs[PR_CCS],
> > env->cc_result);
> > break;
> > default:
> > - helper_evaluate_flags();
> > + helper_evaluate_flags(env);
> > break;
> > }
> > break;
> > @@ -626,12 +625,12 @@ void helper_top_evaluate_flags(void)
> > case CC_OP_CMP:
> > if (env->cc_size == 4)
> > env->pregs[PR_CCS] =
> > - helper_evaluate_flags_sub_4(
> > + helper_evaluate_flags_sub_4(env,
> > env->pregs[PR_CCS],
> > env->cc_src, env->cc_dest,
> > env->cc_result);
> > else
> > - helper_evaluate_flags();
> > + helper_evaluate_flags(env);
> > break;
> > default:
> > {
> > @@ -639,13 +638,13 @@ void helper_top_evaluate_flags(void)
> > {
> > case 4:
> > env->pregs[PR_CCS] =
> > - helper_evaluate_flags_alu_4(
> > + helper_evaluate_flags_alu_4(env,
> > env->pregs[PR_CCS],
> > env->cc_src, env->cc_dest,
> > env->cc_result);
> > break;
> > default:
> > - helper_evaluate_flags();
> > + helper_evaluate_flags(env);
> > break;
> > }
> > }
> > diff --git a/target-cris/translate.c b/target-cris/translate.c
> > index 1ad9ec7..5e4f7f5 100644
> > --- a/target-cris/translate.c
> > +++ b/target-cris/translate.c
> > @@ -211,9 +211,9 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
> > tcg_gen_andi_tl(cpu_PR[r], tn, 3);
> > else {
> > if (r == PR_PID)
> > - gen_helper_tlb_flush_pid(tn);
> > + gen_helper_tlb_flush_pid(cpu_env, tn);
> > if (dc->tb_flags & S_FLAG && r == PR_SPC)
> > - gen_helper_spc_write(tn);
> > + gen_helper_spc_write(cpu_env, tn);
> > else if (r == PR_CCS)
> > dc->cpustate_changed = 1;
> > tcg_gen_mov_tl(cpu_PR[r], tn);
> > @@ -241,24 +241,24 @@ static int cris_fetch(DisasContext *dc, uint32_t addr,
> > switch (size) {
> > case 4:
> > {
> > - r = ldl_code(addr);
> > + r = cpu_ldl_code(cpu_single_env, addr);
> > break;
> > }
> > case 2:
> > {
> > if (sign) {
> > - r = ldsw_code(addr);
> > + r = cpu_ldsw_code(cpu_single_env, addr);
> > } else {
> > - r = lduw_code(addr);
> > + r = cpu_lduw_code(cpu_single_env, addr);
> > }
> > break;
> > }
> > case 1:
> > {
> > if (sign) {
> > - r = ldsb_code(addr);
> > + r = cpu_ldsb_code(cpu_single_env, addr);
> > } else {
> > - r = ldub_code(addr);
> > + r = cpu_ldub_code(cpu_single_env, addr);
> > }
> > break;
> > }
> > @@ -278,7 +278,7 @@ static void cris_lock_irq(DisasContext *dc)
> > static inline void t_gen_raise_exception(uint32_t index)
> > {
> > TCGv_i32 tmp = tcg_const_i32(index);
> > - gen_helper_raise_exception(tmp);
> > + gen_helper_raise_exception(cpu_env, tmp);
> > tcg_temp_free_i32(tmp);
> > }
> >
> > @@ -624,17 +624,17 @@ static void cris_evaluate_flags(DisasContext *dc)
> > switch (dc->cc_op)
> > {
> > case CC_OP_MCP:
> > - gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
> > + gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
> > cpu_PR[PR_CCS], cc_src,
> > cc_dest, cc_result);
> > break;
> > case CC_OP_MULS:
> > - gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
> > + gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
> > cpu_PR[PR_CCS], cc_result,
> > cpu_PR[PR_MOF]);
> > break;
> > case CC_OP_MULU:
> > - gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
> > + gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
> > cpu_PR[PR_CCS], cc_result,
> > cpu_PR[PR_MOF]);
> > break;
> > @@ -648,15 +648,15 @@ static void cris_evaluate_flags(DisasContext *dc)
> > switch (dc->cc_size)
> > {
> > case 4:
> > - gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
> > + gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], cpu_env,
> > cpu_PR[PR_CCS], cc_result);
> > break;
> > case 2:
> > - gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
> > + gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], cpu_env,
> > cpu_PR[PR_CCS], cc_result);
> > break;
> > default:
> > - gen_helper_evaluate_flags();
> > + gen_helper_evaluate_flags(cpu_env);
> > break;
> > }
> > break;
> > @@ -666,21 +666,21 @@ static void cris_evaluate_flags(DisasContext *dc)
> > case CC_OP_SUB:
> > case CC_OP_CMP:
> > if (dc->cc_size == 4)
> > - gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
> > + gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
> > cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
> > else
> > - gen_helper_evaluate_flags();
> > + gen_helper_evaluate_flags(cpu_env);
> >
> > break;
> > default:
> > switch (dc->cc_size)
> > {
> > case 4:
> > - gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
> > + gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
> > cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
> > break;
> > default:
> > - gen_helper_evaluate_flags();
> > + gen_helper_evaluate_flags(cpu_env);
> > break;
> > }
> > break;
> > @@ -1475,7 +1475,7 @@ static int dec_btstq(DisasContext *dc)
> >
> > cris_cc_mask(dc, CC_MASK_NZ);
> > cris_evaluate_flags(dc);
> > - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
> > + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
> > tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
> > cris_alu(dc, CC_OP_MOVE,
> > cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
> > @@ -1925,7 +1925,7 @@ static int dec_btst_r(DisasContext *dc)
> > dc->op1, dc->op2);
> > cris_cc_mask(dc, CC_MASK_NZ);
> > cris_evaluate_flags(dc);
> > - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
> > + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
> > cpu_R[dc->op1], cpu_PR[PR_CCS]);
> > cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
> > cpu_R[dc->op2], cpu_R[dc->op2], 4);
> > @@ -2135,14 +2135,16 @@ static int dec_move_rs(DisasContext *dc)
> > {
> > LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
> > cris_cc_mask(dc, 0);
> > - gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
> > + gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
> > + tcg_const_tl(dc->op1));
> > return 2;
> > }
> > static int dec_move_sr(DisasContext *dc)
> > {
> > LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
> > cris_cc_mask(dc, 0);
> > - gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
> > + gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
> > + tcg_const_tl(dc->op2));
> > return 2;
> > }
> >
> > @@ -2906,14 +2908,14 @@ static int dec_rfe_etc(DisasContext *dc)
> > /* rfe. */
> > LOG_DIS("rfe\n");
> > cris_evaluate_flags(dc);
> > - gen_helper_rfe();
> > + gen_helper_rfe(cpu_env);
> > dc->is_jmp = DISAS_UPDATE;
> > break;
> > case 5:
> > /* rfn. */
> > LOG_DIS("rfn\n");
> > cris_evaluate_flags(dc);
> > - gen_helper_rfn();
> > + gen_helper_rfn(cpu_env);
> > dc->is_jmp = DISAS_UPDATE;
> > break;
> > case 6:
>
> Similarly to what I reported for the microblaze and sh4 target, I think
> we should not start using cpu_single_env (a global variable) to replace
> env (a global variable stored in a register).
>
> It is possible to pass env through the subroutine, though it is more
> complicated there than for other targets. I have therefore done the work
> and I have attached the two resulting patches to this mail.
Hi Aurelien!
I agree with your comment and change. The indentation looks a bit odd
here though. The CRISv32 port used tabs when written but some patches
have made it in that used space, so it's become a bit of a mess. Maybe
it's time to convert it to the QEMU codingstyle?
>From my point of view, I think we should either keep the tabs or change
the whole file for 4 space indent.
I've got nothing against applying your patch as is and then on top of that
the mechanical untabification, to avoid extra work on your side.
Cheers,
Edgar
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 18/21] target-cris: switch to AREG0 free mode
2012-09-07 14:40 ` Edgar E. Iglesias
@ 2012-09-07 14:46 ` Aurelien Jarno
2012-09-08 3:34 ` Edgar E. Iglesias
0 siblings, 1 reply; 64+ messages in thread
From: Aurelien Jarno @ 2012-09-07 14:46 UTC (permalink / raw)
To: Edgar E. Iglesias; +Cc: Blue Swirl, qemu-devel
On Fri, Sep 07, 2012 at 04:40:03PM +0200, Edgar E. Iglesias wrote:
> On Fri, Sep 07, 2012 at 04:18:41PM +0200, Aurelien Jarno wrote:
> > On Sun, Sep 02, 2012 at 05:33:47PM +0000, Blue Swirl wrote:
> > > Add an explicit CPUState parameter instead of relying on AREG0
> > > and switch to AREG0 free mode.
> > >
> > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> > > ---
> > > configure | 2 +-
> > > target-cris/Makefile.objs | 2 -
> > > target-cris/helper.c | 4 +-
> > > target-cris/helper.h | 34 ++++++++--------
> > > target-cris/op_helper.c | 89 +++++++++++++++++++++----------------------
> > > target-cris/translate.c | 50 ++++++++++++-----------
> > > target-cris/translate_v10.c | 22 +++++-----
> > > 7 files changed, 101 insertions(+), 102 deletions(-)
> > >
> > > diff --git a/configure b/configure
> > > index e464d2f..d760e07 100755
> > > --- a/configure
> > > +++ b/configure
> > > @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
> > >
> > >
> > > case "$target_arch2" in
> > > - alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> > > + alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> > > echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
> > > ;;
> > > esac
> > > diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
> > > index 4b09e8c..afb87bc 100644
> > > --- a/target-cris/Makefile.objs
> > > +++ b/target-cris/Makefile.objs
> > > @@ -1,4 +1,2 @@
> > > obj-y += translate.o op_helper.o helper.o cpu.o
> > > obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
> > > -
> > > -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> > > diff --git a/target-cris/helper.c b/target-cris/helper.c
> > > index bfbc29e..1bdb7e2 100644
> > > --- a/target-cris/helper.c
> > > +++ b/target-cris/helper.c
> > > @@ -151,7 +151,7 @@ static void do_interruptv10(CPUCRISState *env)
> > > }
> > >
> > > /* Now that we are in kernel mode, load the handlers address. */
> > > - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
> > > + env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
> > > env->locked_irq = 1;
> > > env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
> > >
> > > @@ -233,7 +233,7 @@ void do_interrupt(CPUCRISState *env)
> > > /* Now that we are in kernel mode, load the handlers address.
> > > This load may not fault, real hw leaves that behaviour as
> > > undefined. */
> > > - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
> > > + env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
> > >
> > > /* Clear the excption_index to avoid spurios hw_aborts for recursive
> > > bus faults. */
> > > diff --git a/target-cris/helper.h b/target-cris/helper.h
> > > index 093063a..b575524 100644
> > > --- a/target-cris/helper.h
> > > +++ b/target-cris/helper.h
> > > @@ -1,26 +1,26 @@
> > > #include "def-helper.h"
> > >
> > > -DEF_HELPER_1(raise_exception, void, i32)
> > > -DEF_HELPER_1(tlb_flush_pid, void, i32)
> > > -DEF_HELPER_1(spc_write, void, i32)
> > > +DEF_HELPER_2(raise_exception, void, env, i32)
> > > +DEF_HELPER_2(tlb_flush_pid, void, env, i32)
> > > +DEF_HELPER_2(spc_write, void, env, i32)
> > > DEF_HELPER_3(dump, void, i32, i32, i32)
> > > -DEF_HELPER_0(rfe, void);
> > > -DEF_HELPER_0(rfn, void);
> > > +DEF_HELPER_1(rfe, void, env);
> > > +DEF_HELPER_1(rfn, void, env);
> > >
> > > -DEF_HELPER_2(movl_sreg_reg, void, i32, i32)
> > > -DEF_HELPER_2(movl_reg_sreg, void, i32, i32)
> > > +DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32)
> > > +DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32)
> > >
> > > DEF_HELPER_FLAGS_1(lz, TCG_CALL_PURE, i32, i32);
> > > -DEF_HELPER_FLAGS_3(btst, TCG_CALL_PURE, i32, i32, i32, i32);
> > > +DEF_HELPER_FLAGS_4(btst, TCG_CALL_PURE, i32, env, i32, i32, i32);
> > >
> > > -DEF_HELPER_FLAGS_3(evaluate_flags_muls, TCG_CALL_PURE, i32, i32, i32, i32)
> > > -DEF_HELPER_FLAGS_3(evaluate_flags_mulu, TCG_CALL_PURE, i32, i32, i32, i32)
> > > -DEF_HELPER_FLAGS_4(evaluate_flags_mcp, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> > > -DEF_HELPER_FLAGS_4(evaluate_flags_alu_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> > > -DEF_HELPER_FLAGS_4(evaluate_flags_sub_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> > > -DEF_HELPER_FLAGS_2(evaluate_flags_move_4, TCG_CALL_PURE, i32, i32, i32)
> > > -DEF_HELPER_FLAGS_2(evaluate_flags_move_2, TCG_CALL_PURE, i32, i32, i32)
> > > -DEF_HELPER_0(evaluate_flags, void)
> > > -DEF_HELPER_0(top_evaluate_flags, void)
> > > +DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_PURE, i32, env, i32, i32, i32)
> > > +DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_PURE, i32, env, i32, i32, i32)
> > > +DEF_HELPER_FLAGS_5(evaluate_flags_mcp, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> > > +DEF_HELPER_FLAGS_5(evaluate_flags_alu_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> > > +DEF_HELPER_FLAGS_5(evaluate_flags_sub_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> > > +DEF_HELPER_FLAGS_3(evaluate_flags_move_4, TCG_CALL_PURE, i32, env, i32, i32)
> > > +DEF_HELPER_FLAGS_3(evaluate_flags_move_2, TCG_CALL_PURE, i32, env, i32, i32)
> > > +DEF_HELPER_1(evaluate_flags, void, env)
> > > +DEF_HELPER_1(top_evaluate_flags, void, env)
> > >
> > > #include "def-helper.h"
> > > diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> > > index ac7c98c..5cce3e7 100644
> > > --- a/target-cris/op_helper.c
> > > +++ b/target-cris/op_helper.c
> > > @@ -19,7 +19,6 @@
> > > */
> > >
> > > #include "cpu.h"
> > > -#include "dyngen-exec.h"
> > > #include "mmu.h"
> > > #include "helper.h"
> > > #include "host-utils.h"
> > > @@ -55,17 +54,12 @@
> > > /* Try to fill the TLB and return an exception if error. If retaddr is
> > > NULL, it means that the function was called in C code (i.e. not
> > > from generated code or from helper.c) */
> > > -/* XXX: fix it to restore all registers */
> > > -void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
> > > +void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
> > > uintptr_t retaddr)
> > > {
> > > TranslationBlock *tb;
> > > - CPUCRISState *saved_env;
> > > int ret;
> > >
> > > - saved_env = env;
> > > - env = env1;
> > > -
> > > D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
> > > env->pc, env->debug1, (void *)retaddr);
> > > ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
> > > @@ -79,23 +73,22 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
> > > cpu_restore_state(tb, env, retaddr);
> > >
> > > /* Evaluate flags after retranslation. */
> > > - helper_top_evaluate_flags();
> > > + helper_top_evaluate_flags(env);
> > > }
> > > }
> > > cpu_loop_exit(env);
> > > }
> > > - env = saved_env;
> > > }
> > >
> > > #endif
> > >
> > > -void helper_raise_exception(uint32_t index)
> > > +void helper_raise_exception(CPUCRISState *env, uint32_t index)
> > > {
> > > env->exception_index = index;
> > > cpu_loop_exit(env);
> > > }
> > >
> > > -void helper_tlb_flush_pid(uint32_t pid)
> > > +void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
> > > {
> > > #if !defined(CONFIG_USER_ONLY)
> > > pid &= 0xff;
> > > @@ -104,7 +97,7 @@ void helper_tlb_flush_pid(uint32_t pid)
> > > #endif
> > > }
> > >
> > > -void helper_spc_write(uint32_t new_spc)
> > > +void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
> > > {
> > > #if !defined(CONFIG_USER_ONLY)
> > > tlb_flush_page(env, env->pregs[PR_SPC]);
> > > @@ -121,7 +114,7 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
> > > #define EXTRACT_FIELD(src, start, end) \
> > > (((src) >> start) & ((1 << (end - start + 1)) - 1))
> > >
> > > -void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
> > > +void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
> > > {
> > > uint32_t srs;
> > > srs = env->pregs[PR_SRS];
> > > @@ -171,7 +164,7 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
> > > #endif
> > > }
> > >
> > > -void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
> > > +void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
> > > {
> > > uint32_t srs;
> > > env->pregs[PR_SRS] &= 3;
> > > @@ -216,7 +209,7 @@ static void cris_ccs_rshift(CPUCRISState *env)
> > > env->pregs[PR_CCS] = ccs;
> > > }
> > >
> > > -void helper_rfe(void)
> > > +void helper_rfe(CPUCRISState *env)
> > > {
> > > int rflag = env->pregs[PR_CCS] & R_FLAG;
> > >
> > > @@ -232,7 +225,7 @@ void helper_rfe(void)
> > > env->pregs[PR_CCS] |= P_FLAG;
> > > }
> > >
> > > -void helper_rfn(void)
> > > +void helper_rfn(CPUCRISState *env)
> > > {
> > > int rflag = env->pregs[PR_CCS] & R_FLAG;
> > >
> > > @@ -256,7 +249,7 @@ uint32_t helper_lz(uint32_t t0)
> > > return clz32(t0);
> > > }
> > >
> > > -uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
> > > +uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
> > > {
> > > /* FIXME: clean this up. */
> > >
> > > @@ -284,7 +277,8 @@ uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
> > > return ccs;
> > > }
> > >
> > > -static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
> > > +static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
> > > + uint32_t flags, uint32_t ccs)
> > > {
> > > unsigned int x, z, mask;
> > >
> > > @@ -303,7 +297,8 @@ static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
> > > return ccs;
> > > }
> > >
> > > -uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
> > > +uint32_t helper_evaluate_flags_muls(CPUCRISState *env, uint32_t ccs,
> > > + uint32_t res, uint32_t mof)
> > > {
> > > uint32_t flags = 0;
> > > int64_t tmp;
> > > @@ -321,10 +316,11 @@ uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
> > > if ((dneg && mof != -1)
> > > || (!dneg && mof != 0))
> > > flags |= V_FLAG;
> > > - return evaluate_flags_writeback(flags, ccs);
> > > + return evaluate_flags_writeback(env, flags, ccs);
> > > }
> > >
> > > -uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
> > > +uint32_t helper_evaluate_flags_mulu(CPUCRISState *env, uint32_t ccs,
> > > + uint32_t res, uint32_t mof)
> > > {
> > > uint32_t flags = 0;
> > > uint64_t tmp;
> > > @@ -339,10 +335,10 @@ uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
> > > if (mof)
> > > flags |= V_FLAG;
> > >
> > > - return evaluate_flags_writeback(flags, ccs);
> > > + return evaluate_flags_writeback(env, flags, ccs);
> > > }
> > >
> > > -uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
> > > +uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
> > > uint32_t src, uint32_t dst, uint32_t res)
> > > {
> > > uint32_t flags = 0;
> > > @@ -368,10 +364,10 @@ uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
> > > flags |= R_FLAG;
> > > }
> > >
> > > - return evaluate_flags_writeback(flags, ccs);
> > > + return evaluate_flags_writeback(env, flags, ccs);
> > > }
> > >
> > > -uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
> > > +uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
> > > uint32_t src, uint32_t dst, uint32_t res)
> > > {
> > > uint32_t flags = 0;
> > > @@ -397,10 +393,10 @@ uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
> > > flags |= C_FLAG;
> > > }
> > >
> > > - return evaluate_flags_writeback(flags, ccs);
> > > + return evaluate_flags_writeback(env, flags, ccs);
> > > }
> > >
> > > -uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
> > > +uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
> > > uint32_t src, uint32_t dst, uint32_t res)
> > > {
> > > uint32_t flags = 0;
> > > @@ -427,10 +423,11 @@ uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
> > > }
> > >
> > > flags ^= C_FLAG;
> > > - return evaluate_flags_writeback(flags, ccs);
> > > + return evaluate_flags_writeback(env, flags, ccs);
> > > }
> > >
> > > -uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
> > > +uint32_t helper_evaluate_flags_move_4(CPUCRISState *env, uint32_t ccs,
> > > + uint32_t res)
> > > {
> > > uint32_t flags = 0;
> > >
> > > @@ -439,9 +436,10 @@ uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
> > > else if (res == 0L)
> > > flags |= Z_FLAG;
> > >
> > > - return evaluate_flags_writeback(flags, ccs);
> > > + return evaluate_flags_writeback(env, flags, ccs);
> > > }
> > > -uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
> > > +uint32_t helper_evaluate_flags_move_2(CPUCRISState *env, uint32_t ccs,
> > > + uint32_t res)
> > > {
> > > uint32_t flags = 0;
> > >
> > > @@ -450,12 +448,12 @@ uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
> > > else if (res == 0)
> > > flags |= Z_FLAG;
> > >
> > > - return evaluate_flags_writeback(flags, ccs);
> > > + return evaluate_flags_writeback(env, flags, ccs);
> > > }
> > >
> > > /* TODO: This is expensive. We could split things up and only evaluate part of
> > > CCR on a need to know basis. For now, we simply re-evaluate everything. */
> > > -void helper_evaluate_flags(void)
> > > +void helper_evaluate_flags(CPUCRISState *env)
> > > {
> > > uint32_t src, dst, res;
> > > uint32_t flags = 0;
> > > @@ -571,25 +569,26 @@ void helper_evaluate_flags(void)
> > > if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
> > > flags ^= C_FLAG;
> > >
> > > - env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
> > > + env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
> > > + env->pregs[PR_CCS]);
> > > }
> > >
> > > -void helper_top_evaluate_flags(void)
> > > +void helper_top_evaluate_flags(CPUCRISState *env)
> > > {
> > > switch (env->cc_op)
> > > {
> > > case CC_OP_MCP:
> > > - env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
> > > + env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
> > > env->pregs[PR_CCS], env->cc_src,
> > > env->cc_dest, env->cc_result);
> > > break;
> > > case CC_OP_MULS:
> > > - env->pregs[PR_CCS] = helper_evaluate_flags_muls(
> > > + env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
> > > env->pregs[PR_CCS], env->cc_result,
> > > env->pregs[PR_MOF]);
> > > break;
> > > case CC_OP_MULU:
> > > - env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
> > > + env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
> > > env->pregs[PR_CCS], env->cc_result,
> > > env->pregs[PR_MOF]);
> > > break;
> > > @@ -604,18 +603,18 @@ void helper_top_evaluate_flags(void)
> > > {
> > > case 4:
> > > env->pregs[PR_CCS] =
> > > - helper_evaluate_flags_move_4(
> > > + helper_evaluate_flags_move_4(env,
> > > env->pregs[PR_CCS],
> > > env->cc_result);
> > > break;
> > > case 2:
> > > env->pregs[PR_CCS] =
> > > - helper_evaluate_flags_move_2(
> > > + helper_evaluate_flags_move_2(env,
> > > env->pregs[PR_CCS],
> > > env->cc_result);
> > > break;
> > > default:
> > > - helper_evaluate_flags();
> > > + helper_evaluate_flags(env);
> > > break;
> > > }
> > > break;
> > > @@ -626,12 +625,12 @@ void helper_top_evaluate_flags(void)
> > > case CC_OP_CMP:
> > > if (env->cc_size == 4)
> > > env->pregs[PR_CCS] =
> > > - helper_evaluate_flags_sub_4(
> > > + helper_evaluate_flags_sub_4(env,
> > > env->pregs[PR_CCS],
> > > env->cc_src, env->cc_dest,
> > > env->cc_result);
> > > else
> > > - helper_evaluate_flags();
> > > + helper_evaluate_flags(env);
> > > break;
> > > default:
> > > {
> > > @@ -639,13 +638,13 @@ void helper_top_evaluate_flags(void)
> > > {
> > > case 4:
> > > env->pregs[PR_CCS] =
> > > - helper_evaluate_flags_alu_4(
> > > + helper_evaluate_flags_alu_4(env,
> > > env->pregs[PR_CCS],
> > > env->cc_src, env->cc_dest,
> > > env->cc_result);
> > > break;
> > > default:
> > > - helper_evaluate_flags();
> > > + helper_evaluate_flags(env);
> > > break;
> > > }
> > > }
> > > diff --git a/target-cris/translate.c b/target-cris/translate.c
> > > index 1ad9ec7..5e4f7f5 100644
> > > --- a/target-cris/translate.c
> > > +++ b/target-cris/translate.c
> > > @@ -211,9 +211,9 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
> > > tcg_gen_andi_tl(cpu_PR[r], tn, 3);
> > > else {
> > > if (r == PR_PID)
> > > - gen_helper_tlb_flush_pid(tn);
> > > + gen_helper_tlb_flush_pid(cpu_env, tn);
> > > if (dc->tb_flags & S_FLAG && r == PR_SPC)
> > > - gen_helper_spc_write(tn);
> > > + gen_helper_spc_write(cpu_env, tn);
> > > else if (r == PR_CCS)
> > > dc->cpustate_changed = 1;
> > > tcg_gen_mov_tl(cpu_PR[r], tn);
> > > @@ -241,24 +241,24 @@ static int cris_fetch(DisasContext *dc, uint32_t addr,
> > > switch (size) {
> > > case 4:
> > > {
> > > - r = ldl_code(addr);
> > > + r = cpu_ldl_code(cpu_single_env, addr);
> > > break;
> > > }
> > > case 2:
> > > {
> > > if (sign) {
> > > - r = ldsw_code(addr);
> > > + r = cpu_ldsw_code(cpu_single_env, addr);
> > > } else {
> > > - r = lduw_code(addr);
> > > + r = cpu_lduw_code(cpu_single_env, addr);
> > > }
> > > break;
> > > }
> > > case 1:
> > > {
> > > if (sign) {
> > > - r = ldsb_code(addr);
> > > + r = cpu_ldsb_code(cpu_single_env, addr);
> > > } else {
> > > - r = ldub_code(addr);
> > > + r = cpu_ldub_code(cpu_single_env, addr);
> > > }
> > > break;
> > > }
> > > @@ -278,7 +278,7 @@ static void cris_lock_irq(DisasContext *dc)
> > > static inline void t_gen_raise_exception(uint32_t index)
> > > {
> > > TCGv_i32 tmp = tcg_const_i32(index);
> > > - gen_helper_raise_exception(tmp);
> > > + gen_helper_raise_exception(cpu_env, tmp);
> > > tcg_temp_free_i32(tmp);
> > > }
> > >
> > > @@ -624,17 +624,17 @@ static void cris_evaluate_flags(DisasContext *dc)
> > > switch (dc->cc_op)
> > > {
> > > case CC_OP_MCP:
> > > - gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
> > > + gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
> > > cpu_PR[PR_CCS], cc_src,
> > > cc_dest, cc_result);
> > > break;
> > > case CC_OP_MULS:
> > > - gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
> > > + gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
> > > cpu_PR[PR_CCS], cc_result,
> > > cpu_PR[PR_MOF]);
> > > break;
> > > case CC_OP_MULU:
> > > - gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
> > > + gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
> > > cpu_PR[PR_CCS], cc_result,
> > > cpu_PR[PR_MOF]);
> > > break;
> > > @@ -648,15 +648,15 @@ static void cris_evaluate_flags(DisasContext *dc)
> > > switch (dc->cc_size)
> > > {
> > > case 4:
> > > - gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
> > > + gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], cpu_env,
> > > cpu_PR[PR_CCS], cc_result);
> > > break;
> > > case 2:
> > > - gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
> > > + gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], cpu_env,
> > > cpu_PR[PR_CCS], cc_result);
> > > break;
> > > default:
> > > - gen_helper_evaluate_flags();
> > > + gen_helper_evaluate_flags(cpu_env);
> > > break;
> > > }
> > > break;
> > > @@ -666,21 +666,21 @@ static void cris_evaluate_flags(DisasContext *dc)
> > > case CC_OP_SUB:
> > > case CC_OP_CMP:
> > > if (dc->cc_size == 4)
> > > - gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
> > > + gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
> > > cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
> > > else
> > > - gen_helper_evaluate_flags();
> > > + gen_helper_evaluate_flags(cpu_env);
> > >
> > > break;
> > > default:
> > > switch (dc->cc_size)
> > > {
> > > case 4:
> > > - gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
> > > + gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
> > > cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
> > > break;
> > > default:
> > > - gen_helper_evaluate_flags();
> > > + gen_helper_evaluate_flags(cpu_env);
> > > break;
> > > }
> > > break;
> > > @@ -1475,7 +1475,7 @@ static int dec_btstq(DisasContext *dc)
> > >
> > > cris_cc_mask(dc, CC_MASK_NZ);
> > > cris_evaluate_flags(dc);
> > > - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
> > > + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
> > > tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
> > > cris_alu(dc, CC_OP_MOVE,
> > > cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
> > > @@ -1925,7 +1925,7 @@ static int dec_btst_r(DisasContext *dc)
> > > dc->op1, dc->op2);
> > > cris_cc_mask(dc, CC_MASK_NZ);
> > > cris_evaluate_flags(dc);
> > > - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
> > > + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
> > > cpu_R[dc->op1], cpu_PR[PR_CCS]);
> > > cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
> > > cpu_R[dc->op2], cpu_R[dc->op2], 4);
> > > @@ -2135,14 +2135,16 @@ static int dec_move_rs(DisasContext *dc)
> > > {
> > > LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
> > > cris_cc_mask(dc, 0);
> > > - gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
> > > + gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
> > > + tcg_const_tl(dc->op1));
> > > return 2;
> > > }
> > > static int dec_move_sr(DisasContext *dc)
> > > {
> > > LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
> > > cris_cc_mask(dc, 0);
> > > - gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
> > > + gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
> > > + tcg_const_tl(dc->op2));
> > > return 2;
> > > }
> > >
> > > @@ -2906,14 +2908,14 @@ static int dec_rfe_etc(DisasContext *dc)
> > > /* rfe. */
> > > LOG_DIS("rfe\n");
> > > cris_evaluate_flags(dc);
> > > - gen_helper_rfe();
> > > + gen_helper_rfe(cpu_env);
> > > dc->is_jmp = DISAS_UPDATE;
> > > break;
> > > case 5:
> > > /* rfn. */
> > > LOG_DIS("rfn\n");
> > > cris_evaluate_flags(dc);
> > > - gen_helper_rfn();
> > > + gen_helper_rfn(cpu_env);
> > > dc->is_jmp = DISAS_UPDATE;
> > > break;
> > > case 6:
> >
> > Similarly to what I reported for the microblaze and sh4 target, I think
> > we should not start using cpu_single_env (a global variable) to replace
> > env (a global variable stored in a register).
> >
> > It is possible to pass env through the subroutine, though it is more
> > complicated there than for other targets. I have therefore done the work
> > and I have attached the two resulting patches to this mail.
>
> Hi Aurelien!
>
> I agree with your comment and change. The indentation looks a bit odd
> here though. The CRISv32 port used tabs when written but some patches
> have made it in that used space, so it's become a bit of a mess. Maybe
> it's time to convert it to the QEMU codingstyle?
Yes, I tried to make script/checkpatch.pl happy as I know Blue Swirl
really care about that.
> From my point of view, I think we should either keep the tabs or change
> the whole file for 4 space indent.
>
> I've got nothing against applying your patch as is and then on top of that
> the mechanical untabification, to avoid extra work on your side.
>
As you prefer, I can also provide the same patches with tabs instead.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 18/21] target-cris: switch to AREG0 free mode
2012-09-07 14:46 ` Aurelien Jarno
@ 2012-09-08 3:34 ` Edgar E. Iglesias
0 siblings, 0 replies; 64+ messages in thread
From: Edgar E. Iglesias @ 2012-09-08 3:34 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: Blue Swirl, qemu-devel
> > > case 6:
> > >
> > > Similarly to what I reported for the microblaze and sh4 target, I think
> > > we should not start using cpu_single_env (a global variable) to replace
> > > env (a global variable stored in a register).
> > >
> > > It is possible to pass env through the subroutine, though it is more
> > > complicated there than for other targets. I have therefore done the work
> > > and I have attached the two resulting patches to this mail.
> >
> > Hi Aurelien!
> >
> > I agree with your comment and change. The indentation looks a bit odd
> > here though. The CRISv32 port used tabs when written but some patches
> > have made it in that used space, so it's become a bit of a mess. Maybe
> > it's time to convert it to the QEMU codingstyle?
>
> Yes, I tried to make script/checkpatch.pl happy as I know Blue Swirl
> really care about that.
>
> > From my point of view, I think we should either keep the tabs or change
> > the whole file for 4 space indent.
> >
> > I've got nothing against applying your patch as is and then on top of that
> > the mechanical untabification, to avoid extra work on your side.
> >
>
> As you prefer, I can also provide the same patches with tabs instead.
OK, please keep your patch and when it's applied I'll put an untabification
on top.
Cheers,
Edgar
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 18/21] target-cris: switch to AREG0 free mode
2012-09-07 14:18 ` Aurelien Jarno
2012-09-07 14:40 ` Edgar E. Iglesias
@ 2012-09-08 8:35 ` Blue Swirl
2012-09-08 9:02 ` Aurelien Jarno
1 sibling, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-08 8:35 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: Edgar E. Iglesias, qemu-devel
On Fri, Sep 7, 2012 at 2:18 PM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Sun, Sep 02, 2012 at 05:33:47PM +0000, Blue Swirl wrote:
>> Add an explicit CPUState parameter instead of relying on AREG0
>> and switch to AREG0 free mode.
>>
>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>> ---
>> configure | 2 +-
>> target-cris/Makefile.objs | 2 -
>> target-cris/helper.c | 4 +-
>> target-cris/helper.h | 34 ++++++++--------
>> target-cris/op_helper.c | 89 +++++++++++++++++++++----------------------
>> target-cris/translate.c | 50 ++++++++++++-----------
>> target-cris/translate_v10.c | 22 +++++-----
>> 7 files changed, 101 insertions(+), 102 deletions(-)
>>
>> diff --git a/configure b/configure
>> index e464d2f..d760e07 100755
>> --- a/configure
>> +++ b/configure
>> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
>>
>>
>> case "$target_arch2" in
>> - alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
>> + alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
>> echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
>> ;;
>> esac
>> diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
>> index 4b09e8c..afb87bc 100644
>> --- a/target-cris/Makefile.objs
>> +++ b/target-cris/Makefile.objs
>> @@ -1,4 +1,2 @@
>> obj-y += translate.o op_helper.o helper.o cpu.o
>> obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
>> -
>> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
>> diff --git a/target-cris/helper.c b/target-cris/helper.c
>> index bfbc29e..1bdb7e2 100644
>> --- a/target-cris/helper.c
>> +++ b/target-cris/helper.c
>> @@ -151,7 +151,7 @@ static void do_interruptv10(CPUCRISState *env)
>> }
>>
>> /* Now that we are in kernel mode, load the handlers address. */
>> - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
>> + env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
>> env->locked_irq = 1;
>> env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
>>
>> @@ -233,7 +233,7 @@ void do_interrupt(CPUCRISState *env)
>> /* Now that we are in kernel mode, load the handlers address.
>> This load may not fault, real hw leaves that behaviour as
>> undefined. */
>> - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
>> + env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
>>
>> /* Clear the excption_index to avoid spurios hw_aborts for recursive
>> bus faults. */
>> diff --git a/target-cris/helper.h b/target-cris/helper.h
>> index 093063a..b575524 100644
>> --- a/target-cris/helper.h
>> +++ b/target-cris/helper.h
>> @@ -1,26 +1,26 @@
>> #include "def-helper.h"
>>
>> -DEF_HELPER_1(raise_exception, void, i32)
>> -DEF_HELPER_1(tlb_flush_pid, void, i32)
>> -DEF_HELPER_1(spc_write, void, i32)
>> +DEF_HELPER_2(raise_exception, void, env, i32)
>> +DEF_HELPER_2(tlb_flush_pid, void, env, i32)
>> +DEF_HELPER_2(spc_write, void, env, i32)
>> DEF_HELPER_3(dump, void, i32, i32, i32)
>> -DEF_HELPER_0(rfe, void);
>> -DEF_HELPER_0(rfn, void);
>> +DEF_HELPER_1(rfe, void, env);
>> +DEF_HELPER_1(rfn, void, env);
>>
>> -DEF_HELPER_2(movl_sreg_reg, void, i32, i32)
>> -DEF_HELPER_2(movl_reg_sreg, void, i32, i32)
>> +DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32)
>> +DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32)
>>
>> DEF_HELPER_FLAGS_1(lz, TCG_CALL_PURE, i32, i32);
>> -DEF_HELPER_FLAGS_3(btst, TCG_CALL_PURE, i32, i32, i32, i32);
>> +DEF_HELPER_FLAGS_4(btst, TCG_CALL_PURE, i32, env, i32, i32, i32);
>>
>> -DEF_HELPER_FLAGS_3(evaluate_flags_muls, TCG_CALL_PURE, i32, i32, i32, i32)
>> -DEF_HELPER_FLAGS_3(evaluate_flags_mulu, TCG_CALL_PURE, i32, i32, i32, i32)
>> -DEF_HELPER_FLAGS_4(evaluate_flags_mcp, TCG_CALL_PURE, i32, i32, i32, i32, i32)
>> -DEF_HELPER_FLAGS_4(evaluate_flags_alu_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
>> -DEF_HELPER_FLAGS_4(evaluate_flags_sub_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
>> -DEF_HELPER_FLAGS_2(evaluate_flags_move_4, TCG_CALL_PURE, i32, i32, i32)
>> -DEF_HELPER_FLAGS_2(evaluate_flags_move_2, TCG_CALL_PURE, i32, i32, i32)
>> -DEF_HELPER_0(evaluate_flags, void)
>> -DEF_HELPER_0(top_evaluate_flags, void)
>> +DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_PURE, i32, env, i32, i32, i32)
>> +DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_PURE, i32, env, i32, i32, i32)
>> +DEF_HELPER_FLAGS_5(evaluate_flags_mcp, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
>> +DEF_HELPER_FLAGS_5(evaluate_flags_alu_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
>> +DEF_HELPER_FLAGS_5(evaluate_flags_sub_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
>> +DEF_HELPER_FLAGS_3(evaluate_flags_move_4, TCG_CALL_PURE, i32, env, i32, i32)
>> +DEF_HELPER_FLAGS_3(evaluate_flags_move_2, TCG_CALL_PURE, i32, env, i32, i32)
>> +DEF_HELPER_1(evaluate_flags, void, env)
>> +DEF_HELPER_1(top_evaluate_flags, void, env)
>>
>> #include "def-helper.h"
>> diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
>> index ac7c98c..5cce3e7 100644
>> --- a/target-cris/op_helper.c
>> +++ b/target-cris/op_helper.c
>> @@ -19,7 +19,6 @@
>> */
>>
>> #include "cpu.h"
>> -#include "dyngen-exec.h"
>> #include "mmu.h"
>> #include "helper.h"
>> #include "host-utils.h"
>> @@ -55,17 +54,12 @@
>> /* Try to fill the TLB and return an exception if error. If retaddr is
>> NULL, it means that the function was called in C code (i.e. not
>> from generated code or from helper.c) */
>> -/* XXX: fix it to restore all registers */
>> -void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
>> +void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
>> uintptr_t retaddr)
>> {
>> TranslationBlock *tb;
>> - CPUCRISState *saved_env;
>> int ret;
>>
>> - saved_env = env;
>> - env = env1;
>> -
>> D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
>> env->pc, env->debug1, (void *)retaddr);
>> ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
>> @@ -79,23 +73,22 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
>> cpu_restore_state(tb, env, retaddr);
>>
>> /* Evaluate flags after retranslation. */
>> - helper_top_evaluate_flags();
>> + helper_top_evaluate_flags(env);
>> }
>> }
>> cpu_loop_exit(env);
>> }
>> - env = saved_env;
>> }
>>
>> #endif
>>
>> -void helper_raise_exception(uint32_t index)
>> +void helper_raise_exception(CPUCRISState *env, uint32_t index)
>> {
>> env->exception_index = index;
>> cpu_loop_exit(env);
>> }
>>
>> -void helper_tlb_flush_pid(uint32_t pid)
>> +void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
>> {
>> #if !defined(CONFIG_USER_ONLY)
>> pid &= 0xff;
>> @@ -104,7 +97,7 @@ void helper_tlb_flush_pid(uint32_t pid)
>> #endif
>> }
>>
>> -void helper_spc_write(uint32_t new_spc)
>> +void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
>> {
>> #if !defined(CONFIG_USER_ONLY)
>> tlb_flush_page(env, env->pregs[PR_SPC]);
>> @@ -121,7 +114,7 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
>> #define EXTRACT_FIELD(src, start, end) \
>> (((src) >> start) & ((1 << (end - start + 1)) - 1))
>>
>> -void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
>> +void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
>> {
>> uint32_t srs;
>> srs = env->pregs[PR_SRS];
>> @@ -171,7 +164,7 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
>> #endif
>> }
>>
>> -void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
>> +void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
>> {
>> uint32_t srs;
>> env->pregs[PR_SRS] &= 3;
>> @@ -216,7 +209,7 @@ static void cris_ccs_rshift(CPUCRISState *env)
>> env->pregs[PR_CCS] = ccs;
>> }
>>
>> -void helper_rfe(void)
>> +void helper_rfe(CPUCRISState *env)
>> {
>> int rflag = env->pregs[PR_CCS] & R_FLAG;
>>
>> @@ -232,7 +225,7 @@ void helper_rfe(void)
>> env->pregs[PR_CCS] |= P_FLAG;
>> }
>>
>> -void helper_rfn(void)
>> +void helper_rfn(CPUCRISState *env)
>> {
>> int rflag = env->pregs[PR_CCS] & R_FLAG;
>>
>> @@ -256,7 +249,7 @@ uint32_t helper_lz(uint32_t t0)
>> return clz32(t0);
>> }
>>
>> -uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
>> +uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
>> {
>> /* FIXME: clean this up. */
>>
>> @@ -284,7 +277,8 @@ uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
>> return ccs;
>> }
>>
>> -static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
>> +static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
>> + uint32_t flags, uint32_t ccs)
>> {
>> unsigned int x, z, mask;
>>
>> @@ -303,7 +297,8 @@ static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
>> return ccs;
>> }
>>
>> -uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
>> +uint32_t helper_evaluate_flags_muls(CPUCRISState *env, uint32_t ccs,
>> + uint32_t res, uint32_t mof)
>> {
>> uint32_t flags = 0;
>> int64_t tmp;
>> @@ -321,10 +316,11 @@ uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
>> if ((dneg && mof != -1)
>> || (!dneg && mof != 0))
>> flags |= V_FLAG;
>> - return evaluate_flags_writeback(flags, ccs);
>> + return evaluate_flags_writeback(env, flags, ccs);
>> }
>>
>> -uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
>> +uint32_t helper_evaluate_flags_mulu(CPUCRISState *env, uint32_t ccs,
>> + uint32_t res, uint32_t mof)
>> {
>> uint32_t flags = 0;
>> uint64_t tmp;
>> @@ -339,10 +335,10 @@ uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
>> if (mof)
>> flags |= V_FLAG;
>>
>> - return evaluate_flags_writeback(flags, ccs);
>> + return evaluate_flags_writeback(env, flags, ccs);
>> }
>>
>> -uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
>> +uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
>> uint32_t src, uint32_t dst, uint32_t res)
>> {
>> uint32_t flags = 0;
>> @@ -368,10 +364,10 @@ uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
>> flags |= R_FLAG;
>> }
>>
>> - return evaluate_flags_writeback(flags, ccs);
>> + return evaluate_flags_writeback(env, flags, ccs);
>> }
>>
>> -uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
>> +uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
>> uint32_t src, uint32_t dst, uint32_t res)
>> {
>> uint32_t flags = 0;
>> @@ -397,10 +393,10 @@ uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
>> flags |= C_FLAG;
>> }
>>
>> - return evaluate_flags_writeback(flags, ccs);
>> + return evaluate_flags_writeback(env, flags, ccs);
>> }
>>
>> -uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
>> +uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
>> uint32_t src, uint32_t dst, uint32_t res)
>> {
>> uint32_t flags = 0;
>> @@ -427,10 +423,11 @@ uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
>> }
>>
>> flags ^= C_FLAG;
>> - return evaluate_flags_writeback(flags, ccs);
>> + return evaluate_flags_writeback(env, flags, ccs);
>> }
>>
>> -uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
>> +uint32_t helper_evaluate_flags_move_4(CPUCRISState *env, uint32_t ccs,
>> + uint32_t res)
>> {
>> uint32_t flags = 0;
>>
>> @@ -439,9 +436,10 @@ uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
>> else if (res == 0L)
>> flags |= Z_FLAG;
>>
>> - return evaluate_flags_writeback(flags, ccs);
>> + return evaluate_flags_writeback(env, flags, ccs);
>> }
>> -uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
>> +uint32_t helper_evaluate_flags_move_2(CPUCRISState *env, uint32_t ccs,
>> + uint32_t res)
>> {
>> uint32_t flags = 0;
>>
>> @@ -450,12 +448,12 @@ uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
>> else if (res == 0)
>> flags |= Z_FLAG;
>>
>> - return evaluate_flags_writeback(flags, ccs);
>> + return evaluate_flags_writeback(env, flags, ccs);
>> }
>>
>> /* TODO: This is expensive. We could split things up and only evaluate part of
>> CCR on a need to know basis. For now, we simply re-evaluate everything. */
>> -void helper_evaluate_flags(void)
>> +void helper_evaluate_flags(CPUCRISState *env)
>> {
>> uint32_t src, dst, res;
>> uint32_t flags = 0;
>> @@ -571,25 +569,26 @@ void helper_evaluate_flags(void)
>> if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
>> flags ^= C_FLAG;
>>
>> - env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
>> + env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
>> + env->pregs[PR_CCS]);
>> }
>>
>> -void helper_top_evaluate_flags(void)
>> +void helper_top_evaluate_flags(CPUCRISState *env)
>> {
>> switch (env->cc_op)
>> {
>> case CC_OP_MCP:
>> - env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
>> + env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
>> env->pregs[PR_CCS], env->cc_src,
>> env->cc_dest, env->cc_result);
>> break;
>> case CC_OP_MULS:
>> - env->pregs[PR_CCS] = helper_evaluate_flags_muls(
>> + env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
>> env->pregs[PR_CCS], env->cc_result,
>> env->pregs[PR_MOF]);
>> break;
>> case CC_OP_MULU:
>> - env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
>> + env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
>> env->pregs[PR_CCS], env->cc_result,
>> env->pregs[PR_MOF]);
>> break;
>> @@ -604,18 +603,18 @@ void helper_top_evaluate_flags(void)
>> {
>> case 4:
>> env->pregs[PR_CCS] =
>> - helper_evaluate_flags_move_4(
>> + helper_evaluate_flags_move_4(env,
>> env->pregs[PR_CCS],
>> env->cc_result);
>> break;
>> case 2:
>> env->pregs[PR_CCS] =
>> - helper_evaluate_flags_move_2(
>> + helper_evaluate_flags_move_2(env,
>> env->pregs[PR_CCS],
>> env->cc_result);
>> break;
>> default:
>> - helper_evaluate_flags();
>> + helper_evaluate_flags(env);
>> break;
>> }
>> break;
>> @@ -626,12 +625,12 @@ void helper_top_evaluate_flags(void)
>> case CC_OP_CMP:
>> if (env->cc_size == 4)
>> env->pregs[PR_CCS] =
>> - helper_evaluate_flags_sub_4(
>> + helper_evaluate_flags_sub_4(env,
>> env->pregs[PR_CCS],
>> env->cc_src, env->cc_dest,
>> env->cc_result);
>> else
>> - helper_evaluate_flags();
>> + helper_evaluate_flags(env);
>> break;
>> default:
>> {
>> @@ -639,13 +638,13 @@ void helper_top_evaluate_flags(void)
>> {
>> case 4:
>> env->pregs[PR_CCS] =
>> - helper_evaluate_flags_alu_4(
>> + helper_evaluate_flags_alu_4(env,
>> env->pregs[PR_CCS],
>> env->cc_src, env->cc_dest,
>> env->cc_result);
>> break;
>> default:
>> - helper_evaluate_flags();
>> + helper_evaluate_flags(env);
>> break;
>> }
>> }
>> diff --git a/target-cris/translate.c b/target-cris/translate.c
>> index 1ad9ec7..5e4f7f5 100644
>> --- a/target-cris/translate.c
>> +++ b/target-cris/translate.c
>> @@ -211,9 +211,9 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
>> tcg_gen_andi_tl(cpu_PR[r], tn, 3);
>> else {
>> if (r == PR_PID)
>> - gen_helper_tlb_flush_pid(tn);
>> + gen_helper_tlb_flush_pid(cpu_env, tn);
>> if (dc->tb_flags & S_FLAG && r == PR_SPC)
>> - gen_helper_spc_write(tn);
>> + gen_helper_spc_write(cpu_env, tn);
>> else if (r == PR_CCS)
>> dc->cpustate_changed = 1;
>> tcg_gen_mov_tl(cpu_PR[r], tn);
>> @@ -241,24 +241,24 @@ static int cris_fetch(DisasContext *dc, uint32_t addr,
>> switch (size) {
>> case 4:
>> {
>> - r = ldl_code(addr);
>> + r = cpu_ldl_code(cpu_single_env, addr);
>> break;
>> }
>> case 2:
>> {
>> if (sign) {
>> - r = ldsw_code(addr);
>> + r = cpu_ldsw_code(cpu_single_env, addr);
>> } else {
>> - r = lduw_code(addr);
>> + r = cpu_lduw_code(cpu_single_env, addr);
>> }
>> break;
>> }
>> case 1:
>> {
>> if (sign) {
>> - r = ldsb_code(addr);
>> + r = cpu_ldsb_code(cpu_single_env, addr);
>> } else {
>> - r = ldub_code(addr);
>> + r = cpu_ldub_code(cpu_single_env, addr);
>> }
>> break;
>> }
>> @@ -278,7 +278,7 @@ static void cris_lock_irq(DisasContext *dc)
>> static inline void t_gen_raise_exception(uint32_t index)
>> {
>> TCGv_i32 tmp = tcg_const_i32(index);
>> - gen_helper_raise_exception(tmp);
>> + gen_helper_raise_exception(cpu_env, tmp);
>> tcg_temp_free_i32(tmp);
>> }
>>
>> @@ -624,17 +624,17 @@ static void cris_evaluate_flags(DisasContext *dc)
>> switch (dc->cc_op)
>> {
>> case CC_OP_MCP:
>> - gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
>> + gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
>> cpu_PR[PR_CCS], cc_src,
>> cc_dest, cc_result);
>> break;
>> case CC_OP_MULS:
>> - gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
>> + gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
>> cpu_PR[PR_CCS], cc_result,
>> cpu_PR[PR_MOF]);
>> break;
>> case CC_OP_MULU:
>> - gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
>> + gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
>> cpu_PR[PR_CCS], cc_result,
>> cpu_PR[PR_MOF]);
>> break;
>> @@ -648,15 +648,15 @@ static void cris_evaluate_flags(DisasContext *dc)
>> switch (dc->cc_size)
>> {
>> case 4:
>> - gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
>> + gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], cpu_env,
>> cpu_PR[PR_CCS], cc_result);
>> break;
>> case 2:
>> - gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
>> + gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], cpu_env,
>> cpu_PR[PR_CCS], cc_result);
>> break;
>> default:
>> - gen_helper_evaluate_flags();
>> + gen_helper_evaluate_flags(cpu_env);
>> break;
>> }
>> break;
>> @@ -666,21 +666,21 @@ static void cris_evaluate_flags(DisasContext *dc)
>> case CC_OP_SUB:
>> case CC_OP_CMP:
>> if (dc->cc_size == 4)
>> - gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
>> + gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
>> cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
>> else
>> - gen_helper_evaluate_flags();
>> + gen_helper_evaluate_flags(cpu_env);
>>
>> break;
>> default:
>> switch (dc->cc_size)
>> {
>> case 4:
>> - gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
>> + gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
>> cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
>> break;
>> default:
>> - gen_helper_evaluate_flags();
>> + gen_helper_evaluate_flags(cpu_env);
>> break;
>> }
>> break;
>> @@ -1475,7 +1475,7 @@ static int dec_btstq(DisasContext *dc)
>>
>> cris_cc_mask(dc, CC_MASK_NZ);
>> cris_evaluate_flags(dc);
>> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
>> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
>> tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
>> cris_alu(dc, CC_OP_MOVE,
>> cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
>> @@ -1925,7 +1925,7 @@ static int dec_btst_r(DisasContext *dc)
>> dc->op1, dc->op2);
>> cris_cc_mask(dc, CC_MASK_NZ);
>> cris_evaluate_flags(dc);
>> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
>> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
>> cpu_R[dc->op1], cpu_PR[PR_CCS]);
>> cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
>> cpu_R[dc->op2], cpu_R[dc->op2], 4);
>> @@ -2135,14 +2135,16 @@ static int dec_move_rs(DisasContext *dc)
>> {
>> LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
>> cris_cc_mask(dc, 0);
>> - gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
>> + gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
>> + tcg_const_tl(dc->op1));
>> return 2;
>> }
>> static int dec_move_sr(DisasContext *dc)
>> {
>> LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
>> cris_cc_mask(dc, 0);
>> - gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
>> + gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
>> + tcg_const_tl(dc->op2));
>> return 2;
>> }
>>
>> @@ -2906,14 +2908,14 @@ static int dec_rfe_etc(DisasContext *dc)
>> /* rfe. */
>> LOG_DIS("rfe\n");
>> cris_evaluate_flags(dc);
>> - gen_helper_rfe();
>> + gen_helper_rfe(cpu_env);
>> dc->is_jmp = DISAS_UPDATE;
>> break;
>> case 5:
>> /* rfn. */
>> LOG_DIS("rfn\n");
>> cris_evaluate_flags(dc);
>> - gen_helper_rfn();
>> + gen_helper_rfn(cpu_env);
>> dc->is_jmp = DISAS_UPDATE;
>> break;
>> case 6:
>> diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
>> index 3629629..d9d6aa5 100644
>> --- a/target-cris/translate_v10.c
>> +++ b/target-cris/translate_v10.c
>> @@ -182,17 +182,17 @@ static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize,
>> if (memsize != 4) {
>> if (s_ext) {
>> if (memsize == 1)
>> - imm = ldsb_code(dc->pc + 2);
>> + imm = cpu_ldsb_code(cpu_single_env, dc->pc + 2);
>> else
>> - imm = ldsw_code(dc->pc + 2);
>> + imm = cpu_ldsw_code(cpu_single_env, dc->pc + 2);
>> } else {
>> if (memsize == 1)
>> - imm = ldub_code(dc->pc + 2);
>> + imm = cpu_ldub_code(cpu_single_env, dc->pc + 2);
>> else
>> - imm = lduw_code(dc->pc + 2);
>> + imm = cpu_lduw_code(cpu_single_env, dc->pc + 2);
>> }
>> } else
>> - imm = ldl_code(dc->pc + 2);
>> + imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
>>
>> tcg_gen_movi_tl(dst, imm);
>
> Similarly to what I reported for the microblaze and sh4 target, I think
> we should not start using cpu_single_env (a global variable) to replace
> env (a global variable stored in a register).
This task could be also taken to a different patch series, because the
conversions committed earlier also used cpu_single_env.
Eliminating cpu_single_env altogether may be possible but it would
need some refactoring.
>
> It is possible to pass env through the subroutine, though it is more
> complicated there than for other targets. I have therefore done the work
> and I have attached the two resulting patches to this mail.
Thank you for the work, the patches look better. I think the patches
should also include my sign-off.
>
>> @@ -289,7 +289,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
>> } else {
>> /* BTST */
>> cris_update_cc_op(dc, CC_OP_FLAGS, 4);
>> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
>> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
>> tcg_const_tl(imm), cpu_PR[PR_CCS]);
>> }
>> break;
>> @@ -723,7 +723,7 @@ static unsigned int dec10_reg(DisasContext *dc)
>> LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
>> cris_cc_mask(dc, CC_MASK_NZVC);
>> cris_update_cc_op(dc, CC_OP_FLAGS, 4);
>> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
>> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
>> cpu_R[dc->src], cpu_PR[PR_CCS]);
>> break;
>> case CRISV10_REG_DSTEP:
>> @@ -974,7 +974,7 @@ static int dec10_dip(DisasContext *dc)
>> LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
>> dc->pc, dc->opcode, dc->src, dc->dst);
>> if (dc->src == 15) {
>> - imm = ldl_code(dc->pc + 2);
>> + imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
>> tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
>> if (dc->postinc)
>> insn_len += 4;
>> @@ -1119,7 +1119,7 @@ static unsigned int dec10_ind(DisasContext *dc)
>> if (dc->src == 15) {
>> LOG_DIS("jump.%d %d r%d r%d direct\n", size,
>> dc->opcode, dc->src, dc->dst);
>> - imm = ldl_code(dc->pc + 2);
>> + imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
>> if (dc->mode == CRISV10_MODE_AUTOINC)
>> insn_len += size;
>>
>> @@ -1185,7 +1185,7 @@ static unsigned int dec10_ind(DisasContext *dc)
>> case CRISV10_IND_BCC_M:
>>
>> cris_cc_mask(dc, 0);
>> - imm = ldsw_code(dc->pc + 2);
>> + imm = cpu_ldsw_code(cpu_single_env, dc->pc + 2);
>> simm = (int16_t)imm;
>> simm += 4;
>>
>> @@ -1210,7 +1210,7 @@ static unsigned int crisv10_decoder(DisasContext *dc)
>> tcg_gen_debug_insn_start(dc->pc);
>>
>> /* Load a halfword onto the instruction register. */
>> - dc->ir = lduw_code(dc->pc);
>> + dc->ir = cpu_lduw_code(cpu_single_env, dc->pc);
>>
>> /* Now decode it. */
>> dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
>> --
>> 1.7.2.5
>>
>>
>>
>
> --
> Aurelien Jarno GPG: 1024D/F1BCDB73
> aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 18/21] target-cris: switch to AREG0 free mode
2012-09-08 8:35 ` Blue Swirl
@ 2012-09-08 9:02 ` Aurelien Jarno
0 siblings, 0 replies; 64+ messages in thread
From: Aurelien Jarno @ 2012-09-08 9:02 UTC (permalink / raw)
To: Blue Swirl; +Cc: Edgar E. Iglesias, qemu-devel
On Sat, Sep 08, 2012 at 08:35:18AM +0000, Blue Swirl wrote:
> On Fri, Sep 7, 2012 at 2:18 PM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> > On Sun, Sep 02, 2012 at 05:33:47PM +0000, Blue Swirl wrote:
> >> Add an explicit CPUState parameter instead of relying on AREG0
> >> and switch to AREG0 free mode.
> >>
> >> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> >> ---
> >> configure | 2 +-
> >> target-cris/Makefile.objs | 2 -
> >> target-cris/helper.c | 4 +-
> >> target-cris/helper.h | 34 ++++++++--------
> >> target-cris/op_helper.c | 89 +++++++++++++++++++++----------------------
> >> target-cris/translate.c | 50 ++++++++++++-----------
> >> target-cris/translate_v10.c | 22 +++++-----
> >> 7 files changed, 101 insertions(+), 102 deletions(-)
> >>
> >> diff --git a/configure b/configure
> >> index e464d2f..d760e07 100755
> >> --- a/configure
> >> +++ b/configure
> >> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
> >>
> >>
> >> case "$target_arch2" in
> >> - alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> >> + alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> >> echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
> >> ;;
> >> esac
> >> diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
> >> index 4b09e8c..afb87bc 100644
> >> --- a/target-cris/Makefile.objs
> >> +++ b/target-cris/Makefile.objs
> >> @@ -1,4 +1,2 @@
> >> obj-y += translate.o op_helper.o helper.o cpu.o
> >> obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
> >> -
> >> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> >> diff --git a/target-cris/helper.c b/target-cris/helper.c
> >> index bfbc29e..1bdb7e2 100644
> >> --- a/target-cris/helper.c
> >> +++ b/target-cris/helper.c
> >> @@ -151,7 +151,7 @@ static void do_interruptv10(CPUCRISState *env)
> >> }
> >>
> >> /* Now that we are in kernel mode, load the handlers address. */
> >> - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
> >> + env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
> >> env->locked_irq = 1;
> >> env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
> >>
> >> @@ -233,7 +233,7 @@ void do_interrupt(CPUCRISState *env)
> >> /* Now that we are in kernel mode, load the handlers address.
> >> This load may not fault, real hw leaves that behaviour as
> >> undefined. */
> >> - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
> >> + env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
> >>
> >> /* Clear the excption_index to avoid spurios hw_aborts for recursive
> >> bus faults. */
> >> diff --git a/target-cris/helper.h b/target-cris/helper.h
> >> index 093063a..b575524 100644
> >> --- a/target-cris/helper.h
> >> +++ b/target-cris/helper.h
> >> @@ -1,26 +1,26 @@
> >> #include "def-helper.h"
> >>
> >> -DEF_HELPER_1(raise_exception, void, i32)
> >> -DEF_HELPER_1(tlb_flush_pid, void, i32)
> >> -DEF_HELPER_1(spc_write, void, i32)
> >> +DEF_HELPER_2(raise_exception, void, env, i32)
> >> +DEF_HELPER_2(tlb_flush_pid, void, env, i32)
> >> +DEF_HELPER_2(spc_write, void, env, i32)
> >> DEF_HELPER_3(dump, void, i32, i32, i32)
> >> -DEF_HELPER_0(rfe, void);
> >> -DEF_HELPER_0(rfn, void);
> >> +DEF_HELPER_1(rfe, void, env);
> >> +DEF_HELPER_1(rfn, void, env);
> >>
> >> -DEF_HELPER_2(movl_sreg_reg, void, i32, i32)
> >> -DEF_HELPER_2(movl_reg_sreg, void, i32, i32)
> >> +DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32)
> >> +DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32)
> >>
> >> DEF_HELPER_FLAGS_1(lz, TCG_CALL_PURE, i32, i32);
> >> -DEF_HELPER_FLAGS_3(btst, TCG_CALL_PURE, i32, i32, i32, i32);
> >> +DEF_HELPER_FLAGS_4(btst, TCG_CALL_PURE, i32, env, i32, i32, i32);
> >>
> >> -DEF_HELPER_FLAGS_3(evaluate_flags_muls, TCG_CALL_PURE, i32, i32, i32, i32)
> >> -DEF_HELPER_FLAGS_3(evaluate_flags_mulu, TCG_CALL_PURE, i32, i32, i32, i32)
> >> -DEF_HELPER_FLAGS_4(evaluate_flags_mcp, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> >> -DEF_HELPER_FLAGS_4(evaluate_flags_alu_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> >> -DEF_HELPER_FLAGS_4(evaluate_flags_sub_4, TCG_CALL_PURE, i32, i32, i32, i32, i32)
> >> -DEF_HELPER_FLAGS_2(evaluate_flags_move_4, TCG_CALL_PURE, i32, i32, i32)
> >> -DEF_HELPER_FLAGS_2(evaluate_flags_move_2, TCG_CALL_PURE, i32, i32, i32)
> >> -DEF_HELPER_0(evaluate_flags, void)
> >> -DEF_HELPER_0(top_evaluate_flags, void)
> >> +DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_PURE, i32, env, i32, i32, i32)
> >> +DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_PURE, i32, env, i32, i32, i32)
> >> +DEF_HELPER_FLAGS_5(evaluate_flags_mcp, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> >> +DEF_HELPER_FLAGS_5(evaluate_flags_alu_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> >> +DEF_HELPER_FLAGS_5(evaluate_flags_sub_4, TCG_CALL_PURE, i32, env, i32, i32, i32, i32)
> >> +DEF_HELPER_FLAGS_3(evaluate_flags_move_4, TCG_CALL_PURE, i32, env, i32, i32)
> >> +DEF_HELPER_FLAGS_3(evaluate_flags_move_2, TCG_CALL_PURE, i32, env, i32, i32)
> >> +DEF_HELPER_1(evaluate_flags, void, env)
> >> +DEF_HELPER_1(top_evaluate_flags, void, env)
> >>
> >> #include "def-helper.h"
> >> diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> >> index ac7c98c..5cce3e7 100644
> >> --- a/target-cris/op_helper.c
> >> +++ b/target-cris/op_helper.c
> >> @@ -19,7 +19,6 @@
> >> */
> >>
> >> #include "cpu.h"
> >> -#include "dyngen-exec.h"
> >> #include "mmu.h"
> >> #include "helper.h"
> >> #include "host-utils.h"
> >> @@ -55,17 +54,12 @@
> >> /* Try to fill the TLB and return an exception if error. If retaddr is
> >> NULL, it means that the function was called in C code (i.e. not
> >> from generated code or from helper.c) */
> >> -/* XXX: fix it to restore all registers */
> >> -void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
> >> +void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
> >> uintptr_t retaddr)
> >> {
> >> TranslationBlock *tb;
> >> - CPUCRISState *saved_env;
> >> int ret;
> >>
> >> - saved_env = env;
> >> - env = env1;
> >> -
> >> D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
> >> env->pc, env->debug1, (void *)retaddr);
> >> ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
> >> @@ -79,23 +73,22 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
> >> cpu_restore_state(tb, env, retaddr);
> >>
> >> /* Evaluate flags after retranslation. */
> >> - helper_top_evaluate_flags();
> >> + helper_top_evaluate_flags(env);
> >> }
> >> }
> >> cpu_loop_exit(env);
> >> }
> >> - env = saved_env;
> >> }
> >>
> >> #endif
> >>
> >> -void helper_raise_exception(uint32_t index)
> >> +void helper_raise_exception(CPUCRISState *env, uint32_t index)
> >> {
> >> env->exception_index = index;
> >> cpu_loop_exit(env);
> >> }
> >>
> >> -void helper_tlb_flush_pid(uint32_t pid)
> >> +void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
> >> {
> >> #if !defined(CONFIG_USER_ONLY)
> >> pid &= 0xff;
> >> @@ -104,7 +97,7 @@ void helper_tlb_flush_pid(uint32_t pid)
> >> #endif
> >> }
> >>
> >> -void helper_spc_write(uint32_t new_spc)
> >> +void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
> >> {
> >> #if !defined(CONFIG_USER_ONLY)
> >> tlb_flush_page(env, env->pregs[PR_SPC]);
> >> @@ -121,7 +114,7 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
> >> #define EXTRACT_FIELD(src, start, end) \
> >> (((src) >> start) & ((1 << (end - start + 1)) - 1))
> >>
> >> -void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
> >> +void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
> >> {
> >> uint32_t srs;
> >> srs = env->pregs[PR_SRS];
> >> @@ -171,7 +164,7 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
> >> #endif
> >> }
> >>
> >> -void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
> >> +void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
> >> {
> >> uint32_t srs;
> >> env->pregs[PR_SRS] &= 3;
> >> @@ -216,7 +209,7 @@ static void cris_ccs_rshift(CPUCRISState *env)
> >> env->pregs[PR_CCS] = ccs;
> >> }
> >>
> >> -void helper_rfe(void)
> >> +void helper_rfe(CPUCRISState *env)
> >> {
> >> int rflag = env->pregs[PR_CCS] & R_FLAG;
> >>
> >> @@ -232,7 +225,7 @@ void helper_rfe(void)
> >> env->pregs[PR_CCS] |= P_FLAG;
> >> }
> >>
> >> -void helper_rfn(void)
> >> +void helper_rfn(CPUCRISState *env)
> >> {
> >> int rflag = env->pregs[PR_CCS] & R_FLAG;
> >>
> >> @@ -256,7 +249,7 @@ uint32_t helper_lz(uint32_t t0)
> >> return clz32(t0);
> >> }
> >>
> >> -uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
> >> +uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
> >> {
> >> /* FIXME: clean this up. */
> >>
> >> @@ -284,7 +277,8 @@ uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
> >> return ccs;
> >> }
> >>
> >> -static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
> >> +static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
> >> + uint32_t flags, uint32_t ccs)
> >> {
> >> unsigned int x, z, mask;
> >>
> >> @@ -303,7 +297,8 @@ static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
> >> return ccs;
> >> }
> >>
> >> -uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
> >> +uint32_t helper_evaluate_flags_muls(CPUCRISState *env, uint32_t ccs,
> >> + uint32_t res, uint32_t mof)
> >> {
> >> uint32_t flags = 0;
> >> int64_t tmp;
> >> @@ -321,10 +316,11 @@ uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
> >> if ((dneg && mof != -1)
> >> || (!dneg && mof != 0))
> >> flags |= V_FLAG;
> >> - return evaluate_flags_writeback(flags, ccs);
> >> + return evaluate_flags_writeback(env, flags, ccs);
> >> }
> >>
> >> -uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
> >> +uint32_t helper_evaluate_flags_mulu(CPUCRISState *env, uint32_t ccs,
> >> + uint32_t res, uint32_t mof)
> >> {
> >> uint32_t flags = 0;
> >> uint64_t tmp;
> >> @@ -339,10 +335,10 @@ uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
> >> if (mof)
> >> flags |= V_FLAG;
> >>
> >> - return evaluate_flags_writeback(flags, ccs);
> >> + return evaluate_flags_writeback(env, flags, ccs);
> >> }
> >>
> >> -uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
> >> +uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
> >> uint32_t src, uint32_t dst, uint32_t res)
> >> {
> >> uint32_t flags = 0;
> >> @@ -368,10 +364,10 @@ uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
> >> flags |= R_FLAG;
> >> }
> >>
> >> - return evaluate_flags_writeback(flags, ccs);
> >> + return evaluate_flags_writeback(env, flags, ccs);
> >> }
> >>
> >> -uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
> >> +uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
> >> uint32_t src, uint32_t dst, uint32_t res)
> >> {
> >> uint32_t flags = 0;
> >> @@ -397,10 +393,10 @@ uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
> >> flags |= C_FLAG;
> >> }
> >>
> >> - return evaluate_flags_writeback(flags, ccs);
> >> + return evaluate_flags_writeback(env, flags, ccs);
> >> }
> >>
> >> -uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
> >> +uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
> >> uint32_t src, uint32_t dst, uint32_t res)
> >> {
> >> uint32_t flags = 0;
> >> @@ -427,10 +423,11 @@ uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
> >> }
> >>
> >> flags ^= C_FLAG;
> >> - return evaluate_flags_writeback(flags, ccs);
> >> + return evaluate_flags_writeback(env, flags, ccs);
> >> }
> >>
> >> -uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
> >> +uint32_t helper_evaluate_flags_move_4(CPUCRISState *env, uint32_t ccs,
> >> + uint32_t res)
> >> {
> >> uint32_t flags = 0;
> >>
> >> @@ -439,9 +436,10 @@ uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
> >> else if (res == 0L)
> >> flags |= Z_FLAG;
> >>
> >> - return evaluate_flags_writeback(flags, ccs);
> >> + return evaluate_flags_writeback(env, flags, ccs);
> >> }
> >> -uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
> >> +uint32_t helper_evaluate_flags_move_2(CPUCRISState *env, uint32_t ccs,
> >> + uint32_t res)
> >> {
> >> uint32_t flags = 0;
> >>
> >> @@ -450,12 +448,12 @@ uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
> >> else if (res == 0)
> >> flags |= Z_FLAG;
> >>
> >> - return evaluate_flags_writeback(flags, ccs);
> >> + return evaluate_flags_writeback(env, flags, ccs);
> >> }
> >>
> >> /* TODO: This is expensive. We could split things up and only evaluate part of
> >> CCR on a need to know basis. For now, we simply re-evaluate everything. */
> >> -void helper_evaluate_flags(void)
> >> +void helper_evaluate_flags(CPUCRISState *env)
> >> {
> >> uint32_t src, dst, res;
> >> uint32_t flags = 0;
> >> @@ -571,25 +569,26 @@ void helper_evaluate_flags(void)
> >> if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
> >> flags ^= C_FLAG;
> >>
> >> - env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
> >> + env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
> >> + env->pregs[PR_CCS]);
> >> }
> >>
> >> -void helper_top_evaluate_flags(void)
> >> +void helper_top_evaluate_flags(CPUCRISState *env)
> >> {
> >> switch (env->cc_op)
> >> {
> >> case CC_OP_MCP:
> >> - env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
> >> + env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
> >> env->pregs[PR_CCS], env->cc_src,
> >> env->cc_dest, env->cc_result);
> >> break;
> >> case CC_OP_MULS:
> >> - env->pregs[PR_CCS] = helper_evaluate_flags_muls(
> >> + env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
> >> env->pregs[PR_CCS], env->cc_result,
> >> env->pregs[PR_MOF]);
> >> break;
> >> case CC_OP_MULU:
> >> - env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
> >> + env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
> >> env->pregs[PR_CCS], env->cc_result,
> >> env->pregs[PR_MOF]);
> >> break;
> >> @@ -604,18 +603,18 @@ void helper_top_evaluate_flags(void)
> >> {
> >> case 4:
> >> env->pregs[PR_CCS] =
> >> - helper_evaluate_flags_move_4(
> >> + helper_evaluate_flags_move_4(env,
> >> env->pregs[PR_CCS],
> >> env->cc_result);
> >> break;
> >> case 2:
> >> env->pregs[PR_CCS] =
> >> - helper_evaluate_flags_move_2(
> >> + helper_evaluate_flags_move_2(env,
> >> env->pregs[PR_CCS],
> >> env->cc_result);
> >> break;
> >> default:
> >> - helper_evaluate_flags();
> >> + helper_evaluate_flags(env);
> >> break;
> >> }
> >> break;
> >> @@ -626,12 +625,12 @@ void helper_top_evaluate_flags(void)
> >> case CC_OP_CMP:
> >> if (env->cc_size == 4)
> >> env->pregs[PR_CCS] =
> >> - helper_evaluate_flags_sub_4(
> >> + helper_evaluate_flags_sub_4(env,
> >> env->pregs[PR_CCS],
> >> env->cc_src, env->cc_dest,
> >> env->cc_result);
> >> else
> >> - helper_evaluate_flags();
> >> + helper_evaluate_flags(env);
> >> break;
> >> default:
> >> {
> >> @@ -639,13 +638,13 @@ void helper_top_evaluate_flags(void)
> >> {
> >> case 4:
> >> env->pregs[PR_CCS] =
> >> - helper_evaluate_flags_alu_4(
> >> + helper_evaluate_flags_alu_4(env,
> >> env->pregs[PR_CCS],
> >> env->cc_src, env->cc_dest,
> >> env->cc_result);
> >> break;
> >> default:
> >> - helper_evaluate_flags();
> >> + helper_evaluate_flags(env);
> >> break;
> >> }
> >> }
> >> diff --git a/target-cris/translate.c b/target-cris/translate.c
> >> index 1ad9ec7..5e4f7f5 100644
> >> --- a/target-cris/translate.c
> >> +++ b/target-cris/translate.c
> >> @@ -211,9 +211,9 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
> >> tcg_gen_andi_tl(cpu_PR[r], tn, 3);
> >> else {
> >> if (r == PR_PID)
> >> - gen_helper_tlb_flush_pid(tn);
> >> + gen_helper_tlb_flush_pid(cpu_env, tn);
> >> if (dc->tb_flags & S_FLAG && r == PR_SPC)
> >> - gen_helper_spc_write(tn);
> >> + gen_helper_spc_write(cpu_env, tn);
> >> else if (r == PR_CCS)
> >> dc->cpustate_changed = 1;
> >> tcg_gen_mov_tl(cpu_PR[r], tn);
> >> @@ -241,24 +241,24 @@ static int cris_fetch(DisasContext *dc, uint32_t addr,
> >> switch (size) {
> >> case 4:
> >> {
> >> - r = ldl_code(addr);
> >> + r = cpu_ldl_code(cpu_single_env, addr);
> >> break;
> >> }
> >> case 2:
> >> {
> >> if (sign) {
> >> - r = ldsw_code(addr);
> >> + r = cpu_ldsw_code(cpu_single_env, addr);
> >> } else {
> >> - r = lduw_code(addr);
> >> + r = cpu_lduw_code(cpu_single_env, addr);
> >> }
> >> break;
> >> }
> >> case 1:
> >> {
> >> if (sign) {
> >> - r = ldsb_code(addr);
> >> + r = cpu_ldsb_code(cpu_single_env, addr);
> >> } else {
> >> - r = ldub_code(addr);
> >> + r = cpu_ldub_code(cpu_single_env, addr);
> >> }
> >> break;
> >> }
> >> @@ -278,7 +278,7 @@ static void cris_lock_irq(DisasContext *dc)
> >> static inline void t_gen_raise_exception(uint32_t index)
> >> {
> >> TCGv_i32 tmp = tcg_const_i32(index);
> >> - gen_helper_raise_exception(tmp);
> >> + gen_helper_raise_exception(cpu_env, tmp);
> >> tcg_temp_free_i32(tmp);
> >> }
> >>
> >> @@ -624,17 +624,17 @@ static void cris_evaluate_flags(DisasContext *dc)
> >> switch (dc->cc_op)
> >> {
> >> case CC_OP_MCP:
> >> - gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
> >> + gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
> >> cpu_PR[PR_CCS], cc_src,
> >> cc_dest, cc_result);
> >> break;
> >> case CC_OP_MULS:
> >> - gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
> >> + gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
> >> cpu_PR[PR_CCS], cc_result,
> >> cpu_PR[PR_MOF]);
> >> break;
> >> case CC_OP_MULU:
> >> - gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
> >> + gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
> >> cpu_PR[PR_CCS], cc_result,
> >> cpu_PR[PR_MOF]);
> >> break;
> >> @@ -648,15 +648,15 @@ static void cris_evaluate_flags(DisasContext *dc)
> >> switch (dc->cc_size)
> >> {
> >> case 4:
> >> - gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
> >> + gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], cpu_env,
> >> cpu_PR[PR_CCS], cc_result);
> >> break;
> >> case 2:
> >> - gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
> >> + gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], cpu_env,
> >> cpu_PR[PR_CCS], cc_result);
> >> break;
> >> default:
> >> - gen_helper_evaluate_flags();
> >> + gen_helper_evaluate_flags(cpu_env);
> >> break;
> >> }
> >> break;
> >> @@ -666,21 +666,21 @@ static void cris_evaluate_flags(DisasContext *dc)
> >> case CC_OP_SUB:
> >> case CC_OP_CMP:
> >> if (dc->cc_size == 4)
> >> - gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
> >> + gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
> >> cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
> >> else
> >> - gen_helper_evaluate_flags();
> >> + gen_helper_evaluate_flags(cpu_env);
> >>
> >> break;
> >> default:
> >> switch (dc->cc_size)
> >> {
> >> case 4:
> >> - gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
> >> + gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
> >> cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
> >> break;
> >> default:
> >> - gen_helper_evaluate_flags();
> >> + gen_helper_evaluate_flags(cpu_env);
> >> break;
> >> }
> >> break;
> >> @@ -1475,7 +1475,7 @@ static int dec_btstq(DisasContext *dc)
> >>
> >> cris_cc_mask(dc, CC_MASK_NZ);
> >> cris_evaluate_flags(dc);
> >> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
> >> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
> >> tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
> >> cris_alu(dc, CC_OP_MOVE,
> >> cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
> >> @@ -1925,7 +1925,7 @@ static int dec_btst_r(DisasContext *dc)
> >> dc->op1, dc->op2);
> >> cris_cc_mask(dc, CC_MASK_NZ);
> >> cris_evaluate_flags(dc);
> >> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
> >> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
> >> cpu_R[dc->op1], cpu_PR[PR_CCS]);
> >> cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
> >> cpu_R[dc->op2], cpu_R[dc->op2], 4);
> >> @@ -2135,14 +2135,16 @@ static int dec_move_rs(DisasContext *dc)
> >> {
> >> LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
> >> cris_cc_mask(dc, 0);
> >> - gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
> >> + gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
> >> + tcg_const_tl(dc->op1));
> >> return 2;
> >> }
> >> static int dec_move_sr(DisasContext *dc)
> >> {
> >> LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
> >> cris_cc_mask(dc, 0);
> >> - gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
> >> + gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
> >> + tcg_const_tl(dc->op2));
> >> return 2;
> >> }
> >>
> >> @@ -2906,14 +2908,14 @@ static int dec_rfe_etc(DisasContext *dc)
> >> /* rfe. */
> >> LOG_DIS("rfe\n");
> >> cris_evaluate_flags(dc);
> >> - gen_helper_rfe();
> >> + gen_helper_rfe(cpu_env);
> >> dc->is_jmp = DISAS_UPDATE;
> >> break;
> >> case 5:
> >> /* rfn. */
> >> LOG_DIS("rfn\n");
> >> cris_evaluate_flags(dc);
> >> - gen_helper_rfn();
> >> + gen_helper_rfn(cpu_env);
> >> dc->is_jmp = DISAS_UPDATE;
> >> break;
> >> case 6:
> >> diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
> >> index 3629629..d9d6aa5 100644
> >> --- a/target-cris/translate_v10.c
> >> +++ b/target-cris/translate_v10.c
> >> @@ -182,17 +182,17 @@ static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize,
> >> if (memsize != 4) {
> >> if (s_ext) {
> >> if (memsize == 1)
> >> - imm = ldsb_code(dc->pc + 2);
> >> + imm = cpu_ldsb_code(cpu_single_env, dc->pc + 2);
> >> else
> >> - imm = ldsw_code(dc->pc + 2);
> >> + imm = cpu_ldsw_code(cpu_single_env, dc->pc + 2);
> >> } else {
> >> if (memsize == 1)
> >> - imm = ldub_code(dc->pc + 2);
> >> + imm = cpu_ldub_code(cpu_single_env, dc->pc + 2);
> >> else
> >> - imm = lduw_code(dc->pc + 2);
> >> + imm = cpu_lduw_code(cpu_single_env, dc->pc + 2);
> >> }
> >> } else
> >> - imm = ldl_code(dc->pc + 2);
> >> + imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
> >>
> >> tcg_gen_movi_tl(dst, imm);
> >
> > Similarly to what I reported for the microblaze and sh4 target, I think
> > we should not start using cpu_single_env (a global variable) to replace
> > env (a global variable stored in a register).
>
> This task could be also taken to a different patch series, because the
> conversions committed earlier also used cpu_single_env.
>
> Eliminating cpu_single_env altogether may be possible but it would
> need some refactoring.
>
> >
> > It is possible to pass env through the subroutine, though it is more
> > complicated there than for other targets. I have therefore done the work
> > and I have attached the two resulting patches to this mail.
>
> Thank you for the work, the patches look better. I think the patches
> should also include my sign-off.
No problem. Feel free to add it and take these patches in your series.
> >
> >> @@ -289,7 +289,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
> >> } else {
> >> /* BTST */
> >> cris_update_cc_op(dc, CC_OP_FLAGS, 4);
> >> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
> >> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
> >> tcg_const_tl(imm), cpu_PR[PR_CCS]);
> >> }
> >> break;
> >> @@ -723,7 +723,7 @@ static unsigned int dec10_reg(DisasContext *dc)
> >> LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
> >> cris_cc_mask(dc, CC_MASK_NZVC);
> >> cris_update_cc_op(dc, CC_OP_FLAGS, 4);
> >> - gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst],
> >> + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
> >> cpu_R[dc->src], cpu_PR[PR_CCS]);
> >> break;
> >> case CRISV10_REG_DSTEP:
> >> @@ -974,7 +974,7 @@ static int dec10_dip(DisasContext *dc)
> >> LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
> >> dc->pc, dc->opcode, dc->src, dc->dst);
> >> if (dc->src == 15) {
> >> - imm = ldl_code(dc->pc + 2);
> >> + imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
> >> tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
> >> if (dc->postinc)
> >> insn_len += 4;
> >> @@ -1119,7 +1119,7 @@ static unsigned int dec10_ind(DisasContext *dc)
> >> if (dc->src == 15) {
> >> LOG_DIS("jump.%d %d r%d r%d direct\n", size,
> >> dc->opcode, dc->src, dc->dst);
> >> - imm = ldl_code(dc->pc + 2);
> >> + imm = cpu_ldl_code(cpu_single_env, dc->pc + 2);
> >> if (dc->mode == CRISV10_MODE_AUTOINC)
> >> insn_len += size;
> >>
> >> @@ -1185,7 +1185,7 @@ static unsigned int dec10_ind(DisasContext *dc)
> >> case CRISV10_IND_BCC_M:
> >>
> >> cris_cc_mask(dc, 0);
> >> - imm = ldsw_code(dc->pc + 2);
> >> + imm = cpu_ldsw_code(cpu_single_env, dc->pc + 2);
> >> simm = (int16_t)imm;
> >> simm += 4;
> >>
> >> @@ -1210,7 +1210,7 @@ static unsigned int crisv10_decoder(DisasContext *dc)
> >> tcg_gen_debug_insn_start(dc->pc);
> >>
> >> /* Load a halfword onto the instruction register. */
> >> - dc->ir = lduw_code(dc->pc);
> >> + dc->ir = cpu_lduw_code(cpu_single_env, dc->pc);
> >>
> >> /* Now decode it. */
> >> dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
> >> --
> >> 1.7.2.5
> >>
> >>
> >>
> >
> > --
> > Aurelien Jarno GPG: 1024D/F1BCDB73
> > aurelien@aurel32.net http://www.aurel32.net
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread
* [Qemu-devel] [PATCH 19/21] target-sh4: switch to AREG0 free mode
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (17 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 18/21] target-cris: " Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-02 23:42 ` Aurelien Jarno
2012-09-02 17:33 ` [Qemu-devel] [PATCH 20/21] target-mips: " Blue Swirl
` (2 subsequent siblings)
21 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Aurelien Jarno
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
configure | 2 +-
target-sh4/Makefile.objs | 2 -
target-sh4/helper.h | 84 +++++++++++-----------
target-sh4/op_helper.c | 182 ++++++++++++++++++++++-----------------------
target-sh4/translate.c | 114 ++++++++++++++++-------------
5 files changed, 195 insertions(+), 189 deletions(-)
diff --git a/configure b/configure
index d760e07..d69e43e 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
case "$target_arch2" in
- alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
+ alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sh4* | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
;;
esac
diff --git a/target-sh4/Makefile.objs b/target-sh4/Makefile.objs
index 2e0e093..ca20f21 100644
--- a/target-sh4/Makefile.objs
+++ b/target-sh4/Makefile.objs
@@ -1,4 +1,2 @@
obj-y += translate.o op_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-sh4/helper.h b/target-sh4/helper.h
index 95e3c7c..6e4f108 100644
--- a/target-sh4/helper.h
+++ b/target-sh4/helper.h
@@ -1,54 +1,54 @@
#include "def-helper.h"
-DEF_HELPER_0(ldtlb, void)
-DEF_HELPER_0(raise_illegal_instruction, void)
-DEF_HELPER_0(raise_slot_illegal_instruction, void)
-DEF_HELPER_0(raise_fpu_disable, void)
-DEF_HELPER_0(raise_slot_fpu_disable, void)
-DEF_HELPER_0(debug, void)
-DEF_HELPER_1(sleep, void, i32)
-DEF_HELPER_1(trapa, void, i32)
+DEF_HELPER_1(ldtlb, void, env)
+DEF_HELPER_1(raise_illegal_instruction, void, env)
+DEF_HELPER_1(raise_slot_illegal_instruction, void, env)
+DEF_HELPER_1(raise_fpu_disable, void, env)
+DEF_HELPER_1(raise_slot_fpu_disable, void, env)
+DEF_HELPER_1(debug, void, env)
+DEF_HELPER_2(sleep, void, env, i32)
+DEF_HELPER_2(trapa, void, env, i32)
-DEF_HELPER_2(movcal, void, i32, i32)
-DEF_HELPER_0(discard_movcal_backup, void)
-DEF_HELPER_1(ocbi, void, i32)
+DEF_HELPER_3(movcal, void, env, i32, i32)
+DEF_HELPER_1(discard_movcal_backup, void, env)
+DEF_HELPER_2(ocbi, void, env, i32)
-DEF_HELPER_2(addv, i32, i32, i32)
-DEF_HELPER_2(addc, i32, i32, i32)
-DEF_HELPER_2(subv, i32, i32, i32)
-DEF_HELPER_2(subc, i32, i32, i32)
-DEF_HELPER_2(div1, i32, i32, i32)
-DEF_HELPER_2(macl, void, i32, i32)
-DEF_HELPER_2(macw, void, i32, i32)
+DEF_HELPER_3(addv, i32, env, i32, i32)
+DEF_HELPER_3(addc, i32, env, i32, i32)
+DEF_HELPER_3(subv, i32, env, i32, i32)
+DEF_HELPER_3(subc, i32, env, i32, i32)
+DEF_HELPER_3(div1, i32, env, i32, i32)
+DEF_HELPER_3(macl, void, env, i32, i32)
+DEF_HELPER_3(macw, void, env, i32, i32)
-DEF_HELPER_1(ld_fpscr, void, i32)
+DEF_HELPER_2(ld_fpscr, void, env, i32)
DEF_HELPER_1(fabs_FT, f32, f32)
DEF_HELPER_1(fabs_DT, f64, f64)
-DEF_HELPER_2(fadd_FT, f32, f32, f32)
-DEF_HELPER_2(fadd_DT, f64, f64, f64)
-DEF_HELPER_1(fcnvsd_FT_DT, f64, f32)
-DEF_HELPER_1(fcnvds_DT_FT, f32, f64)
+DEF_HELPER_3(fadd_FT, f32, env, f32, f32)
+DEF_HELPER_3(fadd_DT, f64, env, f64, f64)
+DEF_HELPER_2(fcnvsd_FT_DT, f64, env, f32)
+DEF_HELPER_2(fcnvds_DT_FT, f32, env, f64)
-DEF_HELPER_2(fcmp_eq_FT, void, f32, f32)
-DEF_HELPER_2(fcmp_eq_DT, void, f64, f64)
-DEF_HELPER_2(fcmp_gt_FT, void, f32, f32)
-DEF_HELPER_2(fcmp_gt_DT, void, f64, f64)
-DEF_HELPER_2(fdiv_FT, f32, f32, f32)
-DEF_HELPER_2(fdiv_DT, f64, f64, f64)
-DEF_HELPER_1(float_FT, f32, i32)
-DEF_HELPER_1(float_DT, f64, i32)
-DEF_HELPER_3(fmac_FT, f32, f32, f32, f32)
-DEF_HELPER_2(fmul_FT, f32, f32, f32)
-DEF_HELPER_2(fmul_DT, f64, f64, f64)
+DEF_HELPER_3(fcmp_eq_FT, void, env, f32, f32)
+DEF_HELPER_3(fcmp_eq_DT, void, env, f64, f64)
+DEF_HELPER_3(fcmp_gt_FT, void, env, f32, f32)
+DEF_HELPER_3(fcmp_gt_DT, void, env, f64, f64)
+DEF_HELPER_3(fdiv_FT, f32, env, f32, f32)
+DEF_HELPER_3(fdiv_DT, f64, env, f64, f64)
+DEF_HELPER_2(float_FT, f32, env, i32)
+DEF_HELPER_2(float_DT, f64, env, i32)
+DEF_HELPER_4(fmac_FT, f32, env, f32, f32, f32)
+DEF_HELPER_3(fmul_FT, f32, env, f32, f32)
+DEF_HELPER_3(fmul_DT, f64, env, f64, f64)
DEF_HELPER_1(fneg_T, f32, f32)
-DEF_HELPER_2(fsub_FT, f32, f32, f32)
-DEF_HELPER_2(fsub_DT, f64, f64, f64)
-DEF_HELPER_1(fsqrt_FT, f32, f32)
-DEF_HELPER_1(fsqrt_DT, f64, f64)
-DEF_HELPER_1(ftrc_FT, i32, f32)
-DEF_HELPER_1(ftrc_DT, i32, f64)
-DEF_HELPER_2(fipr, void, i32, i32)
-DEF_HELPER_1(ftrv, void, i32)
+DEF_HELPER_3(fsub_FT, f32, env, f32, f32)
+DEF_HELPER_3(fsub_DT, f64, env, f64, f64)
+DEF_HELPER_2(fsqrt_FT, f32, env, f32)
+DEF_HELPER_2(fsqrt_DT, f64, env, f64)
+DEF_HELPER_2(ftrc_FT, i32, env, f32)
+DEF_HELPER_2(ftrc_DT, i32, env, f64)
+DEF_HELPER_3(fipr, void, env, i32, i32)
+DEF_HELPER_2(ftrv, void, env, i32)
#include "def-helper.h"
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 4054791..9b4328d 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -19,10 +19,9 @@
#include <assert.h>
#include <stdlib.h>
#include "cpu.h"
-#include "dyngen-exec.h"
#include "helper.h"
-static void cpu_restore_state_from_retaddr(uintptr_t retaddr)
+static void cpu_restore_state_from_retaddr(CPUSH4State *env, uintptr_t retaddr)
{
TranslationBlock *tb;
@@ -53,26 +52,22 @@ static void cpu_restore_state_from_retaddr(uintptr_t retaddr)
#define SHIFT 3
#include "softmmu_template.h"
-void tlb_fill(CPUSH4State *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- CPUSH4State *saved_env;
int ret;
- saved_env = env;
- env = env1;
ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (ret) {
/* now we have a real cpu fault */
- cpu_restore_state_from_retaddr(retaddr);
+ cpu_restore_state_from_retaddr(env, retaddr);
cpu_loop_exit(env);
}
- env = saved_env;
}
#endif
-void helper_ldtlb(void)
+void helper_ldtlb(CPUSH4State *env)
{
#ifdef CONFIG_USER_ONLY
/* XXXXX */
@@ -82,40 +77,41 @@ void helper_ldtlb(void)
#endif
}
-static inline void raise_exception(int index, uintptr_t retaddr)
+static inline void raise_exception(CPUSH4State *env, int index,
+ uintptr_t retaddr)
{
env->exception_index = index;
- cpu_restore_state_from_retaddr(retaddr);
+ cpu_restore_state_from_retaddr(env, retaddr);
cpu_loop_exit(env);
}
-void helper_raise_illegal_instruction(void)
+void helper_raise_illegal_instruction(CPUSH4State *env)
{
- raise_exception(0x180, GETPC());
+ raise_exception(env, 0x180, GETPC());
}
-void helper_raise_slot_illegal_instruction(void)
+void helper_raise_slot_illegal_instruction(CPUSH4State *env)
{
- raise_exception(0x1a0, GETPC());
+ raise_exception(env, 0x1a0, GETPC());
}
-void helper_raise_fpu_disable(void)
+void helper_raise_fpu_disable(CPUSH4State *env)
{
- raise_exception(0x800, GETPC());
+ raise_exception(env, 0x800, GETPC());
}
-void helper_raise_slot_fpu_disable(void)
+void helper_raise_slot_fpu_disable(CPUSH4State *env)
{
- raise_exception(0x820, GETPC());
+ raise_exception(env, 0x820, GETPC());
}
-void helper_debug(void)
+void helper_debug(CPUSH4State *env)
{
env->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);
}
-void helper_sleep(uint32_t next_pc)
+void helper_sleep(CPUSH4State *env, uint32_t next_pc)
{
env->halted = 1;
env->in_sleep = 1;
@@ -124,13 +120,13 @@ void helper_sleep(uint32_t next_pc)
cpu_loop_exit(env);
}
-void helper_trapa(uint32_t tra)
+void helper_trapa(CPUSH4State *env, uint32_t tra)
{
env->tra = tra << 2;
- raise_exception(0x160, GETPC());
+ raise_exception(env, 0x160, GETPC());
}
-void helper_movcal(uint32_t address, uint32_t value)
+void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
{
if (cpu_sh4_is_cached (env, address))
{
@@ -144,7 +140,7 @@ void helper_movcal(uint32_t address, uint32_t value)
}
}
-void helper_discard_movcal_backup(void)
+void helper_discard_movcal_backup(CPUSH4State *env)
{
memory_content *current = env->movcal_backup;
@@ -158,7 +154,7 @@ void helper_discard_movcal_backup(void)
}
}
-void helper_ocbi(uint32_t address)
+void helper_ocbi(CPUSH4State *env, uint32_t address)
{
memory_content **current = &(env->movcal_backup);
while (*current)
@@ -167,7 +163,7 @@ void helper_ocbi(uint32_t address)
if ((a & ~0x1F) == (address & ~0x1F))
{
memory_content *next = (*current)->next;
- stl(a, (*current)->value);
+ cpu_stl_data(env, a, (*current)->value);
if (next == NULL)
{
@@ -181,7 +177,7 @@ void helper_ocbi(uint32_t address)
}
}
-uint32_t helper_addc(uint32_t arg0, uint32_t arg1)
+uint32_t helper_addc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
uint32_t tmp0, tmp1;
@@ -197,7 +193,7 @@ uint32_t helper_addc(uint32_t arg0, uint32_t arg1)
return arg1;
}
-uint32_t helper_addv(uint32_t arg0, uint32_t arg1)
+uint32_t helper_addv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
uint32_t dest, src, ans;
@@ -236,7 +232,7 @@ uint32_t helper_addv(uint32_t arg0, uint32_t arg1)
#define SETM env->sr |= SR_M
#define CLRM env->sr &= ~SR_M
-uint32_t helper_div1(uint32_t arg0, uint32_t arg1)
+uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
uint32_t tmp0, tmp2;
uint8_t old_q, tmp1 = 0xff;
@@ -344,7 +340,7 @@ uint32_t helper_div1(uint32_t arg0, uint32_t arg1)
return arg1;
}
-void helper_macl(uint32_t arg0, uint32_t arg1)
+void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
int64_t res;
@@ -360,7 +356,7 @@ void helper_macl(uint32_t arg0, uint32_t arg1)
}
}
-void helper_macw(uint32_t arg0, uint32_t arg1)
+void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
int64_t res;
@@ -379,7 +375,7 @@ void helper_macw(uint32_t arg0, uint32_t arg1)
}
}
-uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
+uint32_t helper_subc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
uint32_t tmp0, tmp1;
@@ -395,7 +391,7 @@ uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
return arg1;
}
-uint32_t helper_subv(uint32_t arg0, uint32_t arg1)
+uint32_t helper_subv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
int32_t dest, src, ans;
@@ -424,17 +420,17 @@ uint32_t helper_subv(uint32_t arg0, uint32_t arg1)
return arg1;
}
-static inline void set_t(void)
+static inline void set_t(CPUSH4State *env)
{
env->sr |= SR_T;
}
-static inline void clr_t(void)
+static inline void clr_t(CPUSH4State *env)
{
env->sr &= ~SR_T;
}
-void helper_ld_fpscr(uint32_t val)
+void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
{
env->fpscr = val & FPSCR_MASK;
if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
@@ -445,7 +441,7 @@ void helper_ld_fpscr(uint32_t val)
set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
}
-static void update_fpscr(uintptr_t retaddr)
+static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
{
int xcpt, cause, enable;
@@ -479,7 +475,7 @@ static void update_fpscr(uintptr_t retaddr)
cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
if (cause & enable) {
- cpu_restore_state_from_retaddr(retaddr);
+ cpu_restore_state_from_retaddr(env, retaddr);
env->exception_index = 0x120;
cpu_loop_exit(env);
}
@@ -496,156 +492,156 @@ float64 helper_fabs_DT(float64 t0)
return float64_abs(t0);
}
-float32 helper_fadd_FT(float32 t0, float32 t1)
+float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_add(t0, t1, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return t0;
}
-float64 helper_fadd_DT(float64 t0, float64 t1)
+float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float64_add(t0, t1, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return t0;
}
-void helper_fcmp_eq_FT(float32 t0, float32 t1)
+void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
{
int relation;
set_float_exception_flags(0, &env->fp_status);
relation = float32_compare(t0, t1, &env->fp_status);
if (unlikely(relation == float_relation_unordered)) {
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
} else if (relation == float_relation_equal) {
- set_t();
+ set_t(env);
} else {
- clr_t();
+ clr_t(env);
}
}
-void helper_fcmp_eq_DT(float64 t0, float64 t1)
+void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
{
int relation;
set_float_exception_flags(0, &env->fp_status);
relation = float64_compare(t0, t1, &env->fp_status);
if (unlikely(relation == float_relation_unordered)) {
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
} else if (relation == float_relation_equal) {
- set_t();
+ set_t(env);
} else {
- clr_t();
+ clr_t(env);
}
}
-void helper_fcmp_gt_FT(float32 t0, float32 t1)
+void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
{
int relation;
set_float_exception_flags(0, &env->fp_status);
relation = float32_compare(t0, t1, &env->fp_status);
if (unlikely(relation == float_relation_unordered)) {
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
} else if (relation == float_relation_greater) {
- set_t();
+ set_t(env);
} else {
- clr_t();
+ clr_t(env);
}
}
-void helper_fcmp_gt_DT(float64 t0, float64 t1)
+void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
{
int relation;
set_float_exception_flags(0, &env->fp_status);
relation = float64_compare(t0, t1, &env->fp_status);
if (unlikely(relation == float_relation_unordered)) {
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
} else if (relation == float_relation_greater) {
- set_t();
+ set_t(env);
} else {
- clr_t();
+ clr_t(env);
}
}
-float64 helper_fcnvsd_FT_DT(float32 t0)
+float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
{
float64 ret;
set_float_exception_flags(0, &env->fp_status);
ret = float32_to_float64(t0, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return ret;
}
-float32 helper_fcnvds_DT_FT(float64 t0)
+float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
{
float32 ret;
set_float_exception_flags(0, &env->fp_status);
ret = float64_to_float32(t0, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return ret;
}
-float32 helper_fdiv_FT(float32 t0, float32 t1)
+float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_div(t0, t1, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return t0;
}
-float64 helper_fdiv_DT(float64 t0, float64 t1)
+float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float64_div(t0, t1, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return t0;
}
-float32 helper_float_FT(uint32_t t0)
+float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
{
float32 ret;
set_float_exception_flags(0, &env->fp_status);
ret = int32_to_float32(t0, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return ret;
}
-float64 helper_float_DT(uint32_t t0)
+float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
{
float64 ret;
set_float_exception_flags(0, &env->fp_status);
ret = int32_to_float64(t0, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return ret;
}
-float32 helper_fmac_FT(float32 t0, float32 t1, float32 t2)
+float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_mul(t0, t1, &env->fp_status);
t0 = float32_add(t0, t2, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return t0;
}
-float32 helper_fmul_FT(float32 t0, float32 t1)
+float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_mul(t0, t1, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return t0;
}
-float64 helper_fmul_DT(float64 t0, float64 t1)
+float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float64_mul(t0, t1, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return t0;
}
@@ -654,57 +650,57 @@ float32 helper_fneg_T(float32 t0)
return float32_chs(t0);
}
-float32 helper_fsqrt_FT(float32 t0)
+float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_sqrt(t0, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return t0;
}
-float64 helper_fsqrt_DT(float64 t0)
+float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float64_sqrt(t0, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return t0;
}
-float32 helper_fsub_FT(float32 t0, float32 t1)
+float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_sub(t0, t1, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return t0;
}
-float64 helper_fsub_DT(float64 t0, float64 t1)
+float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float64_sub(t0, t1, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return t0;
}
-uint32_t helper_ftrc_FT(float32 t0)
+uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
{
uint32_t ret;
set_float_exception_flags(0, &env->fp_status);
ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return ret;
}
-uint32_t helper_ftrc_DT(float64 t0)
+uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
{
uint32_t ret;
set_float_exception_flags(0, &env->fp_status);
ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
return ret;
}
-void helper_fipr(uint32_t m, uint32_t n)
+void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
{
int bank, i;
float32 r, p;
@@ -719,12 +715,12 @@ void helper_fipr(uint32_t m, uint32_t n)
&env->fp_status);
r = float32_add(r, p, &env->fp_status);
}
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
env->fregs[bank + n + 3] = r;
}
-void helper_ftrv(uint32_t n)
+void helper_ftrv(CPUSH4State *env, uint32_t n)
{
int bank_matrix, bank_vector;
int i, j;
@@ -743,7 +739,7 @@ void helper_ftrv(uint32_t n)
r[i] = float32_add(r[i], p, &env->fp_status);
}
}
- update_fpscr(GETPC());
+ update_fpscr(env, GETPC());
for (i = 0 ; i < 4 ; i++) {
env->fregs[bank_vector + i] = r[i];
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 6532ad2..102b1b4 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -276,7 +276,7 @@ static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
} else {
tcg_gen_movi_i32(cpu_pc, dest);
if (ctx->singlestep_enabled)
- gen_helper_debug();
+ gen_helper_debug(cpu_env);
tcg_gen_exit_tb(0);
}
}
@@ -288,7 +288,7 @@ static void gen_jump(DisasContext * ctx)
delayed jump as immediate jump are conditinal jumps */
tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
if (ctx->singlestep_enabled)
- gen_helper_debug();
+ gen_helper_debug(cpu_env);
tcg_gen_exit_tb(0);
} else {
gen_goto_tb(ctx, 0, ctx->delayed_pc);
@@ -437,7 +437,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
#define CHECK_NOT_DELAY_SLOT \
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
{ \
- gen_helper_raise_slot_illegal_instruction(); \
+ gen_helper_raise_slot_illegal_instruction(cpu_env); \
ctx->bstate = BS_EXCP; \
return; \
}
@@ -445,9 +445,9 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
#define CHECK_PRIVILEGED \
if (IS_USER(ctx)) { \
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
- gen_helper_raise_slot_illegal_instruction(); \
+ gen_helper_raise_slot_illegal_instruction(cpu_env); \
} else { \
- gen_helper_raise_illegal_instruction(); \
+ gen_helper_raise_illegal_instruction(cpu_env); \
} \
ctx->bstate = BS_EXCP; \
return; \
@@ -456,9 +456,9 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
#define CHECK_FPU_ENABLED \
if (ctx->flags & SR_FD) { \
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
- gen_helper_raise_slot_fpu_disable(); \
+ gen_helper_raise_slot_fpu_disable(cpu_env); \
} else { \
- gen_helper_raise_fpu_disable(); \
+ gen_helper_raise_fpu_disable(cpu_env); \
} \
ctx->bstate = BS_EXCP; \
return; \
@@ -492,7 +492,7 @@ static void _decode_opc(DisasContext * ctx)
if (opcode != 0x0093 /* ocbi */
&& opcode != 0x00c3 /* movca.l */)
{
- gen_helper_discard_movcal_backup ();
+ gen_helper_discard_movcal_backup(cpu_env);
ctx->has_movcal = 0;
}
}
@@ -523,7 +523,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x0038: /* ldtlb */
CHECK_PRIVILEGED
- gen_helper_ldtlb();
+ gen_helper_ldtlb(cpu_env);
return;
case 0x002b: /* rte */
CHECK_PRIVILEGED
@@ -551,7 +551,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x001b: /* sleep */
CHECK_PRIVILEGED
- gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
+ gen_helper_sleep(cpu_env, tcg_const_i32(ctx->pc + 2));
return;
}
@@ -761,10 +761,10 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0x300e: /* addc Rm,Rn */
- gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8));
+ gen_helper_addc(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
return;
case 0x300f: /* addv Rm,Rn */
- gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8));
+ gen_helper_addv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
return;
case 0x2009: /* and Rm,Rn */
tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
@@ -817,7 +817,7 @@ static void _decode_opc(DisasContext * ctx)
}
return;
case 0x3004: /* div1 Rm,Rn */
- gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8));
+ gen_helper_div1(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
return;
case 0x300d: /* dmuls.l Rm,Rn */
{
@@ -870,7 +870,7 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
arg1 = tcg_temp_new();
tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
- gen_helper_macl(arg0, arg1);
+ gen_helper_macl(cpu_env, arg0, arg1);
tcg_temp_free(arg1);
tcg_temp_free(arg0);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
@@ -884,7 +884,7 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
arg1 = tcg_temp_new();
tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
- gen_helper_macw(arg0, arg1);
+ gen_helper_macw(cpu_env, arg0, arg1);
tcg_temp_free(arg1);
tcg_temp_free(arg0);
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
@@ -1013,10 +1013,10 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0x300a: /* subc Rm,Rn */
- gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8));
+ gen_helper_subc(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
return;
case 0x300b: /* subv Rm,Rn */
- gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8));
+ gen_helper_subv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
return;
case 0x2008: /* tst Rm,Rn */
{
@@ -1152,22 +1152,22 @@ static void _decode_opc(DisasContext * ctx)
gen_load_fpr64(fp1, DREG(B7_4));
switch (ctx->opcode & 0xf00f) {
case 0xf000: /* fadd Rm,Rn */
- gen_helper_fadd_DT(fp0, fp0, fp1);
+ gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1);
break;
case 0xf001: /* fsub Rm,Rn */
- gen_helper_fsub_DT(fp0, fp0, fp1);
+ gen_helper_fsub_DT(fp0, cpu_env, fp0, fp1);
break;
case 0xf002: /* fmul Rm,Rn */
- gen_helper_fmul_DT(fp0, fp0, fp1);
+ gen_helper_fmul_DT(fp0, cpu_env, fp0, fp1);
break;
case 0xf003: /* fdiv Rm,Rn */
- gen_helper_fdiv_DT(fp0, fp0, fp1);
+ gen_helper_fdiv_DT(fp0, cpu_env, fp0, fp1);
break;
case 0xf004: /* fcmp/eq Rm,Rn */
- gen_helper_fcmp_eq_DT(fp0, fp1);
+ gen_helper_fcmp_eq_DT(cpu_env, fp0, fp1);
return;
case 0xf005: /* fcmp/gt Rm,Rn */
- gen_helper_fcmp_gt_DT(fp0, fp1);
+ gen_helper_fcmp_gt_DT(cpu_env, fp0, fp1);
return;
}
gen_store_fpr64(fp0, DREG(B11_8));
@@ -1176,22 +1176,32 @@ static void _decode_opc(DisasContext * ctx)
} else {
switch (ctx->opcode & 0xf00f) {
case 0xf000: /* fadd Rm,Rn */
- gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
+ gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_env,
+ cpu_fregs[FREG(B11_8)],
+ cpu_fregs[FREG(B7_4)]);
break;
case 0xf001: /* fsub Rm,Rn */
- gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
+ gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_env,
+ cpu_fregs[FREG(B11_8)],
+ cpu_fregs[FREG(B7_4)]);
break;
case 0xf002: /* fmul Rm,Rn */
- gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
+ gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_env,
+ cpu_fregs[FREG(B11_8)],
+ cpu_fregs[FREG(B7_4)]);
break;
case 0xf003: /* fdiv Rm,Rn */
- gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
+ gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_env,
+ cpu_fregs[FREG(B11_8)],
+ cpu_fregs[FREG(B7_4)]);
break;
case 0xf004: /* fcmp/eq Rm,Rn */
- gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
+ gen_helper_fcmp_eq_FT(cpu_env, cpu_fregs[FREG(B11_8)],
+ cpu_fregs[FREG(B7_4)]);
return;
case 0xf005: /* fcmp/gt Rm,Rn */
- gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
+ gen_helper_fcmp_gt_FT(cpu_env, cpu_fregs[FREG(B11_8)],
+ cpu_fregs[FREG(B7_4)]);
return;
}
}
@@ -1203,8 +1213,9 @@ static void _decode_opc(DisasContext * ctx)
if (ctx->fpscr & FPSCR_PR) {
break; /* illegal instruction */
} else {
- gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)],
- cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)], cpu_fregs[FREG(B11_8)]);
+ gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], cpu_env,
+ cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)],
+ cpu_fregs[FREG(B11_8)]);
return;
}
}
@@ -1356,7 +1367,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv imm;
CHECK_NOT_DELAY_SLOT
imm = tcg_const_i32(B7_0);
- gen_helper_trapa(imm);
+ gen_helper_trapa(cpu_env, imm);
tcg_temp_free(imm);
ctx->bstate = BS_BRANCH;
}
@@ -1531,7 +1542,7 @@ static void _decode_opc(DisasContext * ctx)
LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED})
case 0x406a: /* lds Rm,FPSCR */
CHECK_FPU_ENABLED
- gen_helper_ld_fpscr(REG(B11_8));
+ gen_helper_ld_fpscr(cpu_env, REG(B11_8));
ctx->bstate = BS_STOP;
return;
case 0x4066: /* lds.l @Rm+,FPSCR */
@@ -1540,7 +1551,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
- gen_helper_ld_fpscr(addr);
+ gen_helper_ld_fpscr(cpu_env, addr);
tcg_temp_free(addr);
ctx->bstate = BS_STOP;
}
@@ -1567,7 +1578,7 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv val = tcg_temp_new();
tcg_gen_qemu_ld32u(val, REG(B11_8), ctx->memidx);
- gen_helper_movcal (REG(B11_8), val);
+ gen_helper_movcal(cpu_env, REG(B11_8), val);
tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
}
ctx->has_movcal = 1;
@@ -1619,7 +1630,7 @@ static void _decode_opc(DisasContext * ctx)
break;
case 0x0093: /* ocbi @Rn */
{
- gen_helper_ocbi (REG(B11_8));
+ gen_helper_ocbi(cpu_env, REG(B11_8));
}
return;
case 0x00a3: /* ocbp @Rn */
@@ -1733,12 +1744,12 @@ static void _decode_opc(DisasContext * ctx)
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
fp = tcg_temp_new_i64();
- gen_helper_float_DT(fp, cpu_fpul);
+ gen_helper_float_DT(fp, cpu_env, cpu_fpul);
gen_store_fpr64(fp, DREG(B11_8));
tcg_temp_free_i64(fp);
}
else {
- gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul);
+ gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_env, cpu_fpul);
}
return;
case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
@@ -1749,11 +1760,11 @@ static void _decode_opc(DisasContext * ctx)
break; /* illegal instruction */
fp = tcg_temp_new_i64();
gen_load_fpr64(fp, DREG(B11_8));
- gen_helper_ftrc_DT(cpu_fpul, fp);
+ gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp);
tcg_temp_free_i64(fp);
}
else {
- gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]);
+ gen_helper_ftrc_FT(cpu_fpul, cpu_env, cpu_fregs[FREG(B11_8)]);
}
return;
case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
@@ -1783,11 +1794,12 @@ static void _decode_opc(DisasContext * ctx)
break; /* illegal instruction */
TCGv_i64 fp = tcg_temp_new_i64();
gen_load_fpr64(fp, DREG(B11_8));
- gen_helper_fsqrt_DT(fp, fp);
+ gen_helper_fsqrt_DT(fp, cpu_env, fp);
gen_store_fpr64(fp, DREG(B11_8));
tcg_temp_free_i64(fp);
} else {
- gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
+ gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_env,
+ cpu_fregs[FREG(B11_8)]);
}
return;
case 0xf07d: /* fsrra FRn */
@@ -1809,7 +1821,7 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED
{
TCGv_i64 fp = tcg_temp_new_i64();
- gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);
+ gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul);
gen_store_fpr64(fp, DREG(B11_8));
tcg_temp_free_i64(fp);
}
@@ -1819,7 +1831,7 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv_i64 fp = tcg_temp_new_i64();
gen_load_fpr64(fp, DREG(B11_8));
- gen_helper_fcnvds_DT_FT(cpu_fpul, fp);
+ gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp);
tcg_temp_free_i64(fp);
}
return;
@@ -1829,7 +1841,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv m, n;
m = tcg_const_i32((ctx->opcode >> 8) & 3);
n = tcg_const_i32((ctx->opcode >> 10) & 3);
- gen_helper_fipr(m, n);
+ gen_helper_fipr(cpu_env, m, n);
tcg_temp_free(m);
tcg_temp_free(n);
return;
@@ -1841,7 +1853,7 @@ static void _decode_opc(DisasContext * ctx)
(ctx->fpscr & FPSCR_PR) == 0) {
TCGv n;
n = tcg_const_i32((ctx->opcode >> 10) & 3);
- gen_helper_ftrv(n);
+ gen_helper_ftrv(cpu_env, n);
tcg_temp_free(n);
return;
}
@@ -1853,9 +1865,9 @@ static void _decode_opc(DisasContext * ctx)
fflush(stderr);
#endif
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
- gen_helper_raise_slot_illegal_instruction();
+ gen_helper_raise_slot_illegal_instruction(cpu_env);
} else {
- gen_helper_raise_illegal_instruction();
+ gen_helper_raise_illegal_instruction(cpu_env);
}
ctx->bstate = BS_EXCP;
}
@@ -1934,7 +1946,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
if (ctx.pc == bp->pc) {
/* We have hit a breakpoint - make sure PC is up-to-date */
tcg_gen_movi_i32(cpu_pc, ctx.pc);
- gen_helper_debug();
+ gen_helper_debug(cpu_env);
ctx.bstate = BS_EXCP;
break;
}
@@ -1958,7 +1970,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
fflush(stderr);
#endif
- ctx.opcode = lduw_code(ctx.pc);
+ ctx.opcode = cpu_lduw_code(cpu_single_env, ctx.pc);
decode_opc(&ctx);
num_insns++;
ctx.pc += 2;
@@ -1975,7 +1987,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
gen_io_end();
if (env->singlestep_enabled) {
tcg_gen_movi_i32(cpu_pc, ctx.pc);
- gen_helper_debug();
+ gen_helper_debug(cpu_env);
} else {
switch (ctx.bstate) {
case BS_STOP:
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 19/21] target-sh4: switch to AREG0 free mode
2012-09-02 17:33 ` [Qemu-devel] [PATCH 19/21] target-sh4: " Blue Swirl
@ 2012-09-02 23:42 ` Aurelien Jarno
2012-09-03 18:43 ` Blue Swirl
0 siblings, 1 reply; 64+ messages in thread
From: Aurelien Jarno @ 2012-09-02 23:42 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel
On Sun, Sep 02, 2012 at 05:33:48PM +0000, Blue Swirl wrote:
> Add an explicit CPUState parameter instead of relying on AREG0
> and switch to AREG0 free mode.
>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> ---
> configure | 2 +-
> target-sh4/Makefile.objs | 2 -
> target-sh4/helper.h | 84 +++++++++++-----------
> target-sh4/op_helper.c | 182 ++++++++++++++++++++++-----------------------
> target-sh4/translate.c | 114 ++++++++++++++++-------------
> 5 files changed, 195 insertions(+), 189 deletions(-)
>
> diff --git a/configure b/configure
> index d760e07..d69e43e 100755
> --- a/configure
> +++ b/configure
> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
>
>
> case "$target_arch2" in
> - alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> + alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sh4* | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
> ;;
> esac
> diff --git a/target-sh4/Makefile.objs b/target-sh4/Makefile.objs
> index 2e0e093..ca20f21 100644
> --- a/target-sh4/Makefile.objs
> +++ b/target-sh4/Makefile.objs
> @@ -1,4 +1,2 @@
> obj-y += translate.o op_helper.o helper.o cpu.o
> obj-$(CONFIG_SOFTMMU) += machine.o
> -
> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> diff --git a/target-sh4/helper.h b/target-sh4/helper.h
> index 95e3c7c..6e4f108 100644
> --- a/target-sh4/helper.h
> +++ b/target-sh4/helper.h
> @@ -1,54 +1,54 @@
> #include "def-helper.h"
>
> -DEF_HELPER_0(ldtlb, void)
> -DEF_HELPER_0(raise_illegal_instruction, void)
> -DEF_HELPER_0(raise_slot_illegal_instruction, void)
> -DEF_HELPER_0(raise_fpu_disable, void)
> -DEF_HELPER_0(raise_slot_fpu_disable, void)
> -DEF_HELPER_0(debug, void)
> -DEF_HELPER_1(sleep, void, i32)
> -DEF_HELPER_1(trapa, void, i32)
> +DEF_HELPER_1(ldtlb, void, env)
> +DEF_HELPER_1(raise_illegal_instruction, void, env)
> +DEF_HELPER_1(raise_slot_illegal_instruction, void, env)
> +DEF_HELPER_1(raise_fpu_disable, void, env)
> +DEF_HELPER_1(raise_slot_fpu_disable, void, env)
> +DEF_HELPER_1(debug, void, env)
> +DEF_HELPER_2(sleep, void, env, i32)
> +DEF_HELPER_2(trapa, void, env, i32)
>
> -DEF_HELPER_2(movcal, void, i32, i32)
> -DEF_HELPER_0(discard_movcal_backup, void)
> -DEF_HELPER_1(ocbi, void, i32)
> +DEF_HELPER_3(movcal, void, env, i32, i32)
> +DEF_HELPER_1(discard_movcal_backup, void, env)
> +DEF_HELPER_2(ocbi, void, env, i32)
>
> -DEF_HELPER_2(addv, i32, i32, i32)
> -DEF_HELPER_2(addc, i32, i32, i32)
> -DEF_HELPER_2(subv, i32, i32, i32)
> -DEF_HELPER_2(subc, i32, i32, i32)
> -DEF_HELPER_2(div1, i32, i32, i32)
> -DEF_HELPER_2(macl, void, i32, i32)
> -DEF_HELPER_2(macw, void, i32, i32)
> +DEF_HELPER_3(addv, i32, env, i32, i32)
> +DEF_HELPER_3(addc, i32, env, i32, i32)
> +DEF_HELPER_3(subv, i32, env, i32, i32)
> +DEF_HELPER_3(subc, i32, env, i32, i32)
> +DEF_HELPER_3(div1, i32, env, i32, i32)
> +DEF_HELPER_3(macl, void, env, i32, i32)
> +DEF_HELPER_3(macw, void, env, i32, i32)
>
> -DEF_HELPER_1(ld_fpscr, void, i32)
> +DEF_HELPER_2(ld_fpscr, void, env, i32)
>
> DEF_HELPER_1(fabs_FT, f32, f32)
> DEF_HELPER_1(fabs_DT, f64, f64)
> -DEF_HELPER_2(fadd_FT, f32, f32, f32)
> -DEF_HELPER_2(fadd_DT, f64, f64, f64)
> -DEF_HELPER_1(fcnvsd_FT_DT, f64, f32)
> -DEF_HELPER_1(fcnvds_DT_FT, f32, f64)
> +DEF_HELPER_3(fadd_FT, f32, env, f32, f32)
> +DEF_HELPER_3(fadd_DT, f64, env, f64, f64)
> +DEF_HELPER_2(fcnvsd_FT_DT, f64, env, f32)
> +DEF_HELPER_2(fcnvds_DT_FT, f32, env, f64)
>
> -DEF_HELPER_2(fcmp_eq_FT, void, f32, f32)
> -DEF_HELPER_2(fcmp_eq_DT, void, f64, f64)
> -DEF_HELPER_2(fcmp_gt_FT, void, f32, f32)
> -DEF_HELPER_2(fcmp_gt_DT, void, f64, f64)
> -DEF_HELPER_2(fdiv_FT, f32, f32, f32)
> -DEF_HELPER_2(fdiv_DT, f64, f64, f64)
> -DEF_HELPER_1(float_FT, f32, i32)
> -DEF_HELPER_1(float_DT, f64, i32)
> -DEF_HELPER_3(fmac_FT, f32, f32, f32, f32)
> -DEF_HELPER_2(fmul_FT, f32, f32, f32)
> -DEF_HELPER_2(fmul_DT, f64, f64, f64)
> +DEF_HELPER_3(fcmp_eq_FT, void, env, f32, f32)
> +DEF_HELPER_3(fcmp_eq_DT, void, env, f64, f64)
> +DEF_HELPER_3(fcmp_gt_FT, void, env, f32, f32)
> +DEF_HELPER_3(fcmp_gt_DT, void, env, f64, f64)
> +DEF_HELPER_3(fdiv_FT, f32, env, f32, f32)
> +DEF_HELPER_3(fdiv_DT, f64, env, f64, f64)
> +DEF_HELPER_2(float_FT, f32, env, i32)
> +DEF_HELPER_2(float_DT, f64, env, i32)
> +DEF_HELPER_4(fmac_FT, f32, env, f32, f32, f32)
> +DEF_HELPER_3(fmul_FT, f32, env, f32, f32)
> +DEF_HELPER_3(fmul_DT, f64, env, f64, f64)
> DEF_HELPER_1(fneg_T, f32, f32)
> -DEF_HELPER_2(fsub_FT, f32, f32, f32)
> -DEF_HELPER_2(fsub_DT, f64, f64, f64)
> -DEF_HELPER_1(fsqrt_FT, f32, f32)
> -DEF_HELPER_1(fsqrt_DT, f64, f64)
> -DEF_HELPER_1(ftrc_FT, i32, f32)
> -DEF_HELPER_1(ftrc_DT, i32, f64)
> -DEF_HELPER_2(fipr, void, i32, i32)
> -DEF_HELPER_1(ftrv, void, i32)
> +DEF_HELPER_3(fsub_FT, f32, env, f32, f32)
> +DEF_HELPER_3(fsub_DT, f64, env, f64, f64)
> +DEF_HELPER_2(fsqrt_FT, f32, env, f32)
> +DEF_HELPER_2(fsqrt_DT, f64, env, f64)
> +DEF_HELPER_2(ftrc_FT, i32, env, f32)
> +DEF_HELPER_2(ftrc_DT, i32, env, f64)
> +DEF_HELPER_3(fipr, void, env, i32, i32)
> +DEF_HELPER_2(ftrv, void, env, i32)
>
> #include "def-helper.h"
> diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
> index 4054791..9b4328d 100644
> --- a/target-sh4/op_helper.c
> +++ b/target-sh4/op_helper.c
> @@ -19,10 +19,9 @@
> #include <assert.h>
> #include <stdlib.h>
> #include "cpu.h"
> -#include "dyngen-exec.h"
> #include "helper.h"
>
> -static void cpu_restore_state_from_retaddr(uintptr_t retaddr)
> +static void cpu_restore_state_from_retaddr(CPUSH4State *env, uintptr_t retaddr)
> {
> TranslationBlock *tb;
>
> @@ -53,26 +52,22 @@ static void cpu_restore_state_from_retaddr(uintptr_t retaddr)
> #define SHIFT 3
> #include "softmmu_template.h"
>
> -void tlb_fill(CPUSH4State *env1, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - CPUSH4State *saved_env;
> int ret;
>
> - saved_env = env;
> - env = env1;
> ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
> if (ret) {
> /* now we have a real cpu fault */
> - cpu_restore_state_from_retaddr(retaddr);
> + cpu_restore_state_from_retaddr(env, retaddr);
> cpu_loop_exit(env);
> }
> - env = saved_env;
> }
>
> #endif
>
> -void helper_ldtlb(void)
> +void helper_ldtlb(CPUSH4State *env)
> {
> #ifdef CONFIG_USER_ONLY
> /* XXXXX */
> @@ -82,40 +77,41 @@ void helper_ldtlb(void)
> #endif
> }
>
> -static inline void raise_exception(int index, uintptr_t retaddr)
> +static inline void raise_exception(CPUSH4State *env, int index,
> + uintptr_t retaddr)
> {
> env->exception_index = index;
> - cpu_restore_state_from_retaddr(retaddr);
> + cpu_restore_state_from_retaddr(env, retaddr);
> cpu_loop_exit(env);
> }
>
> -void helper_raise_illegal_instruction(void)
> +void helper_raise_illegal_instruction(CPUSH4State *env)
> {
> - raise_exception(0x180, GETPC());
> + raise_exception(env, 0x180, GETPC());
> }
>
> -void helper_raise_slot_illegal_instruction(void)
> +void helper_raise_slot_illegal_instruction(CPUSH4State *env)
> {
> - raise_exception(0x1a0, GETPC());
> + raise_exception(env, 0x1a0, GETPC());
> }
>
> -void helper_raise_fpu_disable(void)
> +void helper_raise_fpu_disable(CPUSH4State *env)
> {
> - raise_exception(0x800, GETPC());
> + raise_exception(env, 0x800, GETPC());
> }
>
> -void helper_raise_slot_fpu_disable(void)
> +void helper_raise_slot_fpu_disable(CPUSH4State *env)
> {
> - raise_exception(0x820, GETPC());
> + raise_exception(env, 0x820, GETPC());
> }
>
> -void helper_debug(void)
> +void helper_debug(CPUSH4State *env)
> {
> env->exception_index = EXCP_DEBUG;
> cpu_loop_exit(env);
> }
>
> -void helper_sleep(uint32_t next_pc)
> +void helper_sleep(CPUSH4State *env, uint32_t next_pc)
> {
> env->halted = 1;
> env->in_sleep = 1;
> @@ -124,13 +120,13 @@ void helper_sleep(uint32_t next_pc)
> cpu_loop_exit(env);
> }
>
> -void helper_trapa(uint32_t tra)
> +void helper_trapa(CPUSH4State *env, uint32_t tra)
> {
> env->tra = tra << 2;
> - raise_exception(0x160, GETPC());
> + raise_exception(env, 0x160, GETPC());
> }
>
> -void helper_movcal(uint32_t address, uint32_t value)
> +void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
> {
> if (cpu_sh4_is_cached (env, address))
> {
> @@ -144,7 +140,7 @@ void helper_movcal(uint32_t address, uint32_t value)
> }
> }
>
> -void helper_discard_movcal_backup(void)
> +void helper_discard_movcal_backup(CPUSH4State *env)
> {
> memory_content *current = env->movcal_backup;
>
> @@ -158,7 +154,7 @@ void helper_discard_movcal_backup(void)
> }
> }
>
> -void helper_ocbi(uint32_t address)
> +void helper_ocbi(CPUSH4State *env, uint32_t address)
> {
> memory_content **current = &(env->movcal_backup);
> while (*current)
> @@ -167,7 +163,7 @@ void helper_ocbi(uint32_t address)
> if ((a & ~0x1F) == (address & ~0x1F))
> {
> memory_content *next = (*current)->next;
> - stl(a, (*current)->value);
> + cpu_stl_data(env, a, (*current)->value);
>
> if (next == NULL)
> {
> @@ -181,7 +177,7 @@ void helper_ocbi(uint32_t address)
> }
> }
>
> -uint32_t helper_addc(uint32_t arg0, uint32_t arg1)
> +uint32_t helper_addc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
> {
> uint32_t tmp0, tmp1;
>
> @@ -197,7 +193,7 @@ uint32_t helper_addc(uint32_t arg0, uint32_t arg1)
> return arg1;
> }
>
> -uint32_t helper_addv(uint32_t arg0, uint32_t arg1)
> +uint32_t helper_addv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
> {
> uint32_t dest, src, ans;
>
> @@ -236,7 +232,7 @@ uint32_t helper_addv(uint32_t arg0, uint32_t arg1)
> #define SETM env->sr |= SR_M
> #define CLRM env->sr &= ~SR_M
>
> -uint32_t helper_div1(uint32_t arg0, uint32_t arg1)
> +uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
> {
> uint32_t tmp0, tmp2;
> uint8_t old_q, tmp1 = 0xff;
> @@ -344,7 +340,7 @@ uint32_t helper_div1(uint32_t arg0, uint32_t arg1)
> return arg1;
> }
>
> -void helper_macl(uint32_t arg0, uint32_t arg1)
> +void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
> {
> int64_t res;
>
> @@ -360,7 +356,7 @@ void helper_macl(uint32_t arg0, uint32_t arg1)
> }
> }
>
> -void helper_macw(uint32_t arg0, uint32_t arg1)
> +void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
> {
> int64_t res;
>
> @@ -379,7 +375,7 @@ void helper_macw(uint32_t arg0, uint32_t arg1)
> }
> }
>
> -uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
> +uint32_t helper_subc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
> {
> uint32_t tmp0, tmp1;
>
> @@ -395,7 +391,7 @@ uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
> return arg1;
> }
>
> -uint32_t helper_subv(uint32_t arg0, uint32_t arg1)
> +uint32_t helper_subv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
> {
> int32_t dest, src, ans;
>
> @@ -424,17 +420,17 @@ uint32_t helper_subv(uint32_t arg0, uint32_t arg1)
> return arg1;
> }
>
> -static inline void set_t(void)
> +static inline void set_t(CPUSH4State *env)
> {
> env->sr |= SR_T;
> }
>
> -static inline void clr_t(void)
> +static inline void clr_t(CPUSH4State *env)
> {
> env->sr &= ~SR_T;
> }
>
> -void helper_ld_fpscr(uint32_t val)
> +void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
> {
> env->fpscr = val & FPSCR_MASK;
> if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
> @@ -445,7 +441,7 @@ void helper_ld_fpscr(uint32_t val)
> set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
> }
>
> -static void update_fpscr(uintptr_t retaddr)
> +static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
> {
> int xcpt, cause, enable;
>
> @@ -479,7 +475,7 @@ static void update_fpscr(uintptr_t retaddr)
> cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
> enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
> if (cause & enable) {
> - cpu_restore_state_from_retaddr(retaddr);
> + cpu_restore_state_from_retaddr(env, retaddr);
> env->exception_index = 0x120;
> cpu_loop_exit(env);
> }
> @@ -496,156 +492,156 @@ float64 helper_fabs_DT(float64 t0)
> return float64_abs(t0);
> }
>
> -float32 helper_fadd_FT(float32 t0, float32 t1)
> +float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
> {
> set_float_exception_flags(0, &env->fp_status);
> t0 = float32_add(t0, t1, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return t0;
> }
>
> -float64 helper_fadd_DT(float64 t0, float64 t1)
> +float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
> {
> set_float_exception_flags(0, &env->fp_status);
> t0 = float64_add(t0, t1, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return t0;
> }
>
> -void helper_fcmp_eq_FT(float32 t0, float32 t1)
> +void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
> {
> int relation;
>
> set_float_exception_flags(0, &env->fp_status);
> relation = float32_compare(t0, t1, &env->fp_status);
> if (unlikely(relation == float_relation_unordered)) {
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> } else if (relation == float_relation_equal) {
> - set_t();
> + set_t(env);
> } else {
> - clr_t();
> + clr_t(env);
> }
> }
>
> -void helper_fcmp_eq_DT(float64 t0, float64 t1)
> +void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
> {
> int relation;
>
> set_float_exception_flags(0, &env->fp_status);
> relation = float64_compare(t0, t1, &env->fp_status);
> if (unlikely(relation == float_relation_unordered)) {
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> } else if (relation == float_relation_equal) {
> - set_t();
> + set_t(env);
> } else {
> - clr_t();
> + clr_t(env);
> }
> }
>
> -void helper_fcmp_gt_FT(float32 t0, float32 t1)
> +void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
> {
> int relation;
>
> set_float_exception_flags(0, &env->fp_status);
> relation = float32_compare(t0, t1, &env->fp_status);
> if (unlikely(relation == float_relation_unordered)) {
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> } else if (relation == float_relation_greater) {
> - set_t();
> + set_t(env);
> } else {
> - clr_t();
> + clr_t(env);
> }
> }
>
> -void helper_fcmp_gt_DT(float64 t0, float64 t1)
> +void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
> {
> int relation;
>
> set_float_exception_flags(0, &env->fp_status);
> relation = float64_compare(t0, t1, &env->fp_status);
> if (unlikely(relation == float_relation_unordered)) {
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> } else if (relation == float_relation_greater) {
> - set_t();
> + set_t(env);
> } else {
> - clr_t();
> + clr_t(env);
> }
> }
>
> -float64 helper_fcnvsd_FT_DT(float32 t0)
> +float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
> {
> float64 ret;
> set_float_exception_flags(0, &env->fp_status);
> ret = float32_to_float64(t0, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return ret;
> }
>
> -float32 helper_fcnvds_DT_FT(float64 t0)
> +float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
> {
> float32 ret;
> set_float_exception_flags(0, &env->fp_status);
> ret = float64_to_float32(t0, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return ret;
> }
>
> -float32 helper_fdiv_FT(float32 t0, float32 t1)
> +float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
> {
> set_float_exception_flags(0, &env->fp_status);
> t0 = float32_div(t0, t1, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return t0;
> }
>
> -float64 helper_fdiv_DT(float64 t0, float64 t1)
> +float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
> {
> set_float_exception_flags(0, &env->fp_status);
> t0 = float64_div(t0, t1, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return t0;
> }
>
> -float32 helper_float_FT(uint32_t t0)
> +float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
> {
> float32 ret;
> set_float_exception_flags(0, &env->fp_status);
> ret = int32_to_float32(t0, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return ret;
> }
>
> -float64 helper_float_DT(uint32_t t0)
> +float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
> {
> float64 ret;
> set_float_exception_flags(0, &env->fp_status);
> ret = int32_to_float64(t0, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return ret;
> }
>
> -float32 helper_fmac_FT(float32 t0, float32 t1, float32 t2)
> +float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
> {
> set_float_exception_flags(0, &env->fp_status);
> t0 = float32_mul(t0, t1, &env->fp_status);
> t0 = float32_add(t0, t2, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return t0;
> }
>
> -float32 helper_fmul_FT(float32 t0, float32 t1)
> +float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
> {
> set_float_exception_flags(0, &env->fp_status);
> t0 = float32_mul(t0, t1, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return t0;
> }
>
> -float64 helper_fmul_DT(float64 t0, float64 t1)
> +float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
> {
> set_float_exception_flags(0, &env->fp_status);
> t0 = float64_mul(t0, t1, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return t0;
> }
>
> @@ -654,57 +650,57 @@ float32 helper_fneg_T(float32 t0)
> return float32_chs(t0);
> }
>
> -float32 helper_fsqrt_FT(float32 t0)
> +float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
> {
> set_float_exception_flags(0, &env->fp_status);
> t0 = float32_sqrt(t0, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return t0;
> }
>
> -float64 helper_fsqrt_DT(float64 t0)
> +float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
> {
> set_float_exception_flags(0, &env->fp_status);
> t0 = float64_sqrt(t0, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return t0;
> }
>
> -float32 helper_fsub_FT(float32 t0, float32 t1)
> +float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
> {
> set_float_exception_flags(0, &env->fp_status);
> t0 = float32_sub(t0, t1, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return t0;
> }
>
> -float64 helper_fsub_DT(float64 t0, float64 t1)
> +float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
> {
> set_float_exception_flags(0, &env->fp_status);
> t0 = float64_sub(t0, t1, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return t0;
> }
>
> -uint32_t helper_ftrc_FT(float32 t0)
> +uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
> {
> uint32_t ret;
> set_float_exception_flags(0, &env->fp_status);
> ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return ret;
> }
>
> -uint32_t helper_ftrc_DT(float64 t0)
> +uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
> {
> uint32_t ret;
> set_float_exception_flags(0, &env->fp_status);
> ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
> return ret;
> }
>
> -void helper_fipr(uint32_t m, uint32_t n)
> +void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
> {
> int bank, i;
> float32 r, p;
> @@ -719,12 +715,12 @@ void helper_fipr(uint32_t m, uint32_t n)
> &env->fp_status);
> r = float32_add(r, p, &env->fp_status);
> }
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
>
> env->fregs[bank + n + 3] = r;
> }
>
> -void helper_ftrv(uint32_t n)
> +void helper_ftrv(CPUSH4State *env, uint32_t n)
> {
> int bank_matrix, bank_vector;
> int i, j;
> @@ -743,7 +739,7 @@ void helper_ftrv(uint32_t n)
> r[i] = float32_add(r[i], p, &env->fp_status);
> }
> }
> - update_fpscr(GETPC());
> + update_fpscr(env, GETPC());
>
> for (i = 0 ; i < 4 ; i++) {
> env->fregs[bank_vector + i] = r[i];
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 6532ad2..102b1b4 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -276,7 +276,7 @@ static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
> } else {
> tcg_gen_movi_i32(cpu_pc, dest);
> if (ctx->singlestep_enabled)
> - gen_helper_debug();
> + gen_helper_debug(cpu_env);
> tcg_gen_exit_tb(0);
> }
> }
> @@ -288,7 +288,7 @@ static void gen_jump(DisasContext * ctx)
> delayed jump as immediate jump are conditinal jumps */
> tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
> if (ctx->singlestep_enabled)
> - gen_helper_debug();
> + gen_helper_debug(cpu_env);
> tcg_gen_exit_tb(0);
> } else {
> gen_goto_tb(ctx, 0, ctx->delayed_pc);
> @@ -437,7 +437,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
> #define CHECK_NOT_DELAY_SLOT \
> if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
> { \
> - gen_helper_raise_slot_illegal_instruction(); \
> + gen_helper_raise_slot_illegal_instruction(cpu_env); \
> ctx->bstate = BS_EXCP; \
> return; \
> }
> @@ -445,9 +445,9 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
> #define CHECK_PRIVILEGED \
> if (IS_USER(ctx)) { \
> if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
> - gen_helper_raise_slot_illegal_instruction(); \
> + gen_helper_raise_slot_illegal_instruction(cpu_env); \
> } else { \
> - gen_helper_raise_illegal_instruction(); \
> + gen_helper_raise_illegal_instruction(cpu_env); \
> } \
> ctx->bstate = BS_EXCP; \
> return; \
> @@ -456,9 +456,9 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
> #define CHECK_FPU_ENABLED \
> if (ctx->flags & SR_FD) { \
> if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
> - gen_helper_raise_slot_fpu_disable(); \
> + gen_helper_raise_slot_fpu_disable(cpu_env); \
> } else { \
> - gen_helper_raise_fpu_disable(); \
> + gen_helper_raise_fpu_disable(cpu_env); \
> } \
> ctx->bstate = BS_EXCP; \
> return; \
> @@ -492,7 +492,7 @@ static void _decode_opc(DisasContext * ctx)
> if (opcode != 0x0093 /* ocbi */
> && opcode != 0x00c3 /* movca.l */)
> {
> - gen_helper_discard_movcal_backup ();
> + gen_helper_discard_movcal_backup(cpu_env);
> ctx->has_movcal = 0;
> }
> }
> @@ -523,7 +523,7 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0x0038: /* ldtlb */
> CHECK_PRIVILEGED
> - gen_helper_ldtlb();
> + gen_helper_ldtlb(cpu_env);
> return;
> case 0x002b: /* rte */
> CHECK_PRIVILEGED
> @@ -551,7 +551,7 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0x001b: /* sleep */
> CHECK_PRIVILEGED
> - gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
> + gen_helper_sleep(cpu_env, tcg_const_i32(ctx->pc + 2));
> return;
> }
>
> @@ -761,10 +761,10 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
> return;
> case 0x300e: /* addc Rm,Rn */
> - gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8));
> + gen_helper_addc(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
> return;
> case 0x300f: /* addv Rm,Rn */
> - gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8));
> + gen_helper_addv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
> return;
> case 0x2009: /* and Rm,Rn */
> tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
> @@ -817,7 +817,7 @@ static void _decode_opc(DisasContext * ctx)
> }
> return;
> case 0x3004: /* div1 Rm,Rn */
> - gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8));
> + gen_helper_div1(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
> return;
> case 0x300d: /* dmuls.l Rm,Rn */
> {
> @@ -870,7 +870,7 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
> arg1 = tcg_temp_new();
> tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
> - gen_helper_macl(arg0, arg1);
> + gen_helper_macl(cpu_env, arg0, arg1);
> tcg_temp_free(arg1);
> tcg_temp_free(arg0);
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> @@ -884,7 +884,7 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
> arg1 = tcg_temp_new();
> tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
> - gen_helper_macw(arg0, arg1);
> + gen_helper_macw(cpu_env, arg0, arg1);
> tcg_temp_free(arg1);
> tcg_temp_free(arg0);
> tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
> @@ -1013,10 +1013,10 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
> return;
> case 0x300a: /* subc Rm,Rn */
> - gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8));
> + gen_helper_subc(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
> return;
> case 0x300b: /* subv Rm,Rn */
> - gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8));
> + gen_helper_subv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
> return;
> case 0x2008: /* tst Rm,Rn */
> {
> @@ -1152,22 +1152,22 @@ static void _decode_opc(DisasContext * ctx)
> gen_load_fpr64(fp1, DREG(B7_4));
> switch (ctx->opcode & 0xf00f) {
> case 0xf000: /* fadd Rm,Rn */
> - gen_helper_fadd_DT(fp0, fp0, fp1);
> + gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1);
> break;
> case 0xf001: /* fsub Rm,Rn */
> - gen_helper_fsub_DT(fp0, fp0, fp1);
> + gen_helper_fsub_DT(fp0, cpu_env, fp0, fp1);
> break;
> case 0xf002: /* fmul Rm,Rn */
> - gen_helper_fmul_DT(fp0, fp0, fp1);
> + gen_helper_fmul_DT(fp0, cpu_env, fp0, fp1);
> break;
> case 0xf003: /* fdiv Rm,Rn */
> - gen_helper_fdiv_DT(fp0, fp0, fp1);
> + gen_helper_fdiv_DT(fp0, cpu_env, fp0, fp1);
> break;
> case 0xf004: /* fcmp/eq Rm,Rn */
> - gen_helper_fcmp_eq_DT(fp0, fp1);
> + gen_helper_fcmp_eq_DT(cpu_env, fp0, fp1);
> return;
> case 0xf005: /* fcmp/gt Rm,Rn */
> - gen_helper_fcmp_gt_DT(fp0, fp1);
> + gen_helper_fcmp_gt_DT(cpu_env, fp0, fp1);
> return;
> }
> gen_store_fpr64(fp0, DREG(B11_8));
> @@ -1176,22 +1176,32 @@ static void _decode_opc(DisasContext * ctx)
> } else {
> switch (ctx->opcode & 0xf00f) {
> case 0xf000: /* fadd Rm,Rn */
> - gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
> + gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_env,
> + cpu_fregs[FREG(B11_8)],
> + cpu_fregs[FREG(B7_4)]);
> break;
> case 0xf001: /* fsub Rm,Rn */
> - gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
> + gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_env,
> + cpu_fregs[FREG(B11_8)],
> + cpu_fregs[FREG(B7_4)]);
> break;
> case 0xf002: /* fmul Rm,Rn */
> - gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
> + gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_env,
> + cpu_fregs[FREG(B11_8)],
> + cpu_fregs[FREG(B7_4)]);
> break;
> case 0xf003: /* fdiv Rm,Rn */
> - gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
> + gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_env,
> + cpu_fregs[FREG(B11_8)],
> + cpu_fregs[FREG(B7_4)]);
> break;
> case 0xf004: /* fcmp/eq Rm,Rn */
> - gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
> + gen_helper_fcmp_eq_FT(cpu_env, cpu_fregs[FREG(B11_8)],
> + cpu_fregs[FREG(B7_4)]);
> return;
> case 0xf005: /* fcmp/gt Rm,Rn */
> - gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
> + gen_helper_fcmp_gt_FT(cpu_env, cpu_fregs[FREG(B11_8)],
> + cpu_fregs[FREG(B7_4)]);
> return;
> }
> }
> @@ -1203,8 +1213,9 @@ static void _decode_opc(DisasContext * ctx)
> if (ctx->fpscr & FPSCR_PR) {
> break; /* illegal instruction */
> } else {
> - gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)],
> - cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)], cpu_fregs[FREG(B11_8)]);
> + gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], cpu_env,
> + cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)],
> + cpu_fregs[FREG(B11_8)]);
> return;
> }
> }
> @@ -1356,7 +1367,7 @@ static void _decode_opc(DisasContext * ctx)
> TCGv imm;
> CHECK_NOT_DELAY_SLOT
> imm = tcg_const_i32(B7_0);
> - gen_helper_trapa(imm);
> + gen_helper_trapa(cpu_env, imm);
> tcg_temp_free(imm);
> ctx->bstate = BS_BRANCH;
> }
> @@ -1531,7 +1542,7 @@ static void _decode_opc(DisasContext * ctx)
> LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED})
> case 0x406a: /* lds Rm,FPSCR */
> CHECK_FPU_ENABLED
> - gen_helper_ld_fpscr(REG(B11_8));
> + gen_helper_ld_fpscr(cpu_env, REG(B11_8));
> ctx->bstate = BS_STOP;
> return;
> case 0x4066: /* lds.l @Rm+,FPSCR */
> @@ -1540,7 +1551,7 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new();
> tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
> tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
> - gen_helper_ld_fpscr(addr);
> + gen_helper_ld_fpscr(cpu_env, addr);
> tcg_temp_free(addr);
> ctx->bstate = BS_STOP;
> }
> @@ -1567,7 +1578,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv val = tcg_temp_new();
> tcg_gen_qemu_ld32u(val, REG(B11_8), ctx->memidx);
> - gen_helper_movcal (REG(B11_8), val);
> + gen_helper_movcal(cpu_env, REG(B11_8), val);
> tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
> }
> ctx->has_movcal = 1;
> @@ -1619,7 +1630,7 @@ static void _decode_opc(DisasContext * ctx)
> break;
> case 0x0093: /* ocbi @Rn */
> {
> - gen_helper_ocbi (REG(B11_8));
> + gen_helper_ocbi(cpu_env, REG(B11_8));
> }
> return;
> case 0x00a3: /* ocbp @Rn */
> @@ -1733,12 +1744,12 @@ static void _decode_opc(DisasContext * ctx)
> if (ctx->opcode & 0x0100)
> break; /* illegal instruction */
> fp = tcg_temp_new_i64();
> - gen_helper_float_DT(fp, cpu_fpul);
> + gen_helper_float_DT(fp, cpu_env, cpu_fpul);
> gen_store_fpr64(fp, DREG(B11_8));
> tcg_temp_free_i64(fp);
> }
> else {
> - gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul);
> + gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_env, cpu_fpul);
> }
> return;
> case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
> @@ -1749,11 +1760,11 @@ static void _decode_opc(DisasContext * ctx)
> break; /* illegal instruction */
> fp = tcg_temp_new_i64();
> gen_load_fpr64(fp, DREG(B11_8));
> - gen_helper_ftrc_DT(cpu_fpul, fp);
> + gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp);
> tcg_temp_free_i64(fp);
> }
> else {
> - gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]);
> + gen_helper_ftrc_FT(cpu_fpul, cpu_env, cpu_fregs[FREG(B11_8)]);
> }
> return;
> case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
> @@ -1783,11 +1794,12 @@ static void _decode_opc(DisasContext * ctx)
> break; /* illegal instruction */
> TCGv_i64 fp = tcg_temp_new_i64();
> gen_load_fpr64(fp, DREG(B11_8));
> - gen_helper_fsqrt_DT(fp, fp);
> + gen_helper_fsqrt_DT(fp, cpu_env, fp);
> gen_store_fpr64(fp, DREG(B11_8));
> tcg_temp_free_i64(fp);
> } else {
> - gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
> + gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_env,
> + cpu_fregs[FREG(B11_8)]);
> }
> return;
> case 0xf07d: /* fsrra FRn */
> @@ -1809,7 +1821,7 @@ static void _decode_opc(DisasContext * ctx)
> CHECK_FPU_ENABLED
> {
> TCGv_i64 fp = tcg_temp_new_i64();
> - gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);
> + gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul);
> gen_store_fpr64(fp, DREG(B11_8));
> tcg_temp_free_i64(fp);
> }
> @@ -1819,7 +1831,7 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv_i64 fp = tcg_temp_new_i64();
> gen_load_fpr64(fp, DREG(B11_8));
> - gen_helper_fcnvds_DT_FT(cpu_fpul, fp);
> + gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp);
> tcg_temp_free_i64(fp);
> }
> return;
> @@ -1829,7 +1841,7 @@ static void _decode_opc(DisasContext * ctx)
> TCGv m, n;
> m = tcg_const_i32((ctx->opcode >> 8) & 3);
> n = tcg_const_i32((ctx->opcode >> 10) & 3);
> - gen_helper_fipr(m, n);
> + gen_helper_fipr(cpu_env, m, n);
> tcg_temp_free(m);
> tcg_temp_free(n);
> return;
> @@ -1841,7 +1853,7 @@ static void _decode_opc(DisasContext * ctx)
> (ctx->fpscr & FPSCR_PR) == 0) {
> TCGv n;
> n = tcg_const_i32((ctx->opcode >> 10) & 3);
> - gen_helper_ftrv(n);
> + gen_helper_ftrv(cpu_env, n);
> tcg_temp_free(n);
> return;
> }
> @@ -1853,9 +1865,9 @@ static void _decode_opc(DisasContext * ctx)
> fflush(stderr);
> #endif
> if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
> - gen_helper_raise_slot_illegal_instruction();
> + gen_helper_raise_slot_illegal_instruction(cpu_env);
> } else {
> - gen_helper_raise_illegal_instruction();
> + gen_helper_raise_illegal_instruction(cpu_env);
> }
> ctx->bstate = BS_EXCP;
> }
> @@ -1934,7 +1946,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
> if (ctx.pc == bp->pc) {
> /* We have hit a breakpoint - make sure PC is up-to-date */
> tcg_gen_movi_i32(cpu_pc, ctx.pc);
> - gen_helper_debug();
> + gen_helper_debug(cpu_env);
> ctx.bstate = BS_EXCP;
> break;
> }
> @@ -1958,7 +1970,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
> fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
> fflush(stderr);
> #endif
> - ctx.opcode = lduw_code(ctx.pc);
> + ctx.opcode = cpu_lduw_code(cpu_single_env, ctx.pc);
Why using cpu_single_env here, while all the code in this function uses
the env argument to gen_intermediate_code()? I thought one of the goal
of this patch series was to get rid of the global env variable.
> decode_opc(&ctx);
> num_insns++;
> ctx.pc += 2;
> @@ -1975,7 +1987,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
> gen_io_end();
> if (env->singlestep_enabled) {
> tcg_gen_movi_i32(cpu_pc, ctx.pc);
> - gen_helper_debug();
> + gen_helper_debug(cpu_env);
> } else {
> switch (ctx.bstate) {
> case BS_STOP:
> --
> 1.7.2.5
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 19/21] target-sh4: switch to AREG0 free mode
2012-09-02 23:42 ` Aurelien Jarno
@ 2012-09-03 18:43 ` Blue Swirl
0 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-03 18:43 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: qemu-devel
On Sun, Sep 2, 2012 at 11:42 PM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Sun, Sep 02, 2012 at 05:33:48PM +0000, Blue Swirl wrote:
>> Add an explicit CPUState parameter instead of relying on AREG0
>> and switch to AREG0 free mode.
>>
>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>> ---
>> configure | 2 +-
>> target-sh4/Makefile.objs | 2 -
>> target-sh4/helper.h | 84 +++++++++++-----------
>> target-sh4/op_helper.c | 182 ++++++++++++++++++++++-----------------------
>> target-sh4/translate.c | 114 ++++++++++++++++-------------
>> 5 files changed, 195 insertions(+), 189 deletions(-)
>>
>> diff --git a/configure b/configure
>> index d760e07..d69e43e 100755
>> --- a/configure
>> +++ b/configure
>> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
>>
>>
>> case "$target_arch2" in
>> - alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
>> + alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sh4* | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
>> echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
>> ;;
>> esac
>> diff --git a/target-sh4/Makefile.objs b/target-sh4/Makefile.objs
>> index 2e0e093..ca20f21 100644
>> --- a/target-sh4/Makefile.objs
>> +++ b/target-sh4/Makefile.objs
>> @@ -1,4 +1,2 @@
>> obj-y += translate.o op_helper.o helper.o cpu.o
>> obj-$(CONFIG_SOFTMMU) += machine.o
>> -
>> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
>> diff --git a/target-sh4/helper.h b/target-sh4/helper.h
>> index 95e3c7c..6e4f108 100644
>> --- a/target-sh4/helper.h
>> +++ b/target-sh4/helper.h
>> @@ -1,54 +1,54 @@
>> #include "def-helper.h"
>>
>> -DEF_HELPER_0(ldtlb, void)
>> -DEF_HELPER_0(raise_illegal_instruction, void)
>> -DEF_HELPER_0(raise_slot_illegal_instruction, void)
>> -DEF_HELPER_0(raise_fpu_disable, void)
>> -DEF_HELPER_0(raise_slot_fpu_disable, void)
>> -DEF_HELPER_0(debug, void)
>> -DEF_HELPER_1(sleep, void, i32)
>> -DEF_HELPER_1(trapa, void, i32)
>> +DEF_HELPER_1(ldtlb, void, env)
>> +DEF_HELPER_1(raise_illegal_instruction, void, env)
>> +DEF_HELPER_1(raise_slot_illegal_instruction, void, env)
>> +DEF_HELPER_1(raise_fpu_disable, void, env)
>> +DEF_HELPER_1(raise_slot_fpu_disable, void, env)
>> +DEF_HELPER_1(debug, void, env)
>> +DEF_HELPER_2(sleep, void, env, i32)
>> +DEF_HELPER_2(trapa, void, env, i32)
>>
>> -DEF_HELPER_2(movcal, void, i32, i32)
>> -DEF_HELPER_0(discard_movcal_backup, void)
>> -DEF_HELPER_1(ocbi, void, i32)
>> +DEF_HELPER_3(movcal, void, env, i32, i32)
>> +DEF_HELPER_1(discard_movcal_backup, void, env)
>> +DEF_HELPER_2(ocbi, void, env, i32)
>>
>> -DEF_HELPER_2(addv, i32, i32, i32)
>> -DEF_HELPER_2(addc, i32, i32, i32)
>> -DEF_HELPER_2(subv, i32, i32, i32)
>> -DEF_HELPER_2(subc, i32, i32, i32)
>> -DEF_HELPER_2(div1, i32, i32, i32)
>> -DEF_HELPER_2(macl, void, i32, i32)
>> -DEF_HELPER_2(macw, void, i32, i32)
>> +DEF_HELPER_3(addv, i32, env, i32, i32)
>> +DEF_HELPER_3(addc, i32, env, i32, i32)
>> +DEF_HELPER_3(subv, i32, env, i32, i32)
>> +DEF_HELPER_3(subc, i32, env, i32, i32)
>> +DEF_HELPER_3(div1, i32, env, i32, i32)
>> +DEF_HELPER_3(macl, void, env, i32, i32)
>> +DEF_HELPER_3(macw, void, env, i32, i32)
>>
>> -DEF_HELPER_1(ld_fpscr, void, i32)
>> +DEF_HELPER_2(ld_fpscr, void, env, i32)
>>
>> DEF_HELPER_1(fabs_FT, f32, f32)
>> DEF_HELPER_1(fabs_DT, f64, f64)
>> -DEF_HELPER_2(fadd_FT, f32, f32, f32)
>> -DEF_HELPER_2(fadd_DT, f64, f64, f64)
>> -DEF_HELPER_1(fcnvsd_FT_DT, f64, f32)
>> -DEF_HELPER_1(fcnvds_DT_FT, f32, f64)
>> +DEF_HELPER_3(fadd_FT, f32, env, f32, f32)
>> +DEF_HELPER_3(fadd_DT, f64, env, f64, f64)
>> +DEF_HELPER_2(fcnvsd_FT_DT, f64, env, f32)
>> +DEF_HELPER_2(fcnvds_DT_FT, f32, env, f64)
>>
>> -DEF_HELPER_2(fcmp_eq_FT, void, f32, f32)
>> -DEF_HELPER_2(fcmp_eq_DT, void, f64, f64)
>> -DEF_HELPER_2(fcmp_gt_FT, void, f32, f32)
>> -DEF_HELPER_2(fcmp_gt_DT, void, f64, f64)
>> -DEF_HELPER_2(fdiv_FT, f32, f32, f32)
>> -DEF_HELPER_2(fdiv_DT, f64, f64, f64)
>> -DEF_HELPER_1(float_FT, f32, i32)
>> -DEF_HELPER_1(float_DT, f64, i32)
>> -DEF_HELPER_3(fmac_FT, f32, f32, f32, f32)
>> -DEF_HELPER_2(fmul_FT, f32, f32, f32)
>> -DEF_HELPER_2(fmul_DT, f64, f64, f64)
>> +DEF_HELPER_3(fcmp_eq_FT, void, env, f32, f32)
>> +DEF_HELPER_3(fcmp_eq_DT, void, env, f64, f64)
>> +DEF_HELPER_3(fcmp_gt_FT, void, env, f32, f32)
>> +DEF_HELPER_3(fcmp_gt_DT, void, env, f64, f64)
>> +DEF_HELPER_3(fdiv_FT, f32, env, f32, f32)
>> +DEF_HELPER_3(fdiv_DT, f64, env, f64, f64)
>> +DEF_HELPER_2(float_FT, f32, env, i32)
>> +DEF_HELPER_2(float_DT, f64, env, i32)
>> +DEF_HELPER_4(fmac_FT, f32, env, f32, f32, f32)
>> +DEF_HELPER_3(fmul_FT, f32, env, f32, f32)
>> +DEF_HELPER_3(fmul_DT, f64, env, f64, f64)
>> DEF_HELPER_1(fneg_T, f32, f32)
>> -DEF_HELPER_2(fsub_FT, f32, f32, f32)
>> -DEF_HELPER_2(fsub_DT, f64, f64, f64)
>> -DEF_HELPER_1(fsqrt_FT, f32, f32)
>> -DEF_HELPER_1(fsqrt_DT, f64, f64)
>> -DEF_HELPER_1(ftrc_FT, i32, f32)
>> -DEF_HELPER_1(ftrc_DT, i32, f64)
>> -DEF_HELPER_2(fipr, void, i32, i32)
>> -DEF_HELPER_1(ftrv, void, i32)
>> +DEF_HELPER_3(fsub_FT, f32, env, f32, f32)
>> +DEF_HELPER_3(fsub_DT, f64, env, f64, f64)
>> +DEF_HELPER_2(fsqrt_FT, f32, env, f32)
>> +DEF_HELPER_2(fsqrt_DT, f64, env, f64)
>> +DEF_HELPER_2(ftrc_FT, i32, env, f32)
>> +DEF_HELPER_2(ftrc_DT, i32, env, f64)
>> +DEF_HELPER_3(fipr, void, env, i32, i32)
>> +DEF_HELPER_2(ftrv, void, env, i32)
>>
>> #include "def-helper.h"
>> diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
>> index 4054791..9b4328d 100644
>> --- a/target-sh4/op_helper.c
>> +++ b/target-sh4/op_helper.c
>> @@ -19,10 +19,9 @@
>> #include <assert.h>
>> #include <stdlib.h>
>> #include "cpu.h"
>> -#include "dyngen-exec.h"
>> #include "helper.h"
>>
>> -static void cpu_restore_state_from_retaddr(uintptr_t retaddr)
>> +static void cpu_restore_state_from_retaddr(CPUSH4State *env, uintptr_t retaddr)
>> {
>> TranslationBlock *tb;
>>
>> @@ -53,26 +52,22 @@ static void cpu_restore_state_from_retaddr(uintptr_t retaddr)
>> #define SHIFT 3
>> #include "softmmu_template.h"
>>
>> -void tlb_fill(CPUSH4State *env1, target_ulong addr, int is_write, int mmu_idx,
>> +void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
>> uintptr_t retaddr)
>> {
>> - CPUSH4State *saved_env;
>> int ret;
>>
>> - saved_env = env;
>> - env = env1;
>> ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
>> if (ret) {
>> /* now we have a real cpu fault */
>> - cpu_restore_state_from_retaddr(retaddr);
>> + cpu_restore_state_from_retaddr(env, retaddr);
>> cpu_loop_exit(env);
>> }
>> - env = saved_env;
>> }
>>
>> #endif
>>
>> -void helper_ldtlb(void)
>> +void helper_ldtlb(CPUSH4State *env)
>> {
>> #ifdef CONFIG_USER_ONLY
>> /* XXXXX */
>> @@ -82,40 +77,41 @@ void helper_ldtlb(void)
>> #endif
>> }
>>
>> -static inline void raise_exception(int index, uintptr_t retaddr)
>> +static inline void raise_exception(CPUSH4State *env, int index,
>> + uintptr_t retaddr)
>> {
>> env->exception_index = index;
>> - cpu_restore_state_from_retaddr(retaddr);
>> + cpu_restore_state_from_retaddr(env, retaddr);
>> cpu_loop_exit(env);
>> }
>>
>> -void helper_raise_illegal_instruction(void)
>> +void helper_raise_illegal_instruction(CPUSH4State *env)
>> {
>> - raise_exception(0x180, GETPC());
>> + raise_exception(env, 0x180, GETPC());
>> }
>>
>> -void helper_raise_slot_illegal_instruction(void)
>> +void helper_raise_slot_illegal_instruction(CPUSH4State *env)
>> {
>> - raise_exception(0x1a0, GETPC());
>> + raise_exception(env, 0x1a0, GETPC());
>> }
>>
>> -void helper_raise_fpu_disable(void)
>> +void helper_raise_fpu_disable(CPUSH4State *env)
>> {
>> - raise_exception(0x800, GETPC());
>> + raise_exception(env, 0x800, GETPC());
>> }
>>
>> -void helper_raise_slot_fpu_disable(void)
>> +void helper_raise_slot_fpu_disable(CPUSH4State *env)
>> {
>> - raise_exception(0x820, GETPC());
>> + raise_exception(env, 0x820, GETPC());
>> }
>>
>> -void helper_debug(void)
>> +void helper_debug(CPUSH4State *env)
>> {
>> env->exception_index = EXCP_DEBUG;
>> cpu_loop_exit(env);
>> }
>>
>> -void helper_sleep(uint32_t next_pc)
>> +void helper_sleep(CPUSH4State *env, uint32_t next_pc)
>> {
>> env->halted = 1;
>> env->in_sleep = 1;
>> @@ -124,13 +120,13 @@ void helper_sleep(uint32_t next_pc)
>> cpu_loop_exit(env);
>> }
>>
>> -void helper_trapa(uint32_t tra)
>> +void helper_trapa(CPUSH4State *env, uint32_t tra)
>> {
>> env->tra = tra << 2;
>> - raise_exception(0x160, GETPC());
>> + raise_exception(env, 0x160, GETPC());
>> }
>>
>> -void helper_movcal(uint32_t address, uint32_t value)
>> +void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
>> {
>> if (cpu_sh4_is_cached (env, address))
>> {
>> @@ -144,7 +140,7 @@ void helper_movcal(uint32_t address, uint32_t value)
>> }
>> }
>>
>> -void helper_discard_movcal_backup(void)
>> +void helper_discard_movcal_backup(CPUSH4State *env)
>> {
>> memory_content *current = env->movcal_backup;
>>
>> @@ -158,7 +154,7 @@ void helper_discard_movcal_backup(void)
>> }
>> }
>>
>> -void helper_ocbi(uint32_t address)
>> +void helper_ocbi(CPUSH4State *env, uint32_t address)
>> {
>> memory_content **current = &(env->movcal_backup);
>> while (*current)
>> @@ -167,7 +163,7 @@ void helper_ocbi(uint32_t address)
>> if ((a & ~0x1F) == (address & ~0x1F))
>> {
>> memory_content *next = (*current)->next;
>> - stl(a, (*current)->value);
>> + cpu_stl_data(env, a, (*current)->value);
>>
>> if (next == NULL)
>> {
>> @@ -181,7 +177,7 @@ void helper_ocbi(uint32_t address)
>> }
>> }
>>
>> -uint32_t helper_addc(uint32_t arg0, uint32_t arg1)
>> +uint32_t helper_addc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
>> {
>> uint32_t tmp0, tmp1;
>>
>> @@ -197,7 +193,7 @@ uint32_t helper_addc(uint32_t arg0, uint32_t arg1)
>> return arg1;
>> }
>>
>> -uint32_t helper_addv(uint32_t arg0, uint32_t arg1)
>> +uint32_t helper_addv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
>> {
>> uint32_t dest, src, ans;
>>
>> @@ -236,7 +232,7 @@ uint32_t helper_addv(uint32_t arg0, uint32_t arg1)
>> #define SETM env->sr |= SR_M
>> #define CLRM env->sr &= ~SR_M
>>
>> -uint32_t helper_div1(uint32_t arg0, uint32_t arg1)
>> +uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
>> {
>> uint32_t tmp0, tmp2;
>> uint8_t old_q, tmp1 = 0xff;
>> @@ -344,7 +340,7 @@ uint32_t helper_div1(uint32_t arg0, uint32_t arg1)
>> return arg1;
>> }
>>
>> -void helper_macl(uint32_t arg0, uint32_t arg1)
>> +void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
>> {
>> int64_t res;
>>
>> @@ -360,7 +356,7 @@ void helper_macl(uint32_t arg0, uint32_t arg1)
>> }
>> }
>>
>> -void helper_macw(uint32_t arg0, uint32_t arg1)
>> +void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
>> {
>> int64_t res;
>>
>> @@ -379,7 +375,7 @@ void helper_macw(uint32_t arg0, uint32_t arg1)
>> }
>> }
>>
>> -uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
>> +uint32_t helper_subc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
>> {
>> uint32_t tmp0, tmp1;
>>
>> @@ -395,7 +391,7 @@ uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
>> return arg1;
>> }
>>
>> -uint32_t helper_subv(uint32_t arg0, uint32_t arg1)
>> +uint32_t helper_subv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
>> {
>> int32_t dest, src, ans;
>>
>> @@ -424,17 +420,17 @@ uint32_t helper_subv(uint32_t arg0, uint32_t arg1)
>> return arg1;
>> }
>>
>> -static inline void set_t(void)
>> +static inline void set_t(CPUSH4State *env)
>> {
>> env->sr |= SR_T;
>> }
>>
>> -static inline void clr_t(void)
>> +static inline void clr_t(CPUSH4State *env)
>> {
>> env->sr &= ~SR_T;
>> }
>>
>> -void helper_ld_fpscr(uint32_t val)
>> +void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
>> {
>> env->fpscr = val & FPSCR_MASK;
>> if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
>> @@ -445,7 +441,7 @@ void helper_ld_fpscr(uint32_t val)
>> set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
>> }
>>
>> -static void update_fpscr(uintptr_t retaddr)
>> +static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
>> {
>> int xcpt, cause, enable;
>>
>> @@ -479,7 +475,7 @@ static void update_fpscr(uintptr_t retaddr)
>> cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
>> enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
>> if (cause & enable) {
>> - cpu_restore_state_from_retaddr(retaddr);
>> + cpu_restore_state_from_retaddr(env, retaddr);
>> env->exception_index = 0x120;
>> cpu_loop_exit(env);
>> }
>> @@ -496,156 +492,156 @@ float64 helper_fabs_DT(float64 t0)
>> return float64_abs(t0);
>> }
>>
>> -float32 helper_fadd_FT(float32 t0, float32 t1)
>> +float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
>> {
>> set_float_exception_flags(0, &env->fp_status);
>> t0 = float32_add(t0, t1, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return t0;
>> }
>>
>> -float64 helper_fadd_DT(float64 t0, float64 t1)
>> +float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
>> {
>> set_float_exception_flags(0, &env->fp_status);
>> t0 = float64_add(t0, t1, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return t0;
>> }
>>
>> -void helper_fcmp_eq_FT(float32 t0, float32 t1)
>> +void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
>> {
>> int relation;
>>
>> set_float_exception_flags(0, &env->fp_status);
>> relation = float32_compare(t0, t1, &env->fp_status);
>> if (unlikely(relation == float_relation_unordered)) {
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> } else if (relation == float_relation_equal) {
>> - set_t();
>> + set_t(env);
>> } else {
>> - clr_t();
>> + clr_t(env);
>> }
>> }
>>
>> -void helper_fcmp_eq_DT(float64 t0, float64 t1)
>> +void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
>> {
>> int relation;
>>
>> set_float_exception_flags(0, &env->fp_status);
>> relation = float64_compare(t0, t1, &env->fp_status);
>> if (unlikely(relation == float_relation_unordered)) {
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> } else if (relation == float_relation_equal) {
>> - set_t();
>> + set_t(env);
>> } else {
>> - clr_t();
>> + clr_t(env);
>> }
>> }
>>
>> -void helper_fcmp_gt_FT(float32 t0, float32 t1)
>> +void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
>> {
>> int relation;
>>
>> set_float_exception_flags(0, &env->fp_status);
>> relation = float32_compare(t0, t1, &env->fp_status);
>> if (unlikely(relation == float_relation_unordered)) {
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> } else if (relation == float_relation_greater) {
>> - set_t();
>> + set_t(env);
>> } else {
>> - clr_t();
>> + clr_t(env);
>> }
>> }
>>
>> -void helper_fcmp_gt_DT(float64 t0, float64 t1)
>> +void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
>> {
>> int relation;
>>
>> set_float_exception_flags(0, &env->fp_status);
>> relation = float64_compare(t0, t1, &env->fp_status);
>> if (unlikely(relation == float_relation_unordered)) {
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> } else if (relation == float_relation_greater) {
>> - set_t();
>> + set_t(env);
>> } else {
>> - clr_t();
>> + clr_t(env);
>> }
>> }
>>
>> -float64 helper_fcnvsd_FT_DT(float32 t0)
>> +float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
>> {
>> float64 ret;
>> set_float_exception_flags(0, &env->fp_status);
>> ret = float32_to_float64(t0, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return ret;
>> }
>>
>> -float32 helper_fcnvds_DT_FT(float64 t0)
>> +float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
>> {
>> float32 ret;
>> set_float_exception_flags(0, &env->fp_status);
>> ret = float64_to_float32(t0, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return ret;
>> }
>>
>> -float32 helper_fdiv_FT(float32 t0, float32 t1)
>> +float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
>> {
>> set_float_exception_flags(0, &env->fp_status);
>> t0 = float32_div(t0, t1, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return t0;
>> }
>>
>> -float64 helper_fdiv_DT(float64 t0, float64 t1)
>> +float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
>> {
>> set_float_exception_flags(0, &env->fp_status);
>> t0 = float64_div(t0, t1, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return t0;
>> }
>>
>> -float32 helper_float_FT(uint32_t t0)
>> +float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
>> {
>> float32 ret;
>> set_float_exception_flags(0, &env->fp_status);
>> ret = int32_to_float32(t0, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return ret;
>> }
>>
>> -float64 helper_float_DT(uint32_t t0)
>> +float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
>> {
>> float64 ret;
>> set_float_exception_flags(0, &env->fp_status);
>> ret = int32_to_float64(t0, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return ret;
>> }
>>
>> -float32 helper_fmac_FT(float32 t0, float32 t1, float32 t2)
>> +float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
>> {
>> set_float_exception_flags(0, &env->fp_status);
>> t0 = float32_mul(t0, t1, &env->fp_status);
>> t0 = float32_add(t0, t2, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return t0;
>> }
>>
>> -float32 helper_fmul_FT(float32 t0, float32 t1)
>> +float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
>> {
>> set_float_exception_flags(0, &env->fp_status);
>> t0 = float32_mul(t0, t1, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return t0;
>> }
>>
>> -float64 helper_fmul_DT(float64 t0, float64 t1)
>> +float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
>> {
>> set_float_exception_flags(0, &env->fp_status);
>> t0 = float64_mul(t0, t1, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return t0;
>> }
>>
>> @@ -654,57 +650,57 @@ float32 helper_fneg_T(float32 t0)
>> return float32_chs(t0);
>> }
>>
>> -float32 helper_fsqrt_FT(float32 t0)
>> +float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
>> {
>> set_float_exception_flags(0, &env->fp_status);
>> t0 = float32_sqrt(t0, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return t0;
>> }
>>
>> -float64 helper_fsqrt_DT(float64 t0)
>> +float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
>> {
>> set_float_exception_flags(0, &env->fp_status);
>> t0 = float64_sqrt(t0, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return t0;
>> }
>>
>> -float32 helper_fsub_FT(float32 t0, float32 t1)
>> +float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
>> {
>> set_float_exception_flags(0, &env->fp_status);
>> t0 = float32_sub(t0, t1, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return t0;
>> }
>>
>> -float64 helper_fsub_DT(float64 t0, float64 t1)
>> +float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
>> {
>> set_float_exception_flags(0, &env->fp_status);
>> t0 = float64_sub(t0, t1, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return t0;
>> }
>>
>> -uint32_t helper_ftrc_FT(float32 t0)
>> +uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
>> {
>> uint32_t ret;
>> set_float_exception_flags(0, &env->fp_status);
>> ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return ret;
>> }
>>
>> -uint32_t helper_ftrc_DT(float64 t0)
>> +uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
>> {
>> uint32_t ret;
>> set_float_exception_flags(0, &env->fp_status);
>> ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>> return ret;
>> }
>>
>> -void helper_fipr(uint32_t m, uint32_t n)
>> +void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
>> {
>> int bank, i;
>> float32 r, p;
>> @@ -719,12 +715,12 @@ void helper_fipr(uint32_t m, uint32_t n)
>> &env->fp_status);
>> r = float32_add(r, p, &env->fp_status);
>> }
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>>
>> env->fregs[bank + n + 3] = r;
>> }
>>
>> -void helper_ftrv(uint32_t n)
>> +void helper_ftrv(CPUSH4State *env, uint32_t n)
>> {
>> int bank_matrix, bank_vector;
>> int i, j;
>> @@ -743,7 +739,7 @@ void helper_ftrv(uint32_t n)
>> r[i] = float32_add(r[i], p, &env->fp_status);
>> }
>> }
>> - update_fpscr(GETPC());
>> + update_fpscr(env, GETPC());
>>
>> for (i = 0 ; i < 4 ; i++) {
>> env->fregs[bank_vector + i] = r[i];
>> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
>> index 6532ad2..102b1b4 100644
>> --- a/target-sh4/translate.c
>> +++ b/target-sh4/translate.c
>> @@ -276,7 +276,7 @@ static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
>> } else {
>> tcg_gen_movi_i32(cpu_pc, dest);
>> if (ctx->singlestep_enabled)
>> - gen_helper_debug();
>> + gen_helper_debug(cpu_env);
>> tcg_gen_exit_tb(0);
>> }
>> }
>> @@ -288,7 +288,7 @@ static void gen_jump(DisasContext * ctx)
>> delayed jump as immediate jump are conditinal jumps */
>> tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
>> if (ctx->singlestep_enabled)
>> - gen_helper_debug();
>> + gen_helper_debug(cpu_env);
>> tcg_gen_exit_tb(0);
>> } else {
>> gen_goto_tb(ctx, 0, ctx->delayed_pc);
>> @@ -437,7 +437,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
>> #define CHECK_NOT_DELAY_SLOT \
>> if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
>> { \
>> - gen_helper_raise_slot_illegal_instruction(); \
>> + gen_helper_raise_slot_illegal_instruction(cpu_env); \
>> ctx->bstate = BS_EXCP; \
>> return; \
>> }
>> @@ -445,9 +445,9 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
>> #define CHECK_PRIVILEGED \
>> if (IS_USER(ctx)) { \
>> if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
>> - gen_helper_raise_slot_illegal_instruction(); \
>> + gen_helper_raise_slot_illegal_instruction(cpu_env); \
>> } else { \
>> - gen_helper_raise_illegal_instruction(); \
>> + gen_helper_raise_illegal_instruction(cpu_env); \
>> } \
>> ctx->bstate = BS_EXCP; \
>> return; \
>> @@ -456,9 +456,9 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
>> #define CHECK_FPU_ENABLED \
>> if (ctx->flags & SR_FD) { \
>> if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
>> - gen_helper_raise_slot_fpu_disable(); \
>> + gen_helper_raise_slot_fpu_disable(cpu_env); \
>> } else { \
>> - gen_helper_raise_fpu_disable(); \
>> + gen_helper_raise_fpu_disable(cpu_env); \
>> } \
>> ctx->bstate = BS_EXCP; \
>> return; \
>> @@ -492,7 +492,7 @@ static void _decode_opc(DisasContext * ctx)
>> if (opcode != 0x0093 /* ocbi */
>> && opcode != 0x00c3 /* movca.l */)
>> {
>> - gen_helper_discard_movcal_backup ();
>> + gen_helper_discard_movcal_backup(cpu_env);
>> ctx->has_movcal = 0;
>> }
>> }
>> @@ -523,7 +523,7 @@ static void _decode_opc(DisasContext * ctx)
>> return;
>> case 0x0038: /* ldtlb */
>> CHECK_PRIVILEGED
>> - gen_helper_ldtlb();
>> + gen_helper_ldtlb(cpu_env);
>> return;
>> case 0x002b: /* rte */
>> CHECK_PRIVILEGED
>> @@ -551,7 +551,7 @@ static void _decode_opc(DisasContext * ctx)
>> return;
>> case 0x001b: /* sleep */
>> CHECK_PRIVILEGED
>> - gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
>> + gen_helper_sleep(cpu_env, tcg_const_i32(ctx->pc + 2));
>> return;
>> }
>>
>> @@ -761,10 +761,10 @@ static void _decode_opc(DisasContext * ctx)
>> tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
>> return;
>> case 0x300e: /* addc Rm,Rn */
>> - gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8));
>> + gen_helper_addc(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
>> return;
>> case 0x300f: /* addv Rm,Rn */
>> - gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8));
>> + gen_helper_addv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
>> return;
>> case 0x2009: /* and Rm,Rn */
>> tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
>> @@ -817,7 +817,7 @@ static void _decode_opc(DisasContext * ctx)
>> }
>> return;
>> case 0x3004: /* div1 Rm,Rn */
>> - gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8));
>> + gen_helper_div1(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
>> return;
>> case 0x300d: /* dmuls.l Rm,Rn */
>> {
>> @@ -870,7 +870,7 @@ static void _decode_opc(DisasContext * ctx)
>> tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
>> arg1 = tcg_temp_new();
>> tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
>> - gen_helper_macl(arg0, arg1);
>> + gen_helper_macl(cpu_env, arg0, arg1);
>> tcg_temp_free(arg1);
>> tcg_temp_free(arg0);
>> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
>> @@ -884,7 +884,7 @@ static void _decode_opc(DisasContext * ctx)
>> tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
>> arg1 = tcg_temp_new();
>> tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
>> - gen_helper_macw(arg0, arg1);
>> + gen_helper_macw(cpu_env, arg0, arg1);
>> tcg_temp_free(arg1);
>> tcg_temp_free(arg0);
>> tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
>> @@ -1013,10 +1013,10 @@ static void _decode_opc(DisasContext * ctx)
>> tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
>> return;
>> case 0x300a: /* subc Rm,Rn */
>> - gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8));
>> + gen_helper_subc(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
>> return;
>> case 0x300b: /* subv Rm,Rn */
>> - gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8));
>> + gen_helper_subv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
>> return;
>> case 0x2008: /* tst Rm,Rn */
>> {
>> @@ -1152,22 +1152,22 @@ static void _decode_opc(DisasContext * ctx)
>> gen_load_fpr64(fp1, DREG(B7_4));
>> switch (ctx->opcode & 0xf00f) {
>> case 0xf000: /* fadd Rm,Rn */
>> - gen_helper_fadd_DT(fp0, fp0, fp1);
>> + gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1);
>> break;
>> case 0xf001: /* fsub Rm,Rn */
>> - gen_helper_fsub_DT(fp0, fp0, fp1);
>> + gen_helper_fsub_DT(fp0, cpu_env, fp0, fp1);
>> break;
>> case 0xf002: /* fmul Rm,Rn */
>> - gen_helper_fmul_DT(fp0, fp0, fp1);
>> + gen_helper_fmul_DT(fp0, cpu_env, fp0, fp1);
>> break;
>> case 0xf003: /* fdiv Rm,Rn */
>> - gen_helper_fdiv_DT(fp0, fp0, fp1);
>> + gen_helper_fdiv_DT(fp0, cpu_env, fp0, fp1);
>> break;
>> case 0xf004: /* fcmp/eq Rm,Rn */
>> - gen_helper_fcmp_eq_DT(fp0, fp1);
>> + gen_helper_fcmp_eq_DT(cpu_env, fp0, fp1);
>> return;
>> case 0xf005: /* fcmp/gt Rm,Rn */
>> - gen_helper_fcmp_gt_DT(fp0, fp1);
>> + gen_helper_fcmp_gt_DT(cpu_env, fp0, fp1);
>> return;
>> }
>> gen_store_fpr64(fp0, DREG(B11_8));
>> @@ -1176,22 +1176,32 @@ static void _decode_opc(DisasContext * ctx)
>> } else {
>> switch (ctx->opcode & 0xf00f) {
>> case 0xf000: /* fadd Rm,Rn */
>> - gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
>> + gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_env,
>> + cpu_fregs[FREG(B11_8)],
>> + cpu_fregs[FREG(B7_4)]);
>> break;
>> case 0xf001: /* fsub Rm,Rn */
>> - gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
>> + gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_env,
>> + cpu_fregs[FREG(B11_8)],
>> + cpu_fregs[FREG(B7_4)]);
>> break;
>> case 0xf002: /* fmul Rm,Rn */
>> - gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
>> + gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_env,
>> + cpu_fregs[FREG(B11_8)],
>> + cpu_fregs[FREG(B7_4)]);
>> break;
>> case 0xf003: /* fdiv Rm,Rn */
>> - gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
>> + gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_env,
>> + cpu_fregs[FREG(B11_8)],
>> + cpu_fregs[FREG(B7_4)]);
>> break;
>> case 0xf004: /* fcmp/eq Rm,Rn */
>> - gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
>> + gen_helper_fcmp_eq_FT(cpu_env, cpu_fregs[FREG(B11_8)],
>> + cpu_fregs[FREG(B7_4)]);
>> return;
>> case 0xf005: /* fcmp/gt Rm,Rn */
>> - gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
>> + gen_helper_fcmp_gt_FT(cpu_env, cpu_fregs[FREG(B11_8)],
>> + cpu_fregs[FREG(B7_4)]);
>> return;
>> }
>> }
>> @@ -1203,8 +1213,9 @@ static void _decode_opc(DisasContext * ctx)
>> if (ctx->fpscr & FPSCR_PR) {
>> break; /* illegal instruction */
>> } else {
>> - gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)],
>> - cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)], cpu_fregs[FREG(B11_8)]);
>> + gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], cpu_env,
>> + cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)],
>> + cpu_fregs[FREG(B11_8)]);
>> return;
>> }
>> }
>> @@ -1356,7 +1367,7 @@ static void _decode_opc(DisasContext * ctx)
>> TCGv imm;
>> CHECK_NOT_DELAY_SLOT
>> imm = tcg_const_i32(B7_0);
>> - gen_helper_trapa(imm);
>> + gen_helper_trapa(cpu_env, imm);
>> tcg_temp_free(imm);
>> ctx->bstate = BS_BRANCH;
>> }
>> @@ -1531,7 +1542,7 @@ static void _decode_opc(DisasContext * ctx)
>> LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED})
>> case 0x406a: /* lds Rm,FPSCR */
>> CHECK_FPU_ENABLED
>> - gen_helper_ld_fpscr(REG(B11_8));
>> + gen_helper_ld_fpscr(cpu_env, REG(B11_8));
>> ctx->bstate = BS_STOP;
>> return;
>> case 0x4066: /* lds.l @Rm+,FPSCR */
>> @@ -1540,7 +1551,7 @@ static void _decode_opc(DisasContext * ctx)
>> TCGv addr = tcg_temp_new();
>> tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
>> tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
>> - gen_helper_ld_fpscr(addr);
>> + gen_helper_ld_fpscr(cpu_env, addr);
>> tcg_temp_free(addr);
>> ctx->bstate = BS_STOP;
>> }
>> @@ -1567,7 +1578,7 @@ static void _decode_opc(DisasContext * ctx)
>> {
>> TCGv val = tcg_temp_new();
>> tcg_gen_qemu_ld32u(val, REG(B11_8), ctx->memidx);
>> - gen_helper_movcal (REG(B11_8), val);
>> + gen_helper_movcal(cpu_env, REG(B11_8), val);
>> tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
>> }
>> ctx->has_movcal = 1;
>> @@ -1619,7 +1630,7 @@ static void _decode_opc(DisasContext * ctx)
>> break;
>> case 0x0093: /* ocbi @Rn */
>> {
>> - gen_helper_ocbi (REG(B11_8));
>> + gen_helper_ocbi(cpu_env, REG(B11_8));
>> }
>> return;
>> case 0x00a3: /* ocbp @Rn */
>> @@ -1733,12 +1744,12 @@ static void _decode_opc(DisasContext * ctx)
>> if (ctx->opcode & 0x0100)
>> break; /* illegal instruction */
>> fp = tcg_temp_new_i64();
>> - gen_helper_float_DT(fp, cpu_fpul);
>> + gen_helper_float_DT(fp, cpu_env, cpu_fpul);
>> gen_store_fpr64(fp, DREG(B11_8));
>> tcg_temp_free_i64(fp);
>> }
>> else {
>> - gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul);
>> + gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_env, cpu_fpul);
>> }
>> return;
>> case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
>> @@ -1749,11 +1760,11 @@ static void _decode_opc(DisasContext * ctx)
>> break; /* illegal instruction */
>> fp = tcg_temp_new_i64();
>> gen_load_fpr64(fp, DREG(B11_8));
>> - gen_helper_ftrc_DT(cpu_fpul, fp);
>> + gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp);
>> tcg_temp_free_i64(fp);
>> }
>> else {
>> - gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]);
>> + gen_helper_ftrc_FT(cpu_fpul, cpu_env, cpu_fregs[FREG(B11_8)]);
>> }
>> return;
>> case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
>> @@ -1783,11 +1794,12 @@ static void _decode_opc(DisasContext * ctx)
>> break; /* illegal instruction */
>> TCGv_i64 fp = tcg_temp_new_i64();
>> gen_load_fpr64(fp, DREG(B11_8));
>> - gen_helper_fsqrt_DT(fp, fp);
>> + gen_helper_fsqrt_DT(fp, cpu_env, fp);
>> gen_store_fpr64(fp, DREG(B11_8));
>> tcg_temp_free_i64(fp);
>> } else {
>> - gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
>> + gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_env,
>> + cpu_fregs[FREG(B11_8)]);
>> }
>> return;
>> case 0xf07d: /* fsrra FRn */
>> @@ -1809,7 +1821,7 @@ static void _decode_opc(DisasContext * ctx)
>> CHECK_FPU_ENABLED
>> {
>> TCGv_i64 fp = tcg_temp_new_i64();
>> - gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);
>> + gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul);
>> gen_store_fpr64(fp, DREG(B11_8));
>> tcg_temp_free_i64(fp);
>> }
>> @@ -1819,7 +1831,7 @@ static void _decode_opc(DisasContext * ctx)
>> {
>> TCGv_i64 fp = tcg_temp_new_i64();
>> gen_load_fpr64(fp, DREG(B11_8));
>> - gen_helper_fcnvds_DT_FT(cpu_fpul, fp);
>> + gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp);
>> tcg_temp_free_i64(fp);
>> }
>> return;
>> @@ -1829,7 +1841,7 @@ static void _decode_opc(DisasContext * ctx)
>> TCGv m, n;
>> m = tcg_const_i32((ctx->opcode >> 8) & 3);
>> n = tcg_const_i32((ctx->opcode >> 10) & 3);
>> - gen_helper_fipr(m, n);
>> + gen_helper_fipr(cpu_env, m, n);
>> tcg_temp_free(m);
>> tcg_temp_free(n);
>> return;
>> @@ -1841,7 +1853,7 @@ static void _decode_opc(DisasContext * ctx)
>> (ctx->fpscr & FPSCR_PR) == 0) {
>> TCGv n;
>> n = tcg_const_i32((ctx->opcode >> 10) & 3);
>> - gen_helper_ftrv(n);
>> + gen_helper_ftrv(cpu_env, n);
>> tcg_temp_free(n);
>> return;
>> }
>> @@ -1853,9 +1865,9 @@ static void _decode_opc(DisasContext * ctx)
>> fflush(stderr);
>> #endif
>> if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
>> - gen_helper_raise_slot_illegal_instruction();
>> + gen_helper_raise_slot_illegal_instruction(cpu_env);
>> } else {
>> - gen_helper_raise_illegal_instruction();
>> + gen_helper_raise_illegal_instruction(cpu_env);
>> }
>> ctx->bstate = BS_EXCP;
>> }
>> @@ -1934,7 +1946,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
>> if (ctx.pc == bp->pc) {
>> /* We have hit a breakpoint - make sure PC is up-to-date */
>> tcg_gen_movi_i32(cpu_pc, ctx.pc);
>> - gen_helper_debug();
>> + gen_helper_debug(cpu_env);
>> ctx.bstate = BS_EXCP;
>> break;
>> }
>> @@ -1958,7 +1970,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
>> fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
>> fflush(stderr);
>> #endif
>> - ctx.opcode = lduw_code(ctx.pc);
>> + ctx.opcode = cpu_lduw_code(cpu_single_env, ctx.pc);
>
> Why using cpu_single_env here, while all the code in this function uses
> the env argument to gen_intermediate_code()?
Good catch, I don't know why I did that. I'll fix it to use the env argument.
> I thought one of the goal
> of this patch series was to get rid of the global env variable.
Not that variable, only AREG0. But removing cpu_single_env could have
nice cleanup effects on their own too.
>
>> decode_opc(&ctx);
>> num_insns++;
>> ctx.pc += 2;
>> @@ -1975,7 +1987,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
>> gen_io_end();
>> if (env->singlestep_enabled) {
>> tcg_gen_movi_i32(cpu_pc, ctx.pc);
>> - gen_helper_debug();
>> + gen_helper_debug(cpu_env);
>> } else {
>> switch (ctx.bstate) {
>> case BS_STOP:
>> --
>> 1.7.2.5
>>
>>
>>
>
> --
> Aurelien Jarno GPG: 1024D/F1BCDB73
> aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread
* [Qemu-devel] [PATCH 20/21] target-mips: switch to AREG0 free mode
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (18 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 19/21] target-sh4: " Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-03 15:50 ` Aurelien Jarno
2012-09-02 17:33 ` [Qemu-devel] [PATCH 21/21] Remove unused CONFIG_TCG_PASS_AREG0 and dead code Blue Swirl
2012-09-04 18:52 ` [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Richard Henderson
21 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Aurelien Jarno
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
configure | 2 +-
target-mips/Makefile.objs | 2 -
target-mips/cpu.h | 16 +-
target-mips/helper.h | 410 +++++++++---------
target-mips/op_helper.c | 1065 ++++++++++++++++++++++++---------------------
target-mips/translate.c | 754 ++++++++++++++++----------------
6 files changed, 1163 insertions(+), 1086 deletions(-)
diff --git a/configure b/configure
index d69e43e..f60a4b6 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
case "$target_arch2" in
- alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sh4* | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
+ alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | mips* | or32 | s390x | sh4* | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
;;
esac
diff --git a/target-mips/Makefile.objs b/target-mips/Makefile.objs
index 2e0e093..ca20f21 100644
--- a/target-mips/Makefile.objs
+++ b/target-mips/Makefile.objs
@@ -1,4 +1,2 @@
obj-y += translate.o op_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index ce3467f..be4f805 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -38,10 +38,10 @@ struct CPUMIPSTLBContext {
uint32_t nb_tlb;
uint32_t tlb_in_use;
int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type);
- void (*helper_tlbwi) (void);
- void (*helper_tlbwr) (void);
- void (*helper_tlbp) (void);
- void (*helper_tlbr) (void);
+ void (*helper_tlbwi)(struct CPUMIPSState *env);
+ void (*helper_tlbwr)(struct CPUMIPSState *env);
+ void (*helper_tlbp)(struct CPUMIPSState *env);
+ void (*helper_tlbr)(struct CPUMIPSState *env);
union {
struct {
r4k_tlb_t tlb[MIPS_TLB_MAX];
@@ -485,10 +485,10 @@ int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int
target_ulong address, int rw, int access_type);
int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
target_ulong address, int rw, int access_type);
-void r4k_helper_tlbwi (void);
-void r4k_helper_tlbwr (void);
-void r4k_helper_tlbp (void);
-void r4k_helper_tlbr (void);
+void r4k_helper_tlbwi(CPUMIPSState *env);
+void r4k_helper_tlbwr(CPUMIPSState *env);
+void r4k_helper_tlbp(CPUMIPSState *env);
+void r4k_helper_tlbr(CPUMIPSState *env);
void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr,
int is_write, int is_exec, int unused, int size);
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 76fb451..109ac37 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -1,25 +1,25 @@
#include "def-helper.h"
-DEF_HELPER_2(raise_exception_err, noreturn, i32, int)
-DEF_HELPER_1(raise_exception, noreturn, i32)
+DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int)
+DEF_HELPER_2(raise_exception, noreturn, env, i32)
#ifdef TARGET_MIPS64
-DEF_HELPER_3(ldl, tl, tl, tl, int)
-DEF_HELPER_3(ldr, tl, tl, tl, int)
-DEF_HELPER_3(sdl, void, tl, tl, int)
-DEF_HELPER_3(sdr, void, tl, tl, int)
+DEF_HELPER_4(ldl, tl, env, tl, tl, int)
+DEF_HELPER_4(ldr, tl, env, tl, tl, int)
+DEF_HELPER_4(sdl, void, env, tl, tl, int)
+DEF_HELPER_4(sdr, void, env, tl, tl, int)
#endif
-DEF_HELPER_3(lwl, tl, tl, tl, int)
-DEF_HELPER_3(lwr, tl, tl, tl, int)
-DEF_HELPER_3(swl, void, tl, tl, int)
-DEF_HELPER_3(swr, void, tl, tl, int)
+DEF_HELPER_4(lwl, tl, env, tl, tl, int)
+DEF_HELPER_4(lwr, tl, env, tl, tl, int)
+DEF_HELPER_4(swl, void, env, tl, tl, int)
+DEF_HELPER_4(swr, void, env, tl, tl, int)
#ifndef CONFIG_USER_ONLY
-DEF_HELPER_2(ll, tl, tl, int)
-DEF_HELPER_3(sc, tl, tl, tl, int)
+DEF_HELPER_3(ll, tl, env, tl, int)
+DEF_HELPER_4(sc, tl, env, tl, tl, int)
#ifdef TARGET_MIPS64
-DEF_HELPER_2(lld, tl, tl, int)
-DEF_HELPER_3(scd, tl, tl, tl, int)
+DEF_HELPER_3(lld, tl, env, tl, int)
+DEF_HELPER_4(scd, tl, env, tl, tl, int)
#endif
#endif
@@ -28,195 +28,195 @@ DEF_HELPER_FLAGS_1(clz, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
#ifdef TARGET_MIPS64
DEF_HELPER_FLAGS_1(dclo, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
DEF_HELPER_FLAGS_1(dclz, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
-DEF_HELPER_2(dmult, void, tl, tl)
-DEF_HELPER_2(dmultu, void, tl, tl)
+DEF_HELPER_3(dmult, void, env, tl, tl)
+DEF_HELPER_3(dmultu, void, env, tl, tl)
#endif
-DEF_HELPER_2(muls, tl, tl, tl)
-DEF_HELPER_2(mulsu, tl, tl, tl)
-DEF_HELPER_2(macc, tl, tl, tl)
-DEF_HELPER_2(maccu, tl, tl, tl)
-DEF_HELPER_2(msac, tl, tl, tl)
-DEF_HELPER_2(msacu, tl, tl, tl)
-DEF_HELPER_2(mulhi, tl, tl, tl)
-DEF_HELPER_2(mulhiu, tl, tl, tl)
-DEF_HELPER_2(mulshi, tl, tl, tl)
-DEF_HELPER_2(mulshiu, tl, tl, tl)
-DEF_HELPER_2(macchi, tl, tl, tl)
-DEF_HELPER_2(macchiu, tl, tl, tl)
-DEF_HELPER_2(msachi, tl, tl, tl)
-DEF_HELPER_2(msachiu, tl, tl, tl)
+DEF_HELPER_3(muls, tl, env, tl, tl)
+DEF_HELPER_3(mulsu, tl, env, tl, tl)
+DEF_HELPER_3(macc, tl, env, tl, tl)
+DEF_HELPER_3(maccu, tl, env, tl, tl)
+DEF_HELPER_3(msac, tl, env, tl, tl)
+DEF_HELPER_3(msacu, tl, env, tl, tl)
+DEF_HELPER_3(mulhi, tl, env, tl, tl)
+DEF_HELPER_3(mulhiu, tl, env, tl, tl)
+DEF_HELPER_3(mulshi, tl, env, tl, tl)
+DEF_HELPER_3(mulshiu, tl, env, tl, tl)
+DEF_HELPER_3(macchi, tl, env, tl, tl)
+DEF_HELPER_3(macchiu, tl, env, tl, tl)
+DEF_HELPER_3(msachi, tl, env, tl, tl)
+DEF_HELPER_3(msachiu, tl, env, tl, tl)
#ifndef CONFIG_USER_ONLY
/* CP0 helpers */
-DEF_HELPER_0(mfc0_mvpcontrol, tl)
-DEF_HELPER_0(mfc0_mvpconf0, tl)
-DEF_HELPER_0(mfc0_mvpconf1, tl)
-DEF_HELPER_0(mftc0_vpecontrol, tl)
-DEF_HELPER_0(mftc0_vpeconf0, tl)
-DEF_HELPER_0(mfc0_random, tl)
-DEF_HELPER_0(mfc0_tcstatus, tl)
-DEF_HELPER_0(mftc0_tcstatus, tl)
-DEF_HELPER_0(mfc0_tcbind, tl)
-DEF_HELPER_0(mftc0_tcbind, tl)
-DEF_HELPER_0(mfc0_tcrestart, tl)
-DEF_HELPER_0(mftc0_tcrestart, tl)
-DEF_HELPER_0(mfc0_tchalt, tl)
-DEF_HELPER_0(mftc0_tchalt, tl)
-DEF_HELPER_0(mfc0_tccontext, tl)
-DEF_HELPER_0(mftc0_tccontext, tl)
-DEF_HELPER_0(mfc0_tcschedule, tl)
-DEF_HELPER_0(mftc0_tcschedule, tl)
-DEF_HELPER_0(mfc0_tcschefback, tl)
-DEF_HELPER_0(mftc0_tcschefback, tl)
-DEF_HELPER_0(mfc0_count, tl)
-DEF_HELPER_0(mftc0_entryhi, tl)
-DEF_HELPER_0(mftc0_status, tl)
-DEF_HELPER_0(mftc0_cause, tl)
-DEF_HELPER_0(mftc0_epc, tl)
-DEF_HELPER_0(mftc0_ebase, tl)
-DEF_HELPER_1(mftc0_configx, tl, tl)
-DEF_HELPER_0(mfc0_lladdr, tl)
-DEF_HELPER_1(mfc0_watchlo, tl, i32)
-DEF_HELPER_1(mfc0_watchhi, tl, i32)
-DEF_HELPER_0(mfc0_debug, tl)
-DEF_HELPER_0(mftc0_debug, tl)
+DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
+DEF_HELPER_1(mfc0_mvpconf0, tl, env)
+DEF_HELPER_1(mfc0_mvpconf1, tl, env)
+DEF_HELPER_1(mftc0_vpecontrol, tl, env)
+DEF_HELPER_1(mftc0_vpeconf0, tl, env)
+DEF_HELPER_1(mfc0_random, tl, env)
+DEF_HELPER_1(mfc0_tcstatus, tl, env)
+DEF_HELPER_1(mftc0_tcstatus, tl, env)
+DEF_HELPER_1(mfc0_tcbind, tl, env)
+DEF_HELPER_1(mftc0_tcbind, tl, env)
+DEF_HELPER_1(mfc0_tcrestart, tl, env)
+DEF_HELPER_1(mftc0_tcrestart, tl, env)
+DEF_HELPER_1(mfc0_tchalt, tl, env)
+DEF_HELPER_1(mftc0_tchalt, tl, env)
+DEF_HELPER_1(mfc0_tccontext, tl, env)
+DEF_HELPER_1(mftc0_tccontext, tl, env)
+DEF_HELPER_1(mfc0_tcschedule, tl, env)
+DEF_HELPER_1(mftc0_tcschedule, tl, env)
+DEF_HELPER_1(mfc0_tcschefback, tl, env)
+DEF_HELPER_1(mftc0_tcschefback, tl, env)
+DEF_HELPER_1(mfc0_count, tl, env)
+DEF_HELPER_1(mftc0_entryhi, tl, env)
+DEF_HELPER_1(mftc0_status, tl, env)
+DEF_HELPER_1(mftc0_cause, tl, env)
+DEF_HELPER_1(mftc0_epc, tl, env)
+DEF_HELPER_1(mftc0_ebase, tl, env)
+DEF_HELPER_2(mftc0_configx, tl, env, tl)
+DEF_HELPER_1(mfc0_lladdr, tl, env)
+DEF_HELPER_2(mfc0_watchlo, tl, env, i32)
+DEF_HELPER_2(mfc0_watchhi, tl, env, i32)
+DEF_HELPER_1(mfc0_debug, tl, env)
+DEF_HELPER_1(mftc0_debug, tl, env)
#ifdef TARGET_MIPS64
-DEF_HELPER_0(dmfc0_tcrestart, tl)
-DEF_HELPER_0(dmfc0_tchalt, tl)
-DEF_HELPER_0(dmfc0_tccontext, tl)
-DEF_HELPER_0(dmfc0_tcschedule, tl)
-DEF_HELPER_0(dmfc0_tcschefback, tl)
-DEF_HELPER_0(dmfc0_lladdr, tl)
-DEF_HELPER_1(dmfc0_watchlo, tl, i32)
+DEF_HELPER_1(dmfc0_tcrestart, tl, env)
+DEF_HELPER_1(dmfc0_tchalt, tl, env)
+DEF_HELPER_1(dmfc0_tccontext, tl, env)
+DEF_HELPER_1(dmfc0_tcschedule, tl, env)
+DEF_HELPER_1(dmfc0_tcschefback, tl, env)
+DEF_HELPER_1(dmfc0_lladdr, tl, env)
+DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
#endif /* TARGET_MIPS64 */
-DEF_HELPER_1(mtc0_index, void, tl)
-DEF_HELPER_1(mtc0_mvpcontrol, void, tl)
-DEF_HELPER_1(mtc0_vpecontrol, void, tl)
-DEF_HELPER_1(mttc0_vpecontrol, void, tl)
-DEF_HELPER_1(mtc0_vpeconf0, void, tl)
-DEF_HELPER_1(mttc0_vpeconf0, void, tl)
-DEF_HELPER_1(mtc0_vpeconf1, void, tl)
-DEF_HELPER_1(mtc0_yqmask, void, tl)
-DEF_HELPER_1(mtc0_vpeopt, void, tl)
-DEF_HELPER_1(mtc0_entrylo0, void, tl)
-DEF_HELPER_1(mtc0_tcstatus, void, tl)
-DEF_HELPER_1(mttc0_tcstatus, void, tl)
-DEF_HELPER_1(mtc0_tcbind, void, tl)
-DEF_HELPER_1(mttc0_tcbind, void, tl)
-DEF_HELPER_1(mtc0_tcrestart, void, tl)
-DEF_HELPER_1(mttc0_tcrestart, void, tl)
-DEF_HELPER_1(mtc0_tchalt, void, tl)
-DEF_HELPER_1(mttc0_tchalt, void, tl)
-DEF_HELPER_1(mtc0_tccontext, void, tl)
-DEF_HELPER_1(mttc0_tccontext, void, tl)
-DEF_HELPER_1(mtc0_tcschedule, void, tl)
-DEF_HELPER_1(mttc0_tcschedule, void, tl)
-DEF_HELPER_1(mtc0_tcschefback, void, tl)
-DEF_HELPER_1(mttc0_tcschefback, void, tl)
-DEF_HELPER_1(mtc0_entrylo1, void, tl)
-DEF_HELPER_1(mtc0_context, void, tl)
-DEF_HELPER_1(mtc0_pagemask, void, tl)
-DEF_HELPER_1(mtc0_pagegrain, void, tl)
-DEF_HELPER_1(mtc0_wired, void, tl)
-DEF_HELPER_1(mtc0_srsconf0, void, tl)
-DEF_HELPER_1(mtc0_srsconf1, void, tl)
-DEF_HELPER_1(mtc0_srsconf2, void, tl)
-DEF_HELPER_1(mtc0_srsconf3, void, tl)
-DEF_HELPER_1(mtc0_srsconf4, void, tl)
-DEF_HELPER_1(mtc0_hwrena, void, tl)
-DEF_HELPER_1(mtc0_count, void, tl)
-DEF_HELPER_1(mtc0_entryhi, void, tl)
-DEF_HELPER_1(mttc0_entryhi, void, tl)
-DEF_HELPER_1(mtc0_compare, void, tl)
-DEF_HELPER_1(mtc0_status, void, tl)
-DEF_HELPER_1(mttc0_status, void, tl)
-DEF_HELPER_1(mtc0_intctl, void, tl)
-DEF_HELPER_1(mtc0_srsctl, void, tl)
-DEF_HELPER_1(mtc0_cause, void, tl)
-DEF_HELPER_1(mttc0_cause, void, tl)
-DEF_HELPER_1(mtc0_ebase, void, tl)
-DEF_HELPER_1(mttc0_ebase, void, tl)
-DEF_HELPER_1(mtc0_config0, void, tl)
-DEF_HELPER_1(mtc0_config2, void, tl)
-DEF_HELPER_1(mtc0_lladdr, void, tl)
-DEF_HELPER_2(mtc0_watchlo, void, tl, i32)
-DEF_HELPER_2(mtc0_watchhi, void, tl, i32)
-DEF_HELPER_1(mtc0_xcontext, void, tl)
-DEF_HELPER_1(mtc0_framemask, void, tl)
-DEF_HELPER_1(mtc0_debug, void, tl)
-DEF_HELPER_1(mttc0_debug, void, tl)
-DEF_HELPER_1(mtc0_performance0, void, tl)
-DEF_HELPER_1(mtc0_taglo, void, tl)
-DEF_HELPER_1(mtc0_datalo, void, tl)
-DEF_HELPER_1(mtc0_taghi, void, tl)
-DEF_HELPER_1(mtc0_datahi, void, tl)
+DEF_HELPER_2(mtc0_index, void, env, tl)
+DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl)
+DEF_HELPER_2(mtc0_vpecontrol, void, env, tl)
+DEF_HELPER_2(mttc0_vpecontrol, void, env, tl)
+DEF_HELPER_2(mtc0_vpeconf0, void, env, tl)
+DEF_HELPER_2(mttc0_vpeconf0, void, env, tl)
+DEF_HELPER_2(mtc0_vpeconf1, void, env, tl)
+DEF_HELPER_2(mtc0_yqmask, void, env, tl)
+DEF_HELPER_2(mtc0_vpeopt, void, env, tl)
+DEF_HELPER_2(mtc0_entrylo0, void, env, tl)
+DEF_HELPER_2(mtc0_tcstatus, void, env, tl)
+DEF_HELPER_2(mttc0_tcstatus, void, env, tl)
+DEF_HELPER_2(mtc0_tcbind, void, env, tl)
+DEF_HELPER_2(mttc0_tcbind, void, env, tl)
+DEF_HELPER_2(mtc0_tcrestart, void, env, tl)
+DEF_HELPER_2(mttc0_tcrestart, void, env, tl)
+DEF_HELPER_2(mtc0_tchalt, void, env, tl)
+DEF_HELPER_2(mttc0_tchalt, void, env, tl)
+DEF_HELPER_2(mtc0_tccontext, void, env, tl)
+DEF_HELPER_2(mttc0_tccontext, void, env, tl)
+DEF_HELPER_2(mtc0_tcschedule, void, env, tl)
+DEF_HELPER_2(mttc0_tcschedule, void, env, tl)
+DEF_HELPER_2(mtc0_tcschefback, void, env, tl)
+DEF_HELPER_2(mttc0_tcschefback, void, env, tl)
+DEF_HELPER_2(mtc0_entrylo1, void, env, tl)
+DEF_HELPER_2(mtc0_context, void, env, tl)
+DEF_HELPER_2(mtc0_pagemask, void, env, tl)
+DEF_HELPER_2(mtc0_pagegrain, void, env, tl)
+DEF_HELPER_2(mtc0_wired, void, env, tl)
+DEF_HELPER_2(mtc0_srsconf0, void, env, tl)
+DEF_HELPER_2(mtc0_srsconf1, void, env, tl)
+DEF_HELPER_2(mtc0_srsconf2, void, env, tl)
+DEF_HELPER_2(mtc0_srsconf3, void, env, tl)
+DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
+DEF_HELPER_2(mtc0_hwrena, void, env, tl)
+DEF_HELPER_2(mtc0_count, void, env, tl)
+DEF_HELPER_2(mtc0_entryhi, void, env, tl)
+DEF_HELPER_2(mttc0_entryhi, void, env, tl)
+DEF_HELPER_2(mtc0_compare, void, env, tl)
+DEF_HELPER_2(mtc0_status, void, env, tl)
+DEF_HELPER_2(mttc0_status, void, env, tl)
+DEF_HELPER_2(mtc0_intctl, void, env, tl)
+DEF_HELPER_2(mtc0_srsctl, void, env, tl)
+DEF_HELPER_2(mtc0_cause, void, env, tl)
+DEF_HELPER_2(mttc0_cause, void, env, tl)
+DEF_HELPER_2(mtc0_ebase, void, env, tl)
+DEF_HELPER_2(mttc0_ebase, void, env, tl)
+DEF_HELPER_2(mtc0_config0, void, env, tl)
+DEF_HELPER_2(mtc0_config2, void, env, tl)
+DEF_HELPER_2(mtc0_lladdr, void, env, tl)
+DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
+DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
+DEF_HELPER_2(mtc0_xcontext, void, env, tl)
+DEF_HELPER_2(mtc0_framemask, void, env, tl)
+DEF_HELPER_2(mtc0_debug, void, env, tl)
+DEF_HELPER_2(mttc0_debug, void, env, tl)
+DEF_HELPER_2(mtc0_performance0, void, env, tl)
+DEF_HELPER_2(mtc0_taglo, void, env, tl)
+DEF_HELPER_2(mtc0_datalo, void, env, tl)
+DEF_HELPER_2(mtc0_taghi, void, env, tl)
+DEF_HELPER_2(mtc0_datahi, void, env, tl)
/* MIPS MT functions */
-DEF_HELPER_1(mftgpr, tl, i32);
-DEF_HELPER_1(mftlo, tl, i32)
-DEF_HELPER_1(mfthi, tl, i32)
-DEF_HELPER_1(mftacx, tl, i32)
-DEF_HELPER_0(mftdsp, tl)
-DEF_HELPER_2(mttgpr, void, tl, i32)
-DEF_HELPER_2(mttlo, void, tl, i32)
-DEF_HELPER_2(mtthi, void, tl, i32)
-DEF_HELPER_2(mttacx, void, tl, i32)
-DEF_HELPER_1(mttdsp, void, tl)
+DEF_HELPER_2(mftgpr, tl, env, i32);
+DEF_HELPER_2(mftlo, tl, env, i32)
+DEF_HELPER_2(mfthi, tl, env, i32)
+DEF_HELPER_2(mftacx, tl, env, i32)
+DEF_HELPER_1(mftdsp, tl, env)
+DEF_HELPER_3(mttgpr, void, env, tl, i32)
+DEF_HELPER_3(mttlo, void, env, tl, i32)
+DEF_HELPER_3(mtthi, void, env, tl, i32)
+DEF_HELPER_3(mttacx, void, env, tl, i32)
+DEF_HELPER_2(mttdsp, void, env, tl)
DEF_HELPER_0(dmt, tl)
DEF_HELPER_0(emt, tl)
-DEF_HELPER_0(dvpe, tl)
-DEF_HELPER_0(evpe, tl)
+DEF_HELPER_1(dvpe, tl, env)
+DEF_HELPER_1(evpe, tl, env)
#endif /* !CONFIG_USER_ONLY */
/* microMIPS functions */
-DEF_HELPER_3(lwm, void, tl, tl, i32);
-DEF_HELPER_3(swm, void, tl, tl, i32);
+DEF_HELPER_4(lwm, void, env, tl, tl, i32);
+DEF_HELPER_4(swm, void, env, tl, tl, i32);
#ifdef TARGET_MIPS64
-DEF_HELPER_3(ldm, void, tl, tl, i32);
-DEF_HELPER_3(sdm, void, tl, tl, i32);
+DEF_HELPER_4(ldm, void, env, tl, tl, i32);
+DEF_HELPER_4(sdm, void, env, tl, tl, i32);
#endif
DEF_HELPER_2(fork, void, tl, tl)
-DEF_HELPER_1(yield, tl, tl)
+DEF_HELPER_2(yield, tl, env, tl)
/* CP1 functions */
-DEF_HELPER_1(cfc1, tl, i32)
-DEF_HELPER_2(ctc1, void, tl, i32)
+DEF_HELPER_2(cfc1, tl, env, i32)
+DEF_HELPER_3(ctc1, void, env, tl, i32)
-DEF_HELPER_1(float_cvtd_s, i64, i32)
-DEF_HELPER_1(float_cvtd_w, i64, i32)
-DEF_HELPER_1(float_cvtd_l, i64, i64)
-DEF_HELPER_1(float_cvtl_d, i64, i64)
-DEF_HELPER_1(float_cvtl_s, i64, i32)
-DEF_HELPER_1(float_cvtps_pw, i64, i64)
-DEF_HELPER_1(float_cvtpw_ps, i64, i64)
-DEF_HELPER_1(float_cvts_d, i32, i64)
-DEF_HELPER_1(float_cvts_w, i32, i32)
-DEF_HELPER_1(float_cvts_l, i32, i64)
-DEF_HELPER_1(float_cvts_pl, i32, i32)
-DEF_HELPER_1(float_cvts_pu, i32, i32)
-DEF_HELPER_1(float_cvtw_s, i32, i32)
-DEF_HELPER_1(float_cvtw_d, i32, i64)
+DEF_HELPER_2(float_cvtd_s, i64, env, i32)
+DEF_HELPER_2(float_cvtd_w, i64, env, i32)
+DEF_HELPER_2(float_cvtd_l, i64, env, i64)
+DEF_HELPER_2(float_cvtl_d, i64, env, i64)
+DEF_HELPER_2(float_cvtl_s, i64, env, i32)
+DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
+DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
+DEF_HELPER_2(float_cvts_d, i32, env, i64)
+DEF_HELPER_2(float_cvts_w, i32, env, i32)
+DEF_HELPER_2(float_cvts_l, i32, env, i64)
+DEF_HELPER_2(float_cvts_pl, i32, env, i32)
+DEF_HELPER_2(float_cvts_pu, i32, env, i32)
+DEF_HELPER_2(float_cvtw_s, i32, env, i32)
+DEF_HELPER_2(float_cvtw_d, i32, env, i64)
-DEF_HELPER_2(float_addr_ps, i64, i64, i64)
-DEF_HELPER_2(float_mulr_ps, i64, i64, i64)
+DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
+DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
-#define FOP_PROTO(op) \
-DEF_HELPER_1(float_ ## op ## l_s, i64, i32) \
-DEF_HELPER_1(float_ ## op ## l_d, i64, i64) \
-DEF_HELPER_1(float_ ## op ## w_s, i32, i32) \
-DEF_HELPER_1(float_ ## op ## w_d, i32, i64)
+#define FOP_PROTO(op) \
+DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \
+DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \
+DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64)
FOP_PROTO(round)
FOP_PROTO(trunc)
FOP_PROTO(ceil)
FOP_PROTO(floor)
#undef FOP_PROTO
-#define FOP_PROTO(op) \
-DEF_HELPER_1(float_ ## op ## _s, i32, i32) \
-DEF_HELPER_1(float_ ## op ## _d, i64, i64)
+#define FOP_PROTO(op) \
+DEF_HELPER_2(float_ ## op ## _s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## _d, i64, env, i64)
FOP_PROTO(sqrt)
FOP_PROTO(rsqrt)
FOP_PROTO(recip)
@@ -228,14 +228,20 @@ DEF_HELPER_1(float_ ## op ## _d, i64, i64) \
DEF_HELPER_1(float_ ## op ## _ps, i64, i64)
FOP_PROTO(abs)
FOP_PROTO(chs)
+#undef FOP_PROTO
+
+#define FOP_PROTO(op) \
+DEF_HELPER_2(float_ ## op ## _s, i32, env, i32) \
+DEF_HELPER_2(float_ ## op ## _d, i64, env, i64) \
+DEF_HELPER_2(float_ ## op ## _ps, i64, env, i64)
FOP_PROTO(recip1)
FOP_PROTO(rsqrt1)
#undef FOP_PROTO
-#define FOP_PROTO(op) \
-DEF_HELPER_2(float_ ## op ## _s, i32, i32, i32) \
-DEF_HELPER_2(float_ ## op ## _d, i64, i64, i64) \
-DEF_HELPER_2(float_ ## op ## _ps, i64, i64, i64)
+#define FOP_PROTO(op) \
+DEF_HELPER_3(float_ ## op ## _s, i32, env, i32, i32) \
+DEF_HELPER_3(float_ ## op ## _d, i64, env, i64, i64) \
+DEF_HELPER_3(float_ ## op ## _ps, i64, env, i64, i64)
FOP_PROTO(add)
FOP_PROTO(sub)
FOP_PROTO(mul)
@@ -244,23 +250,23 @@ FOP_PROTO(recip2)
FOP_PROTO(rsqrt2)
#undef FOP_PROTO
-#define FOP_PROTO(op) \
-DEF_HELPER_3(float_ ## op ## _s, i32, i32, i32, i32) \
-DEF_HELPER_3(float_ ## op ## _d, i64, i64, i64, i64) \
-DEF_HELPER_3(float_ ## op ## _ps, i64, i64, i64, i64)
+#define FOP_PROTO(op) \
+DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \
+DEF_HELPER_4(float_ ## op ## _d, i64, env, i64, i64, i64) \
+DEF_HELPER_4(float_ ## op ## _ps, i64, env, i64, i64, i64)
FOP_PROTO(muladd)
FOP_PROTO(mulsub)
FOP_PROTO(nmuladd)
FOP_PROTO(nmulsub)
#undef FOP_PROTO
-#define FOP_PROTO(op) \
-DEF_HELPER_3(cmp_d_ ## op, void, i64, i64, int) \
-DEF_HELPER_3(cmpabs_d_ ## op, void, i64, i64, int) \
-DEF_HELPER_3(cmp_s_ ## op, void, i32, i32, int) \
-DEF_HELPER_3(cmpabs_s_ ## op, void, i32, i32, int) \
-DEF_HELPER_3(cmp_ps_ ## op, void, i64, i64, int) \
-DEF_HELPER_3(cmpabs_ps_ ## op, void, i64, i64, int)
+#define FOP_PROTO(op) \
+DEF_HELPER_4(cmp_d_ ## op, void, env, i64, i64, int) \
+DEF_HELPER_4(cmpabs_d_ ## op, void, env, i64, i64, int) \
+DEF_HELPER_4(cmp_s_ ## op, void, env, i32, i32, int) \
+DEF_HELPER_4(cmpabs_s_ ## op, void, env, i32, i32, int) \
+DEF_HELPER_4(cmp_ps_ ## op, void, env, i64, i64, int) \
+DEF_HELPER_4(cmpabs_ps_ ## op, void, env, i64, i64, int)
FOP_PROTO(f)
FOP_PROTO(un)
FOP_PROTO(eq)
@@ -281,20 +287,20 @@ FOP_PROTO(ngt)
/* Special functions */
#ifndef CONFIG_USER_ONLY
-DEF_HELPER_0(tlbwi, void)
-DEF_HELPER_0(tlbwr, void)
-DEF_HELPER_0(tlbp, void)
-DEF_HELPER_0(tlbr, void)
-DEF_HELPER_0(di, tl)
-DEF_HELPER_0(ei, tl)
-DEF_HELPER_0(eret, void)
-DEF_HELPER_0(deret, void)
+DEF_HELPER_1(tlbwi, void, env)
+DEF_HELPER_1(tlbwr, void, env)
+DEF_HELPER_1(tlbp, void, env)
+DEF_HELPER_1(tlbr, void, env)
+DEF_HELPER_1(di, tl, env)
+DEF_HELPER_1(ei, tl, env)
+DEF_HELPER_1(eret, void, env)
+DEF_HELPER_1(deret, void, env)
#endif /* !CONFIG_USER_ONLY */
-DEF_HELPER_0(rdhwr_cpunum, tl)
-DEF_HELPER_0(rdhwr_synci_step, tl)
-DEF_HELPER_0(rdhwr_cc, tl)
-DEF_HELPER_0(rdhwr_ccres, tl)
-DEF_HELPER_1(pmon, void, int)
-DEF_HELPER_0(wait, void)
+DEF_HELPER_1(rdhwr_cpunum, tl, env)
+DEF_HELPER_1(rdhwr_synci_step, tl, env)
+DEF_HELPER_1(rdhwr_cc, tl, env)
+DEF_HELPER_1(rdhwr_ccres, tl, env)
+DEF_HELPER_2(pmon, void, env, int)
+DEF_HELPER_1(wait, void, env)
#include "def-helper.h"
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index e5bc93e..d2a8a55 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -18,8 +18,6 @@
*/
#include <stdlib.h>
#include "cpu.h"
-#include "dyngen-exec.h"
-
#include "host-utils.h"
#include "helper.h"
@@ -84,7 +82,8 @@ static inline void compute_hflags(CPUMIPSState *env)
/*****************************************************************************/
/* Exceptions processing helpers */
-void helper_raise_exception_err (uint32_t exception, int error_code)
+void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
+ int error_code)
{
#if 1
if (exception < 0x100)
@@ -95,13 +94,13 @@ void helper_raise_exception_err (uint32_t exception, int error_code)
cpu_loop_exit(env);
}
-void helper_raise_exception (uint32_t exception)
+void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
{
- helper_raise_exception_err(exception, 0);
+ helper_raise_exception_err(env, exception, 0);
}
#if !defined(CONFIG_USER_ONLY)
-static void do_restore_state(uintptr_t pc)
+static void do_restore_state(CPUMIPSState *env, uintptr_t pc)
{
TranslationBlock *tb;
@@ -114,20 +113,22 @@ static void do_restore_state(uintptr_t pc)
#if defined(CONFIG_USER_ONLY)
#define HELPER_LD(name, insn, type) \
-static inline type do_##name(target_ulong addr, int mem_idx) \
+static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
+ int mem_idx) \
{ \
return (type) insn##_raw(addr); \
}
#else
#define HELPER_LD(name, insn, type) \
-static inline type do_##name(target_ulong addr, int mem_idx) \
+static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
+ int mem_idx) \
{ \
switch (mem_idx) \
{ \
- case 0: return (type) insn##_kernel(addr); break; \
- case 1: return (type) insn##_super(addr); break; \
+ case 0: return (type) cpu_##insn##_kernel(env, addr); break; \
+ case 1: return (type) cpu_##insn##_super(env, addr); break; \
default: \
- case 2: return (type) insn##_user(addr); break; \
+ case 2: return (type) cpu_##insn##_user(env, addr); break; \
} \
}
#endif
@@ -140,20 +141,22 @@ HELPER_LD(ld, ldq, int64_t)
#if defined(CONFIG_USER_ONLY)
#define HELPER_ST(name, insn, type) \
-static inline void do_##name(target_ulong addr, type val, int mem_idx) \
+static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
+ type val, int mem_idx) \
{ \
insn##_raw(addr, val); \
}
#else
#define HELPER_ST(name, insn, type) \
-static inline void do_##name(target_ulong addr, type val, int mem_idx) \
+static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
+ type val, int mem_idx) \
{ \
switch (mem_idx) \
{ \
- case 0: insn##_kernel(addr, val); break; \
- case 1: insn##_super(addr, val); break; \
+ case 0: cpu_##insn##_kernel(env, addr, val); break; \
+ case 1: cpu_##insn##_super(env, addr, val); break; \
default: \
- case 2: insn##_user(addr, val); break; \
+ case 2: cpu_##insn##_user(env, addr, val); break; \
} \
}
#endif
@@ -187,12 +190,12 @@ target_ulong helper_dclz (target_ulong arg1)
#endif /* TARGET_MIPS64 */
/* 64 bits arithmetic for 32 bits hosts */
-static inline uint64_t get_HILO (void)
+static inline uint64_t get_HILO(CPUMIPSState *env)
{
return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
}
-static inline target_ulong set_HIT0_LO(uint64_t HILO)
+static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
{
target_ulong tmp;
env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
@@ -200,7 +203,7 @@ static inline target_ulong set_HIT0_LO(uint64_t HILO)
return tmp;
}
-static inline target_ulong set_HI_LOT0(uint64_t HILO)
+static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
{
target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
env->active_tc.HI[0] = (int32_t)(HILO >> 32);
@@ -208,91 +211,110 @@ static inline target_ulong set_HI_LOT0(uint64_t HILO)
}
/* Multiplication variants of the vr54xx. */
-target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
+target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HI_LOT0(0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
+ return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
+ (int64_t)(int32_t)arg2));
}
-target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
+target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HI_LOT0(0 - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
+ return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
+ (uint64_t)(uint32_t)arg2);
}
-target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
+target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HI_LOT0((int64_t)get_HILO() + (int64_t)(int32_t)arg1 *
- (int64_t)(int32_t)arg2);
+ return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
+ (int64_t)(int32_t)arg2);
}
-target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
+target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HIT0_LO((int64_t)get_HILO() + (int64_t)(int32_t)arg1 *
- (int64_t)(int32_t)arg2);
+ return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
+ (int64_t)(int32_t)arg2);
}
-target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
+target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HI_LOT0((uint64_t)get_HILO() + (uint64_t)(uint32_t)arg1 *
- (uint64_t)(uint32_t)arg2);
+ return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
+ (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
}
-target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
+target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HIT0_LO((uint64_t)get_HILO() + (uint64_t)(uint32_t)arg1 *
- (uint64_t)(uint32_t)arg2);
+ return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
+ (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
}
-target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
+target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HI_LOT0((int64_t)get_HILO() - (int64_t)(int32_t)arg1 *
- (int64_t)(int32_t)arg2);
+ return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
+ (int64_t)(int32_t)arg2);
}
-target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
+target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HIT0_LO((int64_t)get_HILO() - (int64_t)(int32_t)arg1 *
- (int64_t)(int32_t)arg2);
+ return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
+ (int64_t)(int32_t)arg2);
}
-target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
+target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HI_LOT0((uint64_t)get_HILO() - (uint64_t)(uint32_t)arg1 *
- (uint64_t)(uint32_t)arg2);
+ return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
+ (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
}
-target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
+target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HIT0_LO((uint64_t)get_HILO() - (uint64_t)(uint32_t)arg1 *
- (uint64_t)(uint32_t)arg2);
+ return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
+ (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
}
-target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
+target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HIT0_LO((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
+ return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
}
-target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
+target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HIT0_LO((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
+ return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
+ (uint64_t)(uint32_t)arg2);
}
-target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
+target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HIT0_LO(0 - (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
+ return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
+ (int64_t)(int32_t)arg2);
}
-target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
+target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2)
{
- return set_HIT0_LO(0 - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
+ return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
+ (uint64_t)(uint32_t)arg2);
}
#ifdef TARGET_MIPS64
-void helper_dmult (target_ulong arg1, target_ulong arg2)
+void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
{
muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
}
-void helper_dmultu (target_ulong arg1, target_ulong arg2)
+void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
{
mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
}
@@ -300,7 +322,9 @@ void helper_dmultu (target_ulong arg1, target_ulong arg2)
#ifndef CONFIG_USER_ONLY
-static inline target_phys_addr_t do_translate_address(target_ulong address, int rw)
+static inline target_phys_addr_t do_translate_address(CPUMIPSState *env,
+ target_ulong address,
+ int rw)
{
target_phys_addr_t lladdr;
@@ -314,10 +338,10 @@ static inline target_phys_addr_t do_translate_address(target_ulong address, int
}
#define HELPER_LD_ATOMIC(name, insn) \
-target_ulong helper_##name(target_ulong arg, int mem_idx) \
+target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
{ \
- env->lladdr = do_translate_address(arg, 0); \
- env->llval = do_##insn(arg, mem_idx); \
+ env->lladdr = do_translate_address(env, arg, 0); \
+ env->llval = do_##insn(env, arg, mem_idx); \
return env->llval; \
}
HELPER_LD_ATOMIC(ll, lw)
@@ -327,18 +351,19 @@ HELPER_LD_ATOMIC(lld, ld)
#undef HELPER_LD_ATOMIC
#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
-target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
+target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
+ target_ulong arg2, int mem_idx) \
{ \
target_long tmp; \
\
if (arg2 & almask) { \
env->CP0_BadVAddr = arg2; \
- helper_raise_exception(EXCP_AdES); \
+ helper_raise_exception(env, EXCP_AdES); \
} \
- if (do_translate_address(arg2, 1) == env->lladdr) { \
- tmp = do_##ld_insn(arg2, mem_idx); \
+ if (do_translate_address(env, arg2, 1) == env->lladdr) { \
+ tmp = do_##ld_insn(env, arg2, mem_idx); \
if (tmp == env->llval) { \
- do_##st_insn(arg2, arg1, mem_idx); \
+ do_##st_insn(env, arg2, arg1, mem_idx); \
return 1; \
} \
} \
@@ -359,80 +384,84 @@ HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
#define GET_OFFSET(addr, offset) (addr - (offset))
#endif
-target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
+target_ulong helper_lwl(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2, int mem_idx)
{
target_ulong tmp;
- tmp = do_lbu(arg2, mem_idx);
+ tmp = do_lbu(env, arg2, mem_idx);
arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
if (GET_LMASK(arg2) <= 2) {
- tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx);
arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
}
if (GET_LMASK(arg2) <= 1) {
- tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx);
arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
}
if (GET_LMASK(arg2) == 0) {
- tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx);
arg1 = (arg1 & 0xFFFFFF00) | tmp;
}
return (int32_t)arg1;
}
-target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
+target_ulong helper_lwr(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2, int mem_idx)
{
target_ulong tmp;
- tmp = do_lbu(arg2, mem_idx);
+ tmp = do_lbu(env, arg2, mem_idx);
arg1 = (arg1 & 0xFFFFFF00) | tmp;
if (GET_LMASK(arg2) >= 1) {
- tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx);
arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
}
if (GET_LMASK(arg2) >= 2) {
- tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx);
arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
}
if (GET_LMASK(arg2) == 3) {
- tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx);
arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
}
return (int32_t)arg1;
}
-void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
+void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+ int mem_idx)
{
- do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx);
+ do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
if (GET_LMASK(arg2) <= 2)
- do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
if (GET_LMASK(arg2) <= 1)
- do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
if (GET_LMASK(arg2) == 0)
- do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
+ do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
}
-void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
+void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+ int mem_idx)
{
- do_sb(arg2, (uint8_t)arg1, mem_idx);
+ do_sb(env, arg2, (uint8_t)arg1, mem_idx);
if (GET_LMASK(arg2) >= 1)
- do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
if (GET_LMASK(arg2) >= 2)
- do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
if (GET_LMASK(arg2) == 3)
- do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
}
#if defined(TARGET_MIPS64)
@@ -445,167 +474,172 @@ void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
#define GET_LMASK64(v) (((v) & 7) ^ 7)
#endif
-target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
+target_ulong helper_ldl(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2, int mem_idx)
{
uint64_t tmp;
- tmp = do_lbu(arg2, mem_idx);
+ tmp = do_lbu(env, arg2, mem_idx);
arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
if (GET_LMASK64(arg2) <= 6) {
- tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx);
arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
}
if (GET_LMASK64(arg2) <= 5) {
- tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx);
arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
}
if (GET_LMASK64(arg2) <= 4) {
- tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx);
arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
}
if (GET_LMASK64(arg2) <= 3) {
- tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, 4), mem_idx);
arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
}
if (GET_LMASK64(arg2) <= 2) {
- tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, 5), mem_idx);
arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
}
if (GET_LMASK64(arg2) <= 1) {
- tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, 6), mem_idx);
arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
}
if (GET_LMASK64(arg2) == 0) {
- tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, 7), mem_idx);
arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
}
return arg1;
}
-target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
+target_ulong helper_ldr(CPUMIPSState *env, target_ulong arg1,
+ target_ulong arg2, int mem_idx)
{
uint64_t tmp;
- tmp = do_lbu(arg2, mem_idx);
+ tmp = do_lbu(env, arg2, mem_idx);
arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
if (GET_LMASK64(arg2) >= 1) {
- tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx);
arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
}
if (GET_LMASK64(arg2) >= 2) {
- tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx);
arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
}
if (GET_LMASK64(arg2) >= 3) {
- tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx);
arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
}
if (GET_LMASK64(arg2) >= 4) {
- tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, -4), mem_idx);
arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
}
if (GET_LMASK64(arg2) >= 5) {
- tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, -5), mem_idx);
arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
}
if (GET_LMASK64(arg2) >= 6) {
- tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, -6), mem_idx);
arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
}
if (GET_LMASK64(arg2) == 7) {
- tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx);
+ tmp = do_lbu(env, GET_OFFSET(arg2, -7), mem_idx);
arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
}
return arg1;
}
-void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
+void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+ int mem_idx)
{
- do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx);
+ do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
if (GET_LMASK64(arg2) <= 6)
- do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
if (GET_LMASK64(arg2) <= 5)
- do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
if (GET_LMASK64(arg2) <= 4)
- do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
if (GET_LMASK64(arg2) <= 3)
- do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
if (GET_LMASK64(arg2) <= 2)
- do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
if (GET_LMASK64(arg2) <= 1)
- do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
if (GET_LMASK64(arg2) <= 0)
- do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
+ do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
}
-void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
+void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+ int mem_idx)
{
- do_sb(arg2, (uint8_t)arg1, mem_idx);
+ do_sb(env, arg2, (uint8_t)arg1, mem_idx);
if (GET_LMASK64(arg2) >= 1)
- do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
if (GET_LMASK64(arg2) >= 2)
- do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
if (GET_LMASK64(arg2) >= 3)
- do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
if (GET_LMASK64(arg2) >= 4)
- do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
if (GET_LMASK64(arg2) >= 5)
- do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
if (GET_LMASK64(arg2) >= 6)
- do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
if (GET_LMASK64(arg2) == 7)
- do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
+ do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
}
#endif /* TARGET_MIPS64 */
static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
-void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
+void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
+ uint32_t mem_idx)
{
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
#ifdef CONFIG_USER_ONLY
#undef ldfun
-#define ldfun ldl_raw
+#define ldfun(env, addr) ldl_raw(addr)
#else
- uint32_t (*ldfun)(target_ulong);
+ uint32_t (*ldfun)(CPUMIPSState *env, target_ulong);
switch (mem_idx)
{
- case 0: ldfun = ldl_kernel; break;
- case 1: ldfun = ldl_super; break;
+ case 0: ldfun = cpu_ldl_kernel; break;
+ case 1: ldfun = cpu_ldl_super; break;
default:
- case 2: ldfun = ldl_user; break;
+ case 2: ldfun = cpu_ldl_user; break;
}
#endif
@@ -613,32 +647,33 @@ void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
target_ulong i;
for (i = 0; i < base_reglist; i++) {
- env->active_tc.gpr[multiple_regs[i]] = (target_long) ldfun(addr);
+ env->active_tc.gpr[multiple_regs[i]] = (target_long)ldfun(env, addr);
addr += 4;
}
}
if (do_r31) {
- env->active_tc.gpr[31] = (target_long) ldfun(addr);
+ env->active_tc.gpr[31] = (target_long)ldfun(env, addr);
}
}
-void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
+void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
+ uint32_t mem_idx)
{
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
#ifdef CONFIG_USER_ONLY
#undef stfun
-#define stfun stl_raw
+#define stfun(env, addr, val) stl_raw(addr, val)
#else
- void (*stfun)(target_ulong, uint32_t);
+ void (*stfun)(CPUMIPSState *env, target_ulong, uint32_t);
switch (mem_idx)
{
- case 0: stfun = stl_kernel; break;
- case 1: stfun = stl_super; break;
+ case 0: stfun = cpu_stl_kernel; break;
+ case 1: stfun = cpu_stl_super; break;
default:
- case 2: stfun = stl_user; break;
+ case 2: stfun = cpu_stl_user; break;
}
#endif
@@ -646,33 +681,34 @@ void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
target_ulong i;
for (i = 0; i < base_reglist; i++) {
- stfun(addr, env->active_tc.gpr[multiple_regs[i]]);
+ stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]);
addr += 4;
}
}
if (do_r31) {
- stfun(addr, env->active_tc.gpr[31]);
+ stfun(env, addr, env->active_tc.gpr[31]);
}
}
#if defined(TARGET_MIPS64)
-void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
+void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
+ uint32_t mem_idx)
{
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
#ifdef CONFIG_USER_ONLY
#undef ldfun
-#define ldfun ldq_raw
+#define ldfun(env, addr) ldq_raw(addr)
#else
- uint64_t (*ldfun)(target_ulong);
+ uint64_t (*ldfun)(CPUMIPSState *env, target_ulong);
switch (mem_idx)
{
- case 0: ldfun = ldq_kernel; break;
- case 1: ldfun = ldq_super; break;
+ case 0: ldfun = cpu_ldq_kernel; break;
+ case 1: ldfun = cpu_ldq_super; break;
default:
- case 2: ldfun = ldq_user; break;
+ case 2: ldfun = cpu_ldq_user; break;
}
#endif
@@ -680,32 +716,33 @@ void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
target_ulong i;
for (i = 0; i < base_reglist; i++) {
- env->active_tc.gpr[multiple_regs[i]] = ldfun(addr);
+ env->active_tc.gpr[multiple_regs[i]] = ldfun(env, addr);
addr += 8;
}
}
if (do_r31) {
- env->active_tc.gpr[31] = ldfun(addr);
+ env->active_tc.gpr[31] = ldfun(env, addr);
}
}
-void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
+void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
+ uint32_t mem_idx)
{
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
#ifdef CONFIG_USER_ONLY
#undef stfun
-#define stfun stq_raw
+#define stfun(env, addr, val) stq_raw(addr, val)
#else
- void (*stfun)(target_ulong, uint64_t);
+ void (*stfun)(CPUMIPSState *env, target_ulong, uint64_t);
switch (mem_idx)
{
- case 0: stfun = stq_kernel; break;
- case 1: stfun = stq_super; break;
+ case 0: stfun = cpu_stq_kernel; break;
+ case 1: stfun = cpu_stq_super; break;
default:
- case 2: stfun = stq_user; break;
+ case 2: stfun = cpu_stq_user; break;
}
#endif
@@ -713,13 +750,13 @@ void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
target_ulong i;
for (i = 0; i < base_reglist; i++) {
- stfun(addr, env->active_tc.gpr[multiple_regs[i]]);
+ stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]);
addr += 8;
}
}
if (do_r31) {
- stfun(addr, env->active_tc.gpr[31]);
+ stfun(env, addr, env->active_tc.gpr[31]);
}
}
#endif
@@ -772,7 +809,7 @@ static inline void mips_tc_sleep(CPUMIPSState *c, int tc)
FIXME: This code assumes that all VPEs have the same number of TCs,
which depends on runtime setup. Can probably be fixed by
walking the list of CPUMIPSStates. */
-static CPUMIPSState *mips_cpu_map_tc(int *tc)
+static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
{
CPUMIPSState *other;
int vpe_idx, nr_threads = env->nr_threads;
@@ -799,7 +836,7 @@ static CPUMIPSState *mips_cpu_map_tc(int *tc)
These helper call synchronizes the regs for a given cpu. */
/* Called for updates to CP0_Status. */
-static void sync_c0_status(CPUMIPSState *cpu, int tc)
+static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
{
int32_t tcstatus, *tcst;
uint32_t v = cpu->CP0_Status;
@@ -834,7 +871,8 @@ static void sync_c0_status(CPUMIPSState *cpu, int tc)
}
/* Called for updates to CP0_TCStatus. */
-static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, target_ulong v)
+static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
+ target_ulong v)
{
uint32_t status;
uint32_t tcu, tmx, tasid, tksu;
@@ -883,35 +921,35 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
}
/* CP0 helpers */
-target_ulong helper_mfc0_mvpcontrol (void)
+target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
{
return env->mvp->CP0_MVPControl;
}
-target_ulong helper_mfc0_mvpconf0 (void)
+target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
{
return env->mvp->CP0_MVPConf0;
}
-target_ulong helper_mfc0_mvpconf1 (void)
+target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
{
return env->mvp->CP0_MVPConf1;
}
-target_ulong helper_mfc0_random (void)
+target_ulong helper_mfc0_random(CPUMIPSState *env)
{
return (int32_t)cpu_mips_get_random(env);
}
-target_ulong helper_mfc0_tcstatus (void)
+target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
{
return env->active_tc.CP0_TCStatus;
}
-target_ulong helper_mftc0_tcstatus(void)
+target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCStatus;
@@ -919,15 +957,15 @@ target_ulong helper_mftc0_tcstatus(void)
return other->tcs[other_tc].CP0_TCStatus;
}
-target_ulong helper_mfc0_tcbind (void)
+target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
{
return env->active_tc.CP0_TCBind;
}
-target_ulong helper_mftc0_tcbind(void)
+target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCBind;
@@ -935,15 +973,15 @@ target_ulong helper_mftc0_tcbind(void)
return other->tcs[other_tc].CP0_TCBind;
}
-target_ulong helper_mfc0_tcrestart (void)
+target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
{
return env->active_tc.PC;
}
-target_ulong helper_mftc0_tcrestart(void)
+target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.PC;
@@ -951,15 +989,15 @@ target_ulong helper_mftc0_tcrestart(void)
return other->tcs[other_tc].PC;
}
-target_ulong helper_mfc0_tchalt (void)
+target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
{
return env->active_tc.CP0_TCHalt;
}
-target_ulong helper_mftc0_tchalt(void)
+target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCHalt;
@@ -967,15 +1005,15 @@ target_ulong helper_mftc0_tchalt(void)
return other->tcs[other_tc].CP0_TCHalt;
}
-target_ulong helper_mfc0_tccontext (void)
+target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
{
return env->active_tc.CP0_TCContext;
}
-target_ulong helper_mftc0_tccontext(void)
+target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCContext;
@@ -983,15 +1021,15 @@ target_ulong helper_mftc0_tccontext(void)
return other->tcs[other_tc].CP0_TCContext;
}
-target_ulong helper_mfc0_tcschedule (void)
+target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
{
return env->active_tc.CP0_TCSchedule;
}
-target_ulong helper_mftc0_tcschedule(void)
+target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCSchedule;
@@ -999,15 +1037,15 @@ target_ulong helper_mftc0_tcschedule(void)
return other->tcs[other_tc].CP0_TCSchedule;
}
-target_ulong helper_mfc0_tcschefback (void)
+target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
{
return env->active_tc.CP0_TCScheFBack;
}
-target_ulong helper_mftc0_tcschefback(void)
+target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCScheFBack;
@@ -1015,24 +1053,24 @@ target_ulong helper_mftc0_tcschefback(void)
return other->tcs[other_tc].CP0_TCScheFBack;
}
-target_ulong helper_mfc0_count (void)
+target_ulong helper_mfc0_count(CPUMIPSState *env)
{
return (int32_t)cpu_mips_get_count(env);
}
-target_ulong helper_mftc0_entryhi(void)
+target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
return other->CP0_EntryHi;
}
-target_ulong helper_mftc0_cause(void)
+target_ulong helper_mftc0_cause(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
int32_t tccause;
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc) {
tccause = other->CP0_Cause;
@@ -1043,30 +1081,30 @@ target_ulong helper_mftc0_cause(void)
return tccause;
}
-target_ulong helper_mftc0_status(void)
+target_ulong helper_mftc0_status(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
return other->CP0_Status;
}
-target_ulong helper_mfc0_lladdr (void)
+target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
{
return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
}
-target_ulong helper_mfc0_watchlo (uint32_t sel)
+target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
{
return (int32_t)env->CP0_WatchLo[sel];
}
-target_ulong helper_mfc0_watchhi (uint32_t sel)
+target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
{
return env->CP0_WatchHi[sel];
}
-target_ulong helper_mfc0_debug (void)
+target_ulong helper_mfc0_debug(CPUMIPSState *env)
{
target_ulong t0 = env->CP0_Debug;
if (env->hflags & MIPS_HFLAG_DM)
@@ -1075,11 +1113,11 @@ target_ulong helper_mfc0_debug (void)
return t0;
}
-target_ulong helper_mftc0_debug(void)
+target_ulong helper_mftc0_debug(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
int32_t tcstatus;
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
tcstatus = other->active_tc.CP0_Debug_tcstatus;
@@ -1092,43 +1130,43 @@ target_ulong helper_mftc0_debug(void)
}
#if defined(TARGET_MIPS64)
-target_ulong helper_dmfc0_tcrestart (void)
+target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
{
return env->active_tc.PC;
}
-target_ulong helper_dmfc0_tchalt (void)
+target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
{
return env->active_tc.CP0_TCHalt;
}
-target_ulong helper_dmfc0_tccontext (void)
+target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
{
return env->active_tc.CP0_TCContext;
}
-target_ulong helper_dmfc0_tcschedule (void)
+target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
{
return env->active_tc.CP0_TCSchedule;
}
-target_ulong helper_dmfc0_tcschefback (void)
+target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
{
return env->active_tc.CP0_TCScheFBack;
}
-target_ulong helper_dmfc0_lladdr (void)
+target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
{
return env->lladdr >> env->CP0_LLAddr_shift;
}
-target_ulong helper_dmfc0_watchlo (uint32_t sel)
+target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
{
return env->CP0_WatchLo[sel];
}
#endif /* TARGET_MIPS64 */
-void helper_mtc0_index (target_ulong arg1)
+void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
{
int num = 1;
unsigned int tmp = env->tlb->nb_tlb;
@@ -1140,7 +1178,7 @@ void helper_mtc0_index (target_ulong arg1)
env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
}
-void helper_mtc0_mvpcontrol (target_ulong arg1)
+void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
{
uint32_t mask = 0;
uint32_t newval;
@@ -1157,7 +1195,7 @@ void helper_mtc0_mvpcontrol (target_ulong arg1)
env->mvp->CP0_MVPControl = newval;
}
-void helper_mtc0_vpecontrol (target_ulong arg1)
+void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
{
uint32_t mask;
uint32_t newval;
@@ -1174,10 +1212,10 @@ void helper_mtc0_vpecontrol (target_ulong arg1)
env->CP0_VPEControl = newval;
}
-void helper_mttc0_vpecontrol(target_ulong arg1)
+void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
uint32_t mask;
uint32_t newval;
@@ -1190,23 +1228,23 @@ void helper_mttc0_vpecontrol(target_ulong arg1)
other->CP0_VPEControl = newval;
}
-target_ulong helper_mftc0_vpecontrol(void)
+target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
/* FIXME: Mask away return zero on read bits. */
return other->CP0_VPEControl;
}
-target_ulong helper_mftc0_vpeconf0(void)
+target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
return other->CP0_VPEConf0;
}
-void helper_mtc0_vpeconf0 (target_ulong arg1)
+void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
{
uint32_t mask = 0;
uint32_t newval;
@@ -1223,10 +1261,10 @@ void helper_mtc0_vpeconf0 (target_ulong arg1)
env->CP0_VPEConf0 = newval;
}
-void helper_mttc0_vpeconf0(target_ulong arg1)
+void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
uint32_t mask = 0;
uint32_t newval;
@@ -1237,7 +1275,7 @@ void helper_mttc0_vpeconf0(target_ulong arg1)
other->CP0_VPEConf0 = newval;
}
-void helper_mtc0_vpeconf1 (target_ulong arg1)
+void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
{
uint32_t mask = 0;
uint32_t newval;
@@ -1255,25 +1293,25 @@ void helper_mtc0_vpeconf1 (target_ulong arg1)
env->CP0_VPEConf1 = newval;
}
-void helper_mtc0_yqmask (target_ulong arg1)
+void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
{
/* Yield qualifier inputs not implemented. */
env->CP0_YQMask = 0x00000000;
}
-void helper_mtc0_vpeopt (target_ulong arg1)
+void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_VPEOpt = arg1 & 0x0000ffff;
}
-void helper_mtc0_entrylo0 (target_ulong arg1)
+void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
{
/* Large physaddr (PABITS) not implemented */
/* 1k pages not implemented */
env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
}
-void helper_mtc0_tcstatus (target_ulong arg1)
+void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
{
uint32_t mask = env->CP0_TCStatus_rw_bitmask;
uint32_t newval;
@@ -1284,10 +1322,10 @@ void helper_mtc0_tcstatus (target_ulong arg1)
sync_c0_tcstatus(env, env->current_tc, newval);
}
-void helper_mttc0_tcstatus (target_ulong arg1)
+void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCStatus = arg1;
@@ -1296,7 +1334,7 @@ void helper_mttc0_tcstatus (target_ulong arg1)
sync_c0_tcstatus(other, other_tc, arg1);
}
-void helper_mtc0_tcbind (target_ulong arg1)
+void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
{
uint32_t mask = (1 << CP0TCBd_TBE);
uint32_t newval;
@@ -1307,12 +1345,12 @@ void helper_mtc0_tcbind (target_ulong arg1)
env->active_tc.CP0_TCBind = newval;
}
-void helper_mttc0_tcbind (target_ulong arg1)
+void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
uint32_t mask = (1 << CP0TCBd_TBE);
uint32_t newval;
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
mask |= (1 << CP0TCBd_CurVPE);
@@ -1325,7 +1363,7 @@ void helper_mttc0_tcbind (target_ulong arg1)
}
}
-void helper_mtc0_tcrestart (target_ulong arg1)
+void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
{
env->active_tc.PC = arg1;
env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
@@ -1333,10 +1371,10 @@ void helper_mtc0_tcrestart (target_ulong arg1)
/* MIPS16 not implemented. */
}
-void helper_mttc0_tcrestart (target_ulong arg1)
+void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc) {
other->active_tc.PC = arg1;
@@ -1351,7 +1389,7 @@ void helper_mttc0_tcrestart (target_ulong arg1)
}
}
-void helper_mtc0_tchalt (target_ulong arg1)
+void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
{
env->active_tc.CP0_TCHalt = arg1 & 0x1;
@@ -1363,10 +1401,10 @@ void helper_mtc0_tchalt (target_ulong arg1)
}
}
-void helper_mttc0_tchalt (target_ulong arg1)
+void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
// TODO: Halt TC / Restart (if allocated+active) TC.
@@ -1382,15 +1420,15 @@ void helper_mttc0_tchalt (target_ulong arg1)
}
}
-void helper_mtc0_tccontext (target_ulong arg1)
+void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
{
env->active_tc.CP0_TCContext = arg1;
}
-void helper_mttc0_tccontext (target_ulong arg1)
+void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCContext = arg1;
@@ -1398,15 +1436,15 @@ void helper_mttc0_tccontext (target_ulong arg1)
other->tcs[other_tc].CP0_TCContext = arg1;
}
-void helper_mtc0_tcschedule (target_ulong arg1)
+void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
{
env->active_tc.CP0_TCSchedule = arg1;
}
-void helper_mttc0_tcschedule (target_ulong arg1)
+void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCSchedule = arg1;
@@ -1414,15 +1452,15 @@ void helper_mttc0_tcschedule (target_ulong arg1)
other->tcs[other_tc].CP0_TCSchedule = arg1;
}
-void helper_mtc0_tcschefback (target_ulong arg1)
+void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
{
env->active_tc.CP0_TCScheFBack = arg1;
}
-void helper_mttc0_tcschefback (target_ulong arg1)
+void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCScheFBack = arg1;
@@ -1430,25 +1468,25 @@ void helper_mttc0_tcschefback (target_ulong arg1)
other->tcs[other_tc].CP0_TCScheFBack = arg1;
}
-void helper_mtc0_entrylo1 (target_ulong arg1)
+void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
{
/* Large physaddr (PABITS) not implemented */
/* 1k pages not implemented */
env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
}
-void helper_mtc0_context (target_ulong arg1)
+void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
}
-void helper_mtc0_pagemask (target_ulong arg1)
+void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
{
/* 1k pages not implemented */
env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
}
-void helper_mtc0_pagegrain (target_ulong arg1)
+void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
{
/* SmartMIPS not implemented */
/* Large physaddr (PABITS) not implemented */
@@ -1456,47 +1494,47 @@ void helper_mtc0_pagegrain (target_ulong arg1)
env->CP0_PageGrain = 0;
}
-void helper_mtc0_wired (target_ulong arg1)
+void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_Wired = arg1 % env->tlb->nb_tlb;
}
-void helper_mtc0_srsconf0 (target_ulong arg1)
+void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
}
-void helper_mtc0_srsconf1 (target_ulong arg1)
+void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
}
-void helper_mtc0_srsconf2 (target_ulong arg1)
+void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
}
-void helper_mtc0_srsconf3 (target_ulong arg1)
+void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
}
-void helper_mtc0_srsconf4 (target_ulong arg1)
+void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
}
-void helper_mtc0_hwrena (target_ulong arg1)
+void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_HWREna = arg1 & 0x0000000F;
}
-void helper_mtc0_count (target_ulong arg1)
+void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
{
cpu_mips_store_count(env, arg1);
}
-void helper_mtc0_entryhi (target_ulong arg1)
+void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
{
target_ulong old, val;
@@ -1515,21 +1553,21 @@ void helper_mtc0_entryhi (target_ulong arg1)
cpu_mips_tlb_flush(env, 1);
}
-void helper_mttc0_entryhi(target_ulong arg1)
+void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
other->CP0_EntryHi = arg1;
sync_c0_entryhi(other, other_tc);
}
-void helper_mtc0_compare (target_ulong arg1)
+void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
{
cpu_mips_store_compare(env, arg1);
}
-void helper_mtc0_status (target_ulong arg1)
+void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
{
uint32_t val, old;
uint32_t mask = env->CP0_Status_rw_bitmask;
@@ -1538,7 +1576,7 @@ void helper_mtc0_status (target_ulong arg1)
old = env->CP0_Status;
env->CP0_Status = (env->CP0_Status & ~mask) | val;
if (env->CP0_Config3 & (1 << CP0C3_MT)) {
- sync_c0_status(env, env->current_tc);
+ sync_c0_status(env, env, env->current_tc);
} else {
compute_hflags(env);
}
@@ -1557,22 +1595,22 @@ void helper_mtc0_status (target_ulong arg1)
}
}
-void helper_mttc0_status(target_ulong arg1)
+void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
other->CP0_Status = arg1 & ~0xf1000018;
- sync_c0_status(other, other_tc);
+ sync_c0_status(env, other, other_tc);
}
-void helper_mtc0_intctl (target_ulong arg1)
+void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
{
/* vectored interrupts not implemented, no performance counters. */
env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
}
-void helper_mtc0_srsctl (target_ulong arg1)
+void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
{
uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
@@ -1606,52 +1644,52 @@ static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
}
}
-void helper_mtc0_cause(target_ulong arg1)
+void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
{
mtc0_cause(env, arg1);
}
-void helper_mttc0_cause(target_ulong arg1)
+void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
mtc0_cause(other, arg1);
}
-target_ulong helper_mftc0_epc(void)
+target_ulong helper_mftc0_epc(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
return other->CP0_EPC;
}
-target_ulong helper_mftc0_ebase(void)
+target_ulong helper_mftc0_ebase(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
return other->CP0_EBase;
}
-void helper_mtc0_ebase (target_ulong arg1)
+void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
{
/* vectored interrupts not implemented */
env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
}
-void helper_mttc0_ebase(target_ulong arg1)
+void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
}
-target_ulong helper_mftc0_configx(target_ulong idx)
+target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
switch (idx) {
case 0: return other->CP0_Config0;
@@ -1667,49 +1705,49 @@ target_ulong helper_mftc0_configx(target_ulong idx)
return 0;
}
-void helper_mtc0_config0 (target_ulong arg1)
+void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
}
-void helper_mtc0_config2 (target_ulong arg1)
+void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
{
/* tertiary/secondary caches not implemented */
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
}
-void helper_mtc0_lladdr (target_ulong arg1)
+void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
{
target_long mask = env->CP0_LLAddr_rw_bitmask;
arg1 = arg1 << env->CP0_LLAddr_shift;
env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
}
-void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
+void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
/* Watch exceptions for instructions, data loads, data stores
not implemented. */
env->CP0_WatchLo[sel] = (arg1 & ~0x7);
}
-void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
+void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
}
-void helper_mtc0_xcontext (target_ulong arg1)
+void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
{
target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
}
-void helper_mtc0_framemask (target_ulong arg1)
+void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_Framemask = arg1; /* XXX */
}
-void helper_mtc0_debug (target_ulong arg1)
+void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
if (arg1 & (1 << CP0DB_DM))
@@ -1718,11 +1756,11 @@ void helper_mtc0_debug (target_ulong arg1)
env->hflags &= ~MIPS_HFLAG_DM;
}
-void helper_mttc0_debug(target_ulong arg1)
+void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
/* XXX: Might be wrong, check with EJTAG spec. */
if (other_tc == other->current_tc)
@@ -1734,36 +1772,36 @@ void helper_mttc0_debug(target_ulong arg1)
(arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
}
-void helper_mtc0_performance0 (target_ulong arg1)
+void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_Performance0 = arg1 & 0x000007ff;
}
-void helper_mtc0_taglo (target_ulong arg1)
+void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_TagLo = arg1 & 0xFFFFFCF6;
}
-void helper_mtc0_datalo (target_ulong arg1)
+void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_DataLo = arg1; /* XXX */
}
-void helper_mtc0_taghi (target_ulong arg1)
+void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_TagHi = arg1; /* XXX */
}
-void helper_mtc0_datahi (target_ulong arg1)
+void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_DataHi = arg1; /* XXX */
}
/* MIPS MT functions */
-target_ulong helper_mftgpr(uint32_t sel)
+target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.gpr[sel];
@@ -1771,10 +1809,10 @@ target_ulong helper_mftgpr(uint32_t sel)
return other->tcs[other_tc].gpr[sel];
}
-target_ulong helper_mftlo(uint32_t sel)
+target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.LO[sel];
@@ -1782,10 +1820,10 @@ target_ulong helper_mftlo(uint32_t sel)
return other->tcs[other_tc].LO[sel];
}
-target_ulong helper_mfthi(uint32_t sel)
+target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.HI[sel];
@@ -1793,10 +1831,10 @@ target_ulong helper_mfthi(uint32_t sel)
return other->tcs[other_tc].HI[sel];
}
-target_ulong helper_mftacx(uint32_t sel)
+target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.ACX[sel];
@@ -1804,10 +1842,10 @@ target_ulong helper_mftacx(uint32_t sel)
return other->tcs[other_tc].ACX[sel];
}
-target_ulong helper_mftdsp(void)
+target_ulong helper_mftdsp(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
return other->active_tc.DSPControl;
@@ -1815,10 +1853,10 @@ target_ulong helper_mftdsp(void)
return other->tcs[other_tc].DSPControl;
}
-void helper_mttgpr(target_ulong arg1, uint32_t sel)
+void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
other->active_tc.gpr[sel] = arg1;
@@ -1826,10 +1864,10 @@ void helper_mttgpr(target_ulong arg1, uint32_t sel)
other->tcs[other_tc].gpr[sel] = arg1;
}
-void helper_mttlo(target_ulong arg1, uint32_t sel)
+void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
other->active_tc.LO[sel] = arg1;
@@ -1837,10 +1875,10 @@ void helper_mttlo(target_ulong arg1, uint32_t sel)
other->tcs[other_tc].LO[sel] = arg1;
}
-void helper_mtthi(target_ulong arg1, uint32_t sel)
+void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
other->active_tc.HI[sel] = arg1;
@@ -1848,10 +1886,10 @@ void helper_mtthi(target_ulong arg1, uint32_t sel)
other->tcs[other_tc].HI[sel] = arg1;
}
-void helper_mttacx(target_ulong arg1, uint32_t sel)
+void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
other->active_tc.ACX[sel] = arg1;
@@ -1859,10 +1897,10 @@ void helper_mttacx(target_ulong arg1, uint32_t sel)
other->tcs[other_tc].ACX[sel] = arg1;
}
-void helper_mttdsp(target_ulong arg1)
+void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
if (other_tc == other->current_tc)
other->active_tc.DSPControl = arg1;
@@ -1883,7 +1921,7 @@ target_ulong helper_emt(void)
return 0;
}
-target_ulong helper_dvpe(void)
+target_ulong helper_dvpe(CPUMIPSState *env)
{
CPUMIPSState *other_cpu = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
@@ -1899,7 +1937,7 @@ target_ulong helper_dvpe(void)
return prev;
}
-target_ulong helper_evpe(void)
+target_ulong helper_evpe(CPUMIPSState *env)
{
CPUMIPSState *other_cpu = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
@@ -1925,7 +1963,7 @@ void helper_fork(target_ulong arg1, target_ulong arg2)
// TODO: store to TC register
}
-target_ulong helper_yield(target_ulong arg)
+target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
{
target_long arg1 = arg;
@@ -1936,13 +1974,13 @@ target_ulong helper_yield(target_ulong arg)
env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
- helper_raise_exception(EXCP_THREAD);
+ helper_raise_exception(env, EXCP_THREAD);
}
}
} else if (arg1 == 0) {
if (0 /* TODO: TC underflow */) {
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
- helper_raise_exception(EXCP_THREAD);
+ helper_raise_exception(env, EXCP_THREAD);
} else {
// TODO: Deallocate TC
}
@@ -1950,7 +1988,7 @@ target_ulong helper_yield(target_ulong arg)
/* Yield qualifier inputs not implemented. */
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
- helper_raise_exception(EXCP_THREAD);
+ helper_raise_exception(env, EXCP_THREAD);
}
return env->CP0_YQMask;
}
@@ -1972,7 +2010,7 @@ static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
}
}
-static void r4k_fill_tlb (int idx)
+static void r4k_fill_tlb(CPUMIPSState *env, int idx)
{
r4k_tlb_t *tlb;
@@ -1995,7 +2033,7 @@ static void r4k_fill_tlb (int idx)
tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
}
-void r4k_helper_tlbwi (void)
+void r4k_helper_tlbwi(CPUMIPSState *env)
{
int idx;
@@ -2007,18 +2045,18 @@ void r4k_helper_tlbwi (void)
r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
r4k_invalidate_tlb(env, idx, 0);
- r4k_fill_tlb(idx);
+ r4k_fill_tlb(env, idx);
}
-void r4k_helper_tlbwr (void)
+void r4k_helper_tlbwr(CPUMIPSState *env)
{
int r = cpu_mips_get_random(env);
r4k_invalidate_tlb(env, r, 1);
- r4k_fill_tlb(r);
+ r4k_fill_tlb(env, r);
}
-void r4k_helper_tlbp (void)
+void r4k_helper_tlbp(CPUMIPSState *env)
{
r4k_tlb_t *tlb;
target_ulong mask;
@@ -2060,7 +2098,7 @@ void r4k_helper_tlbp (void)
}
}
-void r4k_helper_tlbr (void)
+void r4k_helper_tlbr(CPUMIPSState *env)
{
r4k_tlb_t *tlb;
uint8_t ASID;
@@ -2084,28 +2122,28 @@ void r4k_helper_tlbr (void)
(tlb->C1 << 3) | (tlb->PFN[1] >> 6);
}
-void helper_tlbwi(void)
+void helper_tlbwi(CPUMIPSState *env)
{
- env->tlb->helper_tlbwi();
+ env->tlb->helper_tlbwi(env);
}
-void helper_tlbwr(void)
+void helper_tlbwr(CPUMIPSState *env)
{
- env->tlb->helper_tlbwr();
+ env->tlb->helper_tlbwr(env);
}
-void helper_tlbp(void)
+void helper_tlbp(CPUMIPSState *env)
{
- env->tlb->helper_tlbp();
+ env->tlb->helper_tlbp(env);
}
-void helper_tlbr(void)
+void helper_tlbr(CPUMIPSState *env)
{
- env->tlb->helper_tlbr();
+ env->tlb->helper_tlbr(env);
}
/* Specials */
-target_ulong helper_di (void)
+target_ulong helper_di(CPUMIPSState *env)
{
target_ulong t0 = env->CP0_Status;
@@ -2113,7 +2151,7 @@ target_ulong helper_di (void)
return t0;
}
-target_ulong helper_ei (void)
+target_ulong helper_ei(CPUMIPSState *env)
{
target_ulong t0 = env->CP0_Status;
@@ -2121,7 +2159,7 @@ target_ulong helper_ei (void)
return t0;
}
-static void debug_pre_eret (void)
+static void debug_pre_eret(CPUMIPSState *env)
{
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
@@ -2134,7 +2172,7 @@ static void debug_pre_eret (void)
}
}
-static void debug_post_eret (void)
+static void debug_post_eret(CPUMIPSState *env)
{
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
@@ -2152,7 +2190,7 @@ static void debug_post_eret (void)
}
}
-static void set_pc (target_ulong error_pc)
+static void set_pc(CPUMIPSState *env, target_ulong error_pc)
{
env->active_tc.PC = error_pc & ~(target_ulong)1;
if (error_pc & 1) {
@@ -2162,78 +2200,78 @@ static void set_pc (target_ulong error_pc)
}
}
-void helper_eret (void)
+void helper_eret(CPUMIPSState *env)
{
- debug_pre_eret();
+ debug_pre_eret(env);
if (env->CP0_Status & (1 << CP0St_ERL)) {
- set_pc(env->CP0_ErrorEPC);
+ set_pc(env, env->CP0_ErrorEPC);
env->CP0_Status &= ~(1 << CP0St_ERL);
} else {
- set_pc(env->CP0_EPC);
+ set_pc(env, env->CP0_EPC);
env->CP0_Status &= ~(1 << CP0St_EXL);
}
compute_hflags(env);
- debug_post_eret();
+ debug_post_eret(env);
env->lladdr = 1;
}
-void helper_deret (void)
+void helper_deret(CPUMIPSState *env)
{
- debug_pre_eret();
- set_pc(env->CP0_DEPC);
+ debug_pre_eret(env);
+ set_pc(env, env->CP0_DEPC);
env->hflags &= MIPS_HFLAG_DM;
compute_hflags(env);
- debug_post_eret();
+ debug_post_eret(env);
env->lladdr = 1;
}
#endif /* !CONFIG_USER_ONLY */
-target_ulong helper_rdhwr_cpunum(void)
+target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
{
if ((env->hflags & MIPS_HFLAG_CP0) ||
(env->CP0_HWREna & (1 << 0)))
return env->CP0_EBase & 0x3ff;
else
- helper_raise_exception(EXCP_RI);
+ helper_raise_exception(env, EXCP_RI);
return 0;
}
-target_ulong helper_rdhwr_synci_step(void)
+target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
{
if ((env->hflags & MIPS_HFLAG_CP0) ||
(env->CP0_HWREna & (1 << 1)))
return env->SYNCI_Step;
else
- helper_raise_exception(EXCP_RI);
+ helper_raise_exception(env, EXCP_RI);
return 0;
}
-target_ulong helper_rdhwr_cc(void)
+target_ulong helper_rdhwr_cc(CPUMIPSState *env)
{
if ((env->hflags & MIPS_HFLAG_CP0) ||
(env->CP0_HWREna & (1 << 2)))
return env->CP0_Count;
else
- helper_raise_exception(EXCP_RI);
+ helper_raise_exception(env, EXCP_RI);
return 0;
}
-target_ulong helper_rdhwr_ccres(void)
+target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
{
if ((env->hflags & MIPS_HFLAG_CP0) ||
(env->CP0_HWREna & (1 << 3)))
return env->CCRes;
else
- helper_raise_exception(EXCP_RI);
+ helper_raise_exception(env, EXCP_RI);
return 0;
}
-void helper_pmon (int function)
+void helper_pmon(CPUMIPSState *env, int function)
{
function /= 2;
switch (function) {
@@ -2259,16 +2297,17 @@ void helper_pmon (int function)
}
}
-void helper_wait (void)
+void helper_wait(CPUMIPSState *env)
{
env->halted = 1;
cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE);
- helper_raise_exception(EXCP_HLT);
+ helper_raise_exception(env, EXCP_HLT);
}
#if !defined(CONFIG_USER_ONLY)
-static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write,
+static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
+ target_ulong addr, int is_write,
int is_user, uintptr_t retaddr);
#define MMUSUFFIX _mmu
@@ -2286,23 +2325,20 @@ static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write,
#define SHIFT 3
#include "softmmu_template.h"
-static void do_unaligned_access(target_ulong addr, int is_write,
- int is_user, uintptr_t retaddr)
+static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
+ int is_write, int is_user, uintptr_t retaddr)
{
env->CP0_BadVAddr = addr;
- do_restore_state (retaddr);
- helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
+ do_restore_state(env, retaddr);
+ helper_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL);
}
-void tlb_fill(CPUMIPSState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
TranslationBlock *tb;
- CPUMIPSState *saved_env;
int ret;
- saved_env = env;
- env = env1;
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (ret) {
if (retaddr) {
@@ -2314,20 +2350,17 @@ void tlb_fill(CPUMIPSState *env1, target_ulong addr, int is_write, int mmu_idx,
cpu_restore_state(tb, env, retaddr);
}
}
- helper_raise_exception_err(env->exception_index, env->error_code);
+ helper_raise_exception_err(env, env->exception_index, env->error_code);
}
- env = saved_env;
}
-void cpu_unassigned_access(CPUMIPSState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr,
int is_write, int is_exec, int unused, int size)
{
- env = env1;
-
if (is_exec)
- helper_raise_exception(EXCP_IBE);
+ helper_raise_exception(env, EXCP_IBE);
else
- helper_raise_exception(EXCP_DBE);
+ helper_raise_exception(env, EXCP_DBE);
}
#endif /* !CONFIG_USER_ONLY */
@@ -2356,7 +2389,7 @@ static unsigned int ieee_rm[] = {
#define RESTORE_FLUSH_MODE \
set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
-target_ulong helper_cfc1 (uint32_t reg)
+target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
{
target_ulong arg1;
@@ -2381,7 +2414,7 @@ target_ulong helper_cfc1 (uint32_t reg)
return arg1;
}
-void helper_ctc1 (target_ulong arg1, uint32_t reg)
+void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
{
switch(reg) {
case 25:
@@ -2415,7 +2448,7 @@ void helper_ctc1 (target_ulong arg1, uint32_t reg)
RESTORE_FLUSH_MODE;
set_float_exception_flags(0, &env->active_fpu.fp_status);
if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
- helper_raise_exception(EXCP_FPE);
+ helper_raise_exception(env, EXCP_FPE);
}
static inline int ieee_ex_to_mips(int xcpt)
@@ -2441,13 +2474,13 @@ static inline int ieee_ex_to_mips(int xcpt)
return ret;
}
-static inline void update_fcr31(void)
+static inline void update_fcr31(CPUMIPSState *env)
{
int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
- helper_raise_exception(EXCP_FPE);
+ helper_raise_exception(env, EXCP_FPE);
else
UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
}
@@ -2458,71 +2491,71 @@ static inline void update_fcr31(void)
paired single lower "pl", paired single upper "pu". */
/* unary operations, modifying fp status */
-uint64_t helper_float_sqrt_d(uint64_t fdt0)
+uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
{
return float64_sqrt(fdt0, &env->active_fpu.fp_status);
}
-uint32_t helper_float_sqrt_s(uint32_t fst0)
+uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
{
return float32_sqrt(fst0, &env->active_fpu.fp_status);
}
-uint64_t helper_float_cvtd_s(uint32_t fst0)
+uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t fdt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fdt2;
}
-uint64_t helper_float_cvtd_w(uint32_t wt0)
+uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
{
uint64_t fdt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fdt2;
}
-uint64_t helper_float_cvtd_l(uint64_t dt0)
+uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
{
uint64_t fdt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fdt2;
}
-uint64_t helper_float_cvtl_d(uint64_t fdt0)
+uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
dt2 = FLOAT_SNAN64;
return dt2;
}
-uint64_t helper_float_cvtl_s(uint32_t fst0)
+uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
dt2 = FLOAT_SNAN64;
return dt2;
}
-uint64_t helper_float_cvtps_pw(uint64_t dt0)
+uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
{
uint32_t fst2;
uint32_t fsth2;
@@ -2530,11 +2563,11 @@ uint64_t helper_float_cvtps_pw(uint64_t dt0)
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return ((uint64_t)fsth2 << 32) | fst2;
}
-uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
+uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
uint32_t wth2;
@@ -2542,7 +2575,7 @@ uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
set_float_exception_flags(0, &env->active_fpu.fp_status);
wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
wt2 = FLOAT_SNAN32;
wth2 = FLOAT_SNAN32;
@@ -2550,81 +2583,81 @@ uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
return ((uint64_t)wth2 << 32) | wt2;
}
-uint32_t helper_float_cvts_d(uint64_t fdt0)
+uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t fst2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fst2;
}
-uint32_t helper_float_cvts_w(uint32_t wt0)
+uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
{
uint32_t fst2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fst2;
}
-uint32_t helper_float_cvts_l(uint64_t dt0)
+uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
{
uint32_t fst2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fst2;
}
-uint32_t helper_float_cvts_pl(uint32_t wt0)
+uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
{
uint32_t wt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
wt2 = wt0;
- update_fcr31();
+ update_fcr31(env);
return wt2;
}
-uint32_t helper_float_cvts_pu(uint32_t wth0)
+uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
{
uint32_t wt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
wt2 = wth0;
- update_fcr31();
+ update_fcr31(env);
return wt2;
}
-uint32_t helper_float_cvtw_s(uint32_t fst0)
+uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
wt2 = FLOAT_SNAN32;
return wt2;
}
-uint32_t helper_float_cvtw_d(uint64_t fdt0)
+uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
wt2 = FLOAT_SNAN32;
return wt2;
}
-uint64_t helper_float_roundl_d(uint64_t fdt0)
+uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
@@ -2632,13 +2665,13 @@ uint64_t helper_float_roundl_d(uint64_t fdt0)
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
dt2 = FLOAT_SNAN64;
return dt2;
}
-uint64_t helper_float_roundl_s(uint32_t fst0)
+uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
@@ -2646,13 +2679,13 @@ uint64_t helper_float_roundl_s(uint32_t fst0)
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
dt2 = FLOAT_SNAN64;
return dt2;
}
-uint32_t helper_float_roundw_d(uint64_t fdt0)
+uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
@@ -2660,13 +2693,13 @@ uint32_t helper_float_roundw_d(uint64_t fdt0)
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
wt2 = FLOAT_SNAN32;
return wt2;
}
-uint32_t helper_float_roundw_s(uint32_t fst0)
+uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
@@ -2674,61 +2707,61 @@ uint32_t helper_float_roundw_s(uint32_t fst0)
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
wt2 = FLOAT_SNAN32;
return wt2;
}
-uint64_t helper_float_truncl_d(uint64_t fdt0)
+uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
dt2 = FLOAT_SNAN64;
return dt2;
}
-uint64_t helper_float_truncl_s(uint32_t fst0)
+uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
dt2 = FLOAT_SNAN64;
return dt2;
}
-uint32_t helper_float_truncw_d(uint64_t fdt0)
+uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
wt2 = FLOAT_SNAN32;
return wt2;
}
-uint32_t helper_float_truncw_s(uint32_t fst0)
+uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
wt2 = FLOAT_SNAN32;
return wt2;
}
-uint64_t helper_float_ceill_d(uint64_t fdt0)
+uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
@@ -2736,13 +2769,13 @@ uint64_t helper_float_ceill_d(uint64_t fdt0)
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
dt2 = FLOAT_SNAN64;
return dt2;
}
-uint64_t helper_float_ceill_s(uint32_t fst0)
+uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
@@ -2750,13 +2783,13 @@ uint64_t helper_float_ceill_s(uint32_t fst0)
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
dt2 = FLOAT_SNAN64;
return dt2;
}
-uint32_t helper_float_ceilw_d(uint64_t fdt0)
+uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
@@ -2764,13 +2797,13 @@ uint32_t helper_float_ceilw_d(uint64_t fdt0)
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
wt2 = FLOAT_SNAN32;
return wt2;
}
-uint32_t helper_float_ceilw_s(uint32_t fst0)
+uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
@@ -2778,13 +2811,13 @@ uint32_t helper_float_ceilw_s(uint32_t fst0)
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
wt2 = FLOAT_SNAN32;
return wt2;
}
-uint64_t helper_float_floorl_d(uint64_t fdt0)
+uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
@@ -2792,13 +2825,13 @@ uint64_t helper_float_floorl_d(uint64_t fdt0)
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
dt2 = FLOAT_SNAN64;
return dt2;
}
-uint64_t helper_float_floorl_s(uint32_t fst0)
+uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
@@ -2806,13 +2839,13 @@ uint64_t helper_float_floorl_s(uint32_t fst0)
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
dt2 = FLOAT_SNAN64;
return dt2;
}
-uint32_t helper_float_floorw_d(uint64_t fdt0)
+uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
@@ -2820,13 +2853,13 @@ uint32_t helper_float_floorw_d(uint64_t fdt0)
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
wt2 = FLOAT_SNAN32;
return wt2;
}
-uint32_t helper_float_floorw_s(uint32_t fst0)
+uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
@@ -2834,7 +2867,7 @@ uint32_t helper_float_floorw_s(uint32_t fst0)
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31();
+ update_fcr31(env);
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
wt2 = FLOAT_SNAN32;
return wt2;
@@ -2864,69 +2897,69 @@ FLOAT_UNOP(chs)
#undef FLOAT_UNOP
/* MIPS specific unary operations */
-uint64_t helper_float_recip_d(uint64_t fdt0)
+uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t fdt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fdt2;
}
-uint32_t helper_float_recip_s(uint32_t fst0)
+uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t fst2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fst2;
}
-uint64_t helper_float_rsqrt_d(uint64_t fdt0)
+uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t fdt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fdt2;
}
-uint32_t helper_float_rsqrt_s(uint32_t fst0)
+uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t fst2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fst2;
}
-uint64_t helper_float_recip1_d(uint64_t fdt0)
+uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t fdt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fdt2;
}
-uint32_t helper_float_recip1_s(uint32_t fst0)
+uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t fst2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fst2;
}
-uint64_t helper_float_recip1_ps(uint64_t fdt0)
+uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t fst2;
uint32_t fsth2;
@@ -2934,33 +2967,33 @@ uint64_t helper_float_recip1_ps(uint64_t fdt0)
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return ((uint64_t)fsth2 << 32) | fst2;
}
-uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
+uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t fdt2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fdt2;
}
-uint32_t helper_float_rsqrt1_s(uint32_t fst0)
+uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t fst2;
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return fst2;
}
-uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
+uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t fst2;
uint32_t fsth2;
@@ -2970,39 +3003,43 @@ uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return ((uint64_t)fsth2 << 32) | fst2;
}
-#define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
+#define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
/* binary operations */
#define FLOAT_BINOP(name) \
-uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
+uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
+ uint64_t fdt0, uint64_t fdt1) \
{ \
uint64_t dt2; \
\
set_float_exception_flags(0, &env->active_fpu.fp_status); \
dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
- update_fcr31(); \
+ update_fcr31(env); \
if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
dt2 = FLOAT_QNAN64; \
return dt2; \
} \
\
-uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
+uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
+ uint32_t fst0, uint32_t fst1) \
{ \
uint32_t wt2; \
\
set_float_exception_flags(0, &env->active_fpu.fp_status); \
wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
- update_fcr31(); \
+ update_fcr31(env); \
if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
wt2 = FLOAT_QNAN32; \
return wt2; \
} \
\
-uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
+uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
+ uint64_t fdt0, \
+ uint64_t fdt1) \
{ \
uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
uint32_t fsth0 = fdt0 >> 32; \
@@ -3014,7 +3051,7 @@ uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
set_float_exception_flags(0, &env->active_fpu.fp_status); \
wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
- update_fcr31(); \
+ update_fcr31(env); \
if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
wt2 = FLOAT_QNAN32; \
wth2 = FLOAT_QNAN32; \
@@ -3030,22 +3067,28 @@ FLOAT_BINOP(div)
/* ternary operations */
#define FLOAT_TERNOP(name1, name2) \
-uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
- uint64_t fdt2) \
+uint64_t helper_float_ ## name1 ## name2 ## _d(CPUMIPSState *env, \
+ uint64_t fdt0, \
+ uint64_t fdt1, \
+ uint64_t fdt2) \
{ \
fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
} \
\
-uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
- uint32_t fst2) \
+uint32_t helper_float_ ## name1 ## name2 ## _s(CPUMIPSState *env, \
+ uint32_t fst0, \
+ uint32_t fst1, \
+ uint32_t fst2) \
{ \
fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
} \
\
-uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
- uint64_t fdt2) \
+uint64_t helper_float_ ## name1 ## name2 ## _ps(CPUMIPSState *env, \
+ uint64_t fdt0, \
+ uint64_t fdt1, \
+ uint64_t fdt2) \
{ \
uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
uint32_t fsth0 = fdt0 >> 32; \
@@ -3067,24 +3110,30 @@ FLOAT_TERNOP(mul, sub)
/* negated ternary operations */
#define FLOAT_NTERNOP(name1, name2) \
-uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
- uint64_t fdt2) \
+uint64_t helper_float_n ## name1 ## name2 ## _d(CPUMIPSState *env, \
+ uint64_t fdt0, \
+ uint64_t fdt1, \
+ uint64_t fdt2) \
{ \
fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
return float64_chs(fdt2); \
} \
\
-uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
- uint32_t fst2) \
+uint32_t helper_float_n ## name1 ## name2 ## _s(CPUMIPSState *env, \
+ uint32_t fst0, \
+ uint32_t fst1, \
+ uint32_t fst2) \
{ \
fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
return float32_chs(fst2); \
} \
\
-uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
- uint64_t fdt2) \
+uint64_t helper_float_n ## name1 ## name2 ## _ps(CPUMIPSState *env, \
+ uint64_t fdt0, \
+ uint64_t fdt1, \
+ uint64_t fdt2) \
{ \
uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
uint32_t fsth0 = fdt0 >> 32; \
@@ -3107,25 +3156,25 @@ FLOAT_NTERNOP(mul, sub)
#undef FLOAT_NTERNOP
/* MIPS specific binary operations */
-uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
+uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
set_float_exception_flags(0, &env->active_fpu.fp_status);
fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
- update_fcr31();
+ update_fcr31(env);
return fdt2;
}
-uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
+uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
{
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
- update_fcr31();
+ update_fcr31(env);
return fst2;
}
-uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
+uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
@@ -3137,31 +3186,31 @@ uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
- update_fcr31();
+ update_fcr31(env);
return ((uint64_t)fsth2 << 32) | fst2;
}
-uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
+uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
set_float_exception_flags(0, &env->active_fpu.fp_status);
fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
- update_fcr31();
+ update_fcr31(env);
return fdt2;
}
-uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
+uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
{
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
- update_fcr31();
+ update_fcr31(env);
return fst2;
}
-uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
+uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
@@ -3175,11 +3224,11 @@ uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
- update_fcr31();
+ update_fcr31(env);
return ((uint64_t)fsth2 << 32) | fst2;
}
-uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
+uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
{
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
@@ -3191,11 +3240,11 @@ uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return ((uint64_t)fsth2 << 32) | fst2;
}
-uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
+uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
{
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
@@ -3207,31 +3256,33 @@ uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
set_float_exception_flags(0, &env->active_fpu.fp_status);
fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
- update_fcr31();
+ update_fcr31(env);
return ((uint64_t)fsth2 << 32) | fst2;
}
/* compare operations */
#define FOP_COND_D(op, cond) \
-void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
+void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
+ uint64_t fdt1, int cc) \
{ \
int c; \
set_float_exception_flags(0, &env->active_fpu.fp_status); \
c = cond; \
- update_fcr31(); \
+ update_fcr31(env); \
if (c) \
SET_FP_COND(cc, env->active_fpu); \
else \
CLEAR_FP_COND(cc, env->active_fpu); \
} \
-void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
+void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
+ uint64_t fdt1, int cc) \
{ \
int c; \
set_float_exception_flags(0, &env->active_fpu.fp_status); \
fdt0 = float64_abs(fdt0); \
fdt1 = float64_abs(fdt1); \
c = cond; \
- update_fcr31(); \
+ update_fcr31(env); \
if (c) \
SET_FP_COND(cc, env->active_fpu); \
else \
@@ -3260,25 +3311,27 @@ FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
#define FOP_COND_S(op, cond) \
-void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
+void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
+ uint32_t fst1, int cc) \
{ \
int c; \
set_float_exception_flags(0, &env->active_fpu.fp_status); \
c = cond; \
- update_fcr31(); \
+ update_fcr31(env); \
if (c) \
SET_FP_COND(cc, env->active_fpu); \
else \
CLEAR_FP_COND(cc, env->active_fpu); \
} \
-void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
+void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
+ uint32_t fst1, int cc) \
{ \
int c; \
set_float_exception_flags(0, &env->active_fpu.fp_status); \
fst0 = float32_abs(fst0); \
fst1 = float32_abs(fst1); \
c = cond; \
- update_fcr31(); \
+ update_fcr31(env); \
if (c) \
SET_FP_COND(cc, env->active_fpu); \
else \
@@ -3307,7 +3360,8 @@ FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
#define FOP_COND_PS(op, condl, condh) \
-void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
+void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
+ uint64_t fdt1, int cc) \
{ \
uint32_t fst0, fsth0, fst1, fsth1; \
int ch, cl; \
@@ -3318,7 +3372,7 @@ void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
fsth1 = fdt1 >> 32; \
cl = condl; \
ch = condh; \
- update_fcr31(); \
+ update_fcr31(env); \
if (cl) \
SET_FP_COND(cc, env->active_fpu); \
else \
@@ -3328,7 +3382,8 @@ void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
else \
CLEAR_FP_COND(cc + 1, env->active_fpu); \
} \
-void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
+void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
+ uint64_t fdt1, int cc) \
{ \
uint32_t fst0, fsth0, fst1, fsth1; \
int ch, cl; \
@@ -3338,7 +3393,7 @@ void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
fsth1 = float32_abs(fdt1 >> 32); \
cl = condl; \
ch = condh; \
- update_fcr31(); \
+ update_fcr31(env); \
if (cl) \
SET_FP_COND(cc, env->active_fpu); \
else \
diff --git a/target-mips/translate.c b/target-mips/translate.c
index b293419..7ab769f 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -483,27 +483,45 @@ static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
#include "gen-icount.h"
-#define gen_helper_0i(name, arg) do { \
+#define gen_helper_0e0i(name, arg) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg); \
- gen_helper_##name(helper_tmp); \
+ gen_helper_##name(cpu_env, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \
} while(0)
-#define gen_helper_1i(name, arg1, arg2) do { \
+#define gen_helper_0e1i(name, arg1, arg2) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
- gen_helper_##name(arg1, helper_tmp); \
+ gen_helper_##name(cpu_env, arg1, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \
} while(0)
-#define gen_helper_2i(name, arg1, arg2, arg3) do { \
+#define gen_helper_1e0i(name, ret, arg1) do { \
+ TCGv_i32 helper_tmp = tcg_const_i32(arg1); \
+ gen_helper_##name(ret, cpu_env, helper_tmp); \
+ tcg_temp_free_i32(helper_tmp); \
+ } while(0)
+
+#define gen_helper_1e1i(name, ret, arg1, arg2) do { \
+ TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
+ gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \
+ tcg_temp_free_i32(helper_tmp); \
+ } while(0)
+
+#define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
+ TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
+ gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \
+ tcg_temp_free_i32(helper_tmp); \
+ } while(0)
+
+#define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
- gen_helper_##name(arg1, arg2, helper_tmp); \
+ gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \
} while(0)
-#define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
+#define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
- gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
+ gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \
} while(0)
@@ -748,7 +766,7 @@ generate_exception_err (DisasContext *ctx, int excp, int err)
TCGv_i32 texcp = tcg_const_i32(excp);
TCGv_i32 terr = tcg_const_i32(err);
save_cpu_state(ctx, 1);
- gen_helper_raise_exception_err(texcp, terr);
+ gen_helper_raise_exception_err(cpu_env, texcp, terr);
tcg_temp_free_i32(terr);
tcg_temp_free_i32(texcp);
}
@@ -757,7 +775,7 @@ static inline void
generate_exception (DisasContext *ctx, int excp)
{
save_cpu_state(ctx, 1);
- gen_helper_0i(raise_exception, excp);
+ gen_helper_0e0i(raise_exception, excp);
}
/* Addresses computation */
@@ -871,22 +889,22 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
gen_ldcmp_fpr##bits (ctx, fp0, fs); \
gen_ldcmp_fpr##bits (ctx, fp1, ft); \
switch (n) { \
- case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\
- case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\
- case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\
- case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\
- case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\
- case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\
- case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\
- case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\
- case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\
- case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
- case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\
- case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\
- case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\
- case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\
- case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\
- case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\
+ case 0: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\
+ case 1: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\
+ case 2: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\
+ case 3: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\
+ case 4: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\
+ case 5: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\
+ case 6: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\
+ case 7: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\
+ case 8: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\
+ case 9: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
+ case 10: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\
+ case 11: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\
+ case 12: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\
+ case 13: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\
+ case 14: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\
+ case 15: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\
default: abort(); \
} \
tcg_temp_free_i##bits (fp0); \
@@ -948,7 +966,7 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
#define OP_LD_ATOMIC(insn,fname) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
{ \
- gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \
+ gen_helper_1e1i(insn, ret, arg1, ctx->mem_idx); \
}
#endif
OP_LD_ATOMIC(ll,ld32s);
@@ -975,7 +993,7 @@ static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx)
tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); \
tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUMIPSState, llnewval)); \
- gen_helper_0i(raise_exception, EXCP_SC); \
+ gen_helper_0e0i(raise_exception, EXCP_SC); \
gen_set_label(l2); \
tcg_gen_movi_tl(t0, 0); \
gen_store_gpr(t0, rt); \
@@ -986,7 +1004,7 @@ static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx)
static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
{ \
TCGv t0 = tcg_temp_new(); \
- gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \
+ gen_helper_1e2i(insn, t0, arg1, arg2, ctx->mem_idx); \
gen_store_gpr(t0, rt); \
tcg_temp_free(t0); \
}
@@ -1066,14 +1084,14 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
case OPC_LDL:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx);
+ gen_helper_1e2i(ldl, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "ldl";
break;
case OPC_LDR:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx);
+ gen_helper_1e2i(ldr, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "ldr";
break;
@@ -1127,14 +1145,14 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
case OPC_LWL:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx);
+ gen_helper_1e2i(lwl, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "lwl";
break;
case OPC_LWR:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx);
+ gen_helper_1e2i(lwr, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "lwr";
break;
@@ -1170,12 +1188,12 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
break;
case OPC_SDL:
save_cpu_state(ctx, 1);
- gen_helper_2i(sdl, t1, t0, ctx->mem_idx);
+ gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx);
opn = "sdl";
break;
case OPC_SDR:
save_cpu_state(ctx, 1);
- gen_helper_2i(sdr, t1, t0, ctx->mem_idx);
+ gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx);
opn = "sdr";
break;
#endif
@@ -1196,12 +1214,12 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
break;
case OPC_SWL:
save_cpu_state(ctx, 1);
- gen_helper_2i(swl, t1, t0, ctx->mem_idx);
+ gen_helper_0e2i(swl, t1, t0, ctx->mem_idx);
opn = "swl";
break;
case OPC_SWR:
save_cpu_state(ctx, 1);
- gen_helper_2i(swr, t1, t0, ctx->mem_idx);
+ gen_helper_0e2i(swr, t1, t0, ctx->mem_idx);
opn = "swr";
break;
}
@@ -2138,11 +2156,11 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
opn = "ddivu";
break;
case OPC_DMULT:
- gen_helper_dmult(t0, t1);
+ gen_helper_dmult(cpu_env, t0, t1);
opn = "dmult";
break;
case OPC_DMULTU:
- gen_helper_dmultu(t0, t1);
+ gen_helper_dmultu(cpu_env, t0, t1);
opn = "dmultu";
break;
#endif
@@ -2254,59 +2272,59 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
switch (opc) {
case OPC_VR54XX_MULS:
- gen_helper_muls(t0, t0, t1);
+ gen_helper_muls(t0, cpu_env, t0, t1);
opn = "muls";
break;
case OPC_VR54XX_MULSU:
- gen_helper_mulsu(t0, t0, t1);
+ gen_helper_mulsu(t0, cpu_env, t0, t1);
opn = "mulsu";
break;
case OPC_VR54XX_MACC:
- gen_helper_macc(t0, t0, t1);
+ gen_helper_macc(t0, cpu_env, t0, t1);
opn = "macc";
break;
case OPC_VR54XX_MACCU:
- gen_helper_maccu(t0, t0, t1);
+ gen_helper_maccu(t0, cpu_env, t0, t1);
opn = "maccu";
break;
case OPC_VR54XX_MSAC:
- gen_helper_msac(t0, t0, t1);
+ gen_helper_msac(t0, cpu_env, t0, t1);
opn = "msac";
break;
case OPC_VR54XX_MSACU:
- gen_helper_msacu(t0, t0, t1);
+ gen_helper_msacu(t0, cpu_env, t0, t1);
opn = "msacu";
break;
case OPC_VR54XX_MULHI:
- gen_helper_mulhi(t0, t0, t1);
+ gen_helper_mulhi(t0, cpu_env, t0, t1);
opn = "mulhi";
break;
case OPC_VR54XX_MULHIU:
- gen_helper_mulhiu(t0, t0, t1);
+ gen_helper_mulhiu(t0, cpu_env, t0, t1);
opn = "mulhiu";
break;
case OPC_VR54XX_MULSHI:
- gen_helper_mulshi(t0, t0, t1);
+ gen_helper_mulshi(t0, cpu_env, t0, t1);
opn = "mulshi";
break;
case OPC_VR54XX_MULSHIU:
- gen_helper_mulshiu(t0, t0, t1);
+ gen_helper_mulshiu(t0, cpu_env, t0, t1);
opn = "mulshiu";
break;
case OPC_VR54XX_MACCHI:
- gen_helper_macchi(t0, t0, t1);
+ gen_helper_macchi(t0, cpu_env, t0, t1);
opn = "macchi";
break;
case OPC_VR54XX_MACCHIU:
- gen_helper_macchiu(t0, t0, t1);
+ gen_helper_macchiu(t0, cpu_env, t0, t1);
opn = "macchiu";
break;
case OPC_VR54XX_MSACHI:
- gen_helper_msachi(t0, t0, t1);
+ gen_helper_msachi(t0, cpu_env, t0, t1);
opn = "msachi";
break;
case OPC_VR54XX_MSACHIU:
- gen_helper_msachiu(t0, t0, t1);
+ gen_helper_msachiu(t0, cpu_env, t0, t1);
opn = "msachiu";
break;
default:
@@ -2683,7 +2701,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
gen_save_pc(dest);
if (ctx->singlestep_enabled) {
save_cpu_state(ctx, 0);
- gen_helper_0i(raise_exception, EXCP_DEBUG);
+ gen_helper_0e0i(raise_exception, EXCP_DEBUG);
}
tcg_gen_exit_tb(0);
}
@@ -3187,17 +3205,17 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpcontrol(arg);
+ gen_helper_mfc0_mvpcontrol(arg, cpu_env);
rn = "MVPControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpconf0(arg);
+ gen_helper_mfc0_mvpconf0(arg, cpu_env);
rn = "MVPConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpconf1(arg);
+ gen_helper_mfc0_mvpconf1(arg, cpu_env);
rn = "MVPConf1";
break;
default:
@@ -3207,7 +3225,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 1:
switch (sel) {
case 0:
- gen_helper_mfc0_random(arg);
+ gen_helper_mfc0_random(arg, cpu_env);
rn = "Random";
break;
case 1:
@@ -3258,37 +3276,37 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcstatus(arg);
+ gen_helper_mfc0_tcstatus(arg, cpu_env);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcbind(arg);
+ gen_helper_mfc0_tcbind(arg, cpu_env);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcrestart(arg);
+ gen_helper_mfc0_tcrestart(arg, cpu_env);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tchalt(arg);
+ gen_helper_mfc0_tchalt(arg, cpu_env);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tccontext(arg);
+ gen_helper_mfc0_tccontext(arg, cpu_env);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcschedule(arg);
+ gen_helper_mfc0_tcschedule(arg, cpu_env);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcschefback(arg);
+ gen_helper_mfc0_tcschefback(arg, cpu_env);
rn = "TCScheFBack";
break;
default:
@@ -3399,7 +3417,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
/* Mark as an IO operation because we read the time. */
if (use_icount)
gen_io_start();
- gen_helper_mfc0_count(arg);
+ gen_helper_mfc0_count(arg, cpu_env);
if (use_icount) {
gen_io_end();
}
@@ -3531,7 +3549,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 17:
switch (sel) {
case 0:
- gen_helper_mfc0_lladdr(arg);
+ gen_helper_mfc0_lladdr(arg, cpu_env);
rn = "LLAddr";
break;
default:
@@ -3541,7 +3559,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 18:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mfc0_watchlo, arg, sel);
+ gen_helper_1e0i(mfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
default:
@@ -3551,7 +3569,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 19:
switch (sel) {
case 0 ...7:
- gen_helper_1i(mfc0_watchhi, arg, sel);
+ gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
default:
@@ -3590,7 +3608,7 @@ static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 23:
switch (sel) {
case 0:
- gen_helper_mfc0_debug(arg); /* EJTAG support */
+ gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
rn = "Debug";
break;
case 1:
@@ -3765,12 +3783,12 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 0:
switch (sel) {
case 0:
- gen_helper_mtc0_index(arg);
+ gen_helper_mtc0_index(cpu_env, arg);
rn = "Index";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_mvpcontrol(arg);
+ gen_helper_mtc0_mvpcontrol(cpu_env, arg);
rn = "MVPControl";
break;
case 2:
@@ -3795,22 +3813,22 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpecontrol(arg);
+ gen_helper_mtc0_vpecontrol(cpu_env, arg);
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeconf0(arg);
+ gen_helper_mtc0_vpeconf0(cpu_env, arg);
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeconf1(arg);
+ gen_helper_mtc0_vpeconf1(cpu_env, arg);
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_yqmask(arg);
+ gen_helper_mtc0_yqmask(cpu_env, arg);
rn = "YQMask";
break;
case 5:
@@ -3825,7 +3843,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeopt(arg);
+ gen_helper_mtc0_vpeopt(cpu_env, arg);
rn = "VPEOpt";
break;
default:
@@ -3835,42 +3853,42 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 2:
switch (sel) {
case 0:
- gen_helper_mtc0_entrylo0(arg);
+ gen_helper_mtc0_entrylo0(cpu_env, arg);
rn = "EntryLo0";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcstatus(arg);
+ gen_helper_mtc0_tcstatus(cpu_env, arg);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcbind(arg);
+ gen_helper_mtc0_tcbind(cpu_env, arg);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcrestart(arg);
+ gen_helper_mtc0_tcrestart(cpu_env, arg);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tchalt(arg);
+ gen_helper_mtc0_tchalt(cpu_env, arg);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tccontext(arg);
+ gen_helper_mtc0_tccontext(cpu_env, arg);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcschedule(arg);
+ gen_helper_mtc0_tcschedule(cpu_env, arg);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcschefback(arg);
+ gen_helper_mtc0_tcschefback(cpu_env, arg);
rn = "TCScheFBack";
break;
default:
@@ -3880,7 +3898,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 3:
switch (sel) {
case 0:
- gen_helper_mtc0_entrylo1(arg);
+ gen_helper_mtc0_entrylo1(cpu_env, arg);
rn = "EntryLo1";
break;
default:
@@ -3890,11 +3908,11 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 4:
switch (sel) {
case 0:
- gen_helper_mtc0_context(arg);
+ gen_helper_mtc0_context(cpu_env, arg);
rn = "Context";
break;
case 1:
-// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
+// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
@@ -3904,12 +3922,12 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 5:
switch (sel) {
case 0:
- gen_helper_mtc0_pagemask(arg);
+ gen_helper_mtc0_pagemask(cpu_env, arg);
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_pagegrain(arg);
+ gen_helper_mtc0_pagegrain(cpu_env, arg);
rn = "PageGrain";
break;
default:
@@ -3919,32 +3937,32 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 6:
switch (sel) {
case 0:
- gen_helper_mtc0_wired(arg);
+ gen_helper_mtc0_wired(cpu_env, arg);
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf0(arg);
+ gen_helper_mtc0_srsconf0(cpu_env, arg);
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf1(arg);
+ gen_helper_mtc0_srsconf1(cpu_env, arg);
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf2(arg);
+ gen_helper_mtc0_srsconf2(cpu_env, arg);
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf3(arg);
+ gen_helper_mtc0_srsconf3(cpu_env, arg);
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf4(arg);
+ gen_helper_mtc0_srsconf4(cpu_env, arg);
rn = "SRSConf4";
break;
default:
@@ -3955,7 +3973,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_hwrena(arg);
+ gen_helper_mtc0_hwrena(cpu_env, arg);
rn = "HWREna";
break;
default:
@@ -3969,7 +3987,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 9:
switch (sel) {
case 0:
- gen_helper_mtc0_count(arg);
+ gen_helper_mtc0_count(cpu_env, arg);
rn = "Count";
break;
/* 6,7 are implementation dependent */
@@ -3980,7 +3998,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 10:
switch (sel) {
case 0:
- gen_helper_mtc0_entryhi(arg);
+ gen_helper_mtc0_entryhi(cpu_env, arg);
rn = "EntryHi";
break;
default:
@@ -3990,7 +4008,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 11:
switch (sel) {
case 0:
- gen_helper_mtc0_compare(arg);
+ gen_helper_mtc0_compare(cpu_env, arg);
rn = "Compare";
break;
/* 6,7 are implementation dependent */
@@ -4002,7 +4020,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
- gen_helper_mtc0_status(arg);
+ gen_helper_mtc0_status(cpu_env, arg);
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
@@ -4010,14 +4028,14 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_intctl(arg);
+ gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsctl(arg);
+ gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSCtl";
@@ -4037,7 +4055,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
- gen_helper_mtc0_cause(arg);
+ gen_helper_mtc0_cause(cpu_env, arg);
rn = "Cause";
break;
default:
@@ -4062,7 +4080,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_ebase(arg);
+ gen_helper_mtc0_ebase(cpu_env, arg);
rn = "EBase";
break;
default:
@@ -4072,7 +4090,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 16:
switch (sel) {
case 0:
- gen_helper_mtc0_config0(arg);
+ gen_helper_mtc0_config0(cpu_env, arg);
rn = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -4082,7 +4100,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
rn = "Config1";
break;
case 2:
- gen_helper_mtc0_config2(arg);
+ gen_helper_mtc0_config2(cpu_env, arg);
rn = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -4109,7 +4127,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 17:
switch (sel) {
case 0:
- gen_helper_mtc0_lladdr(arg);
+ gen_helper_mtc0_lladdr(cpu_env, arg);
rn = "LLAddr";
break;
default:
@@ -4119,7 +4137,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 18:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mtc0_watchlo, arg, sel);
+ gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
default:
@@ -4129,7 +4147,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 19:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mtc0_watchhi, arg, sel);
+ gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
default:
@@ -4141,7 +4159,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 0:
#if defined(TARGET_MIPS64)
check_insn(env, ctx, ISA_MIPS3);
- gen_helper_mtc0_xcontext(arg);
+ gen_helper_mtc0_xcontext(cpu_env, arg);
rn = "XContext";
break;
#endif
@@ -4153,7 +4171,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_helper_mtc0_framemask(arg);
+ gen_helper_mtc0_framemask(cpu_env, arg);
rn = "Framemask";
break;
default:
@@ -4167,20 +4185,20 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 23:
switch (sel) {
case 0:
- gen_helper_mtc0_debug(arg); /* EJTAG support */
+ gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Debug";
break;
case 1:
-// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
rn = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
// break;
case 2:
-// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
rn = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -4188,13 +4206,13 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 3:
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
-// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
+// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
rn = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
// break;
case 4:
-// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
+// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceBPC";
@@ -4217,7 +4235,7 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 25:
switch (sel) {
case 0:
- gen_helper_mtc0_performance0(arg);
+ gen_helper_mtc0_performance0(cpu_env, arg);
rn = "Performance0";
break;
case 1:
@@ -4272,14 +4290,14 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 2:
case 4:
case 6:
- gen_helper_mtc0_taglo(arg);
+ gen_helper_mtc0_taglo(cpu_env, arg);
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_helper_mtc0_datalo(arg);
+ gen_helper_mtc0_datalo(cpu_env, arg);
rn = "DataLo";
break;
default:
@@ -4292,14 +4310,14 @@ static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, i
case 2:
case 4:
case 6:
- gen_helper_mtc0_taghi(arg);
+ gen_helper_mtc0_taghi(cpu_env, arg);
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_helper_mtc0_datahi(arg);
+ gen_helper_mtc0_datahi(cpu_env, arg);
rn = "DataHi";
break;
default:
@@ -4364,17 +4382,17 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpcontrol(arg);
+ gen_helper_mfc0_mvpcontrol(arg, cpu_env);
rn = "MVPControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpconf0(arg);
+ gen_helper_mfc0_mvpconf0(arg, cpu_env);
rn = "MVPConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpconf1(arg);
+ gen_helper_mfc0_mvpconf1(arg, cpu_env);
rn = "MVPConf1";
break;
default:
@@ -4384,7 +4402,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 1:
switch (sel) {
case 0:
- gen_helper_mfc0_random(arg);
+ gen_helper_mfc0_random(arg, cpu_env);
rn = "Random";
break;
case 1:
@@ -4434,37 +4452,37 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcstatus(arg);
+ gen_helper_mfc0_tcstatus(arg, cpu_env);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcbind(arg);
+ gen_helper_mfc0_tcbind(arg, cpu_env);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_dmfc0_tcrestart(arg);
+ gen_helper_dmfc0_tcrestart(arg, cpu_env);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_dmfc0_tchalt(arg);
+ gen_helper_dmfc0_tchalt(arg, cpu_env);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_helper_dmfc0_tccontext(arg);
+ gen_helper_dmfc0_tccontext(arg, cpu_env);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_helper_dmfc0_tcschedule(arg);
+ gen_helper_dmfc0_tcschedule(arg, cpu_env);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_dmfc0_tcschefback(arg);
+ gen_helper_dmfc0_tcschefback(arg, cpu_env);
rn = "TCScheFBack";
break;
default:
@@ -4572,7 +4590,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
/* Mark as an IO operation because we read the time. */
if (use_icount)
gen_io_start();
- gen_helper_mfc0_count(arg);
+ gen_helper_mfc0_count(arg, cpu_env);
if (use_icount) {
gen_io_end();
}
@@ -4701,7 +4719,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 17:
switch (sel) {
case 0:
- gen_helper_dmfc0_lladdr(arg);
+ gen_helper_dmfc0_lladdr(arg, cpu_env);
rn = "LLAddr";
break;
default:
@@ -4711,7 +4729,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 18:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(dmfc0_watchlo, arg, sel);
+ gen_helper_1e0i(dmfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
default:
@@ -4721,7 +4739,7 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 19:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mfc0_watchhi, arg, sel);
+ gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
default:
@@ -4757,23 +4775,23 @@ static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 23:
switch (sel) {
case 0:
- gen_helper_mfc0_debug(arg); /* EJTAG support */
+ gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
rn = "Debug";
break;
case 1:
-// gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
+// gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */
rn = "TraceControl";
// break;
case 2:
-// gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
+// gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */
rn = "TraceControl2";
// break;
case 3:
-// gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
+// gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */
rn = "UserTraceData";
// break;
case 4:
-// gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
+// gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */
rn = "TraceBPC";
// break;
default:
@@ -4931,12 +4949,12 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 0:
switch (sel) {
case 0:
- gen_helper_mtc0_index(arg);
+ gen_helper_mtc0_index(cpu_env, arg);
rn = "Index";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_mvpcontrol(arg);
+ gen_helper_mtc0_mvpcontrol(cpu_env, arg);
rn = "MVPControl";
break;
case 2:
@@ -4961,22 +4979,22 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpecontrol(arg);
+ gen_helper_mtc0_vpecontrol(cpu_env, arg);
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeconf0(arg);
+ gen_helper_mtc0_vpeconf0(cpu_env, arg);
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeconf1(arg);
+ gen_helper_mtc0_vpeconf1(cpu_env, arg);
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_yqmask(arg);
+ gen_helper_mtc0_yqmask(cpu_env, arg);
rn = "YQMask";
break;
case 5:
@@ -4991,7 +5009,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeopt(arg);
+ gen_helper_mtc0_vpeopt(cpu_env, arg);
rn = "VPEOpt";
break;
default:
@@ -5001,42 +5019,42 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 2:
switch (sel) {
case 0:
- gen_helper_mtc0_entrylo0(arg);
+ gen_helper_mtc0_entrylo0(cpu_env, arg);
rn = "EntryLo0";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcstatus(arg);
+ gen_helper_mtc0_tcstatus(cpu_env, arg);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcbind(arg);
+ gen_helper_mtc0_tcbind(cpu_env, arg);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcrestart(arg);
+ gen_helper_mtc0_tcrestart(cpu_env, arg);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tchalt(arg);
+ gen_helper_mtc0_tchalt(cpu_env, arg);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tccontext(arg);
+ gen_helper_mtc0_tccontext(cpu_env, arg);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcschedule(arg);
+ gen_helper_mtc0_tcschedule(cpu_env, arg);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcschefback(arg);
+ gen_helper_mtc0_tcschefback(cpu_env, arg);
rn = "TCScheFBack";
break;
default:
@@ -5046,7 +5064,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 3:
switch (sel) {
case 0:
- gen_helper_mtc0_entrylo1(arg);
+ gen_helper_mtc0_entrylo1(cpu_env, arg);
rn = "EntryLo1";
break;
default:
@@ -5056,11 +5074,11 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 4:
switch (sel) {
case 0:
- gen_helper_mtc0_context(arg);
+ gen_helper_mtc0_context(cpu_env, arg);
rn = "Context";
break;
case 1:
-// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
+// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
@@ -5070,12 +5088,12 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 5:
switch (sel) {
case 0:
- gen_helper_mtc0_pagemask(arg);
+ gen_helper_mtc0_pagemask(cpu_env, arg);
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_pagegrain(arg);
+ gen_helper_mtc0_pagegrain(cpu_env, arg);
rn = "PageGrain";
break;
default:
@@ -5085,32 +5103,32 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 6:
switch (sel) {
case 0:
- gen_helper_mtc0_wired(arg);
+ gen_helper_mtc0_wired(cpu_env, arg);
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf0(arg);
+ gen_helper_mtc0_srsconf0(cpu_env, arg);
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf1(arg);
+ gen_helper_mtc0_srsconf1(cpu_env, arg);
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf2(arg);
+ gen_helper_mtc0_srsconf2(cpu_env, arg);
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf3(arg);
+ gen_helper_mtc0_srsconf3(cpu_env, arg);
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf4(arg);
+ gen_helper_mtc0_srsconf4(cpu_env, arg);
rn = "SRSConf4";
break;
default:
@@ -5121,7 +5139,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_hwrena(arg);
+ gen_helper_mtc0_hwrena(cpu_env, arg);
rn = "HWREna";
break;
default:
@@ -5135,7 +5153,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 9:
switch (sel) {
case 0:
- gen_helper_mtc0_count(arg);
+ gen_helper_mtc0_count(cpu_env, arg);
rn = "Count";
break;
/* 6,7 are implementation dependent */
@@ -5148,7 +5166,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 10:
switch (sel) {
case 0:
- gen_helper_mtc0_entryhi(arg);
+ gen_helper_mtc0_entryhi(cpu_env, arg);
rn = "EntryHi";
break;
default:
@@ -5158,7 +5176,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 11:
switch (sel) {
case 0:
- gen_helper_mtc0_compare(arg);
+ gen_helper_mtc0_compare(cpu_env, arg);
rn = "Compare";
break;
/* 6,7 are implementation dependent */
@@ -5172,7 +5190,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
- gen_helper_mtc0_status(arg);
+ gen_helper_mtc0_status(cpu_env, arg);
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
@@ -5180,14 +5198,14 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_intctl(arg);
+ gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsctl(arg);
+ gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSCtl";
@@ -5212,7 +5230,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
if (use_icount) {
gen_io_start();
}
- gen_helper_mtc0_cause(arg);
+ gen_helper_mtc0_cause(cpu_env, arg);
if (use_icount) {
gen_io_end();
}
@@ -5242,7 +5260,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_ebase(arg);
+ gen_helper_mtc0_ebase(cpu_env, arg);
rn = "EBase";
break;
default:
@@ -5252,7 +5270,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 16:
switch (sel) {
case 0:
- gen_helper_mtc0_config0(arg);
+ gen_helper_mtc0_config0(cpu_env, arg);
rn = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -5262,7 +5280,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
rn = "Config1";
break;
case 2:
- gen_helper_mtc0_config2(arg);
+ gen_helper_mtc0_config2(cpu_env, arg);
rn = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -5280,7 +5298,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 17:
switch (sel) {
case 0:
- gen_helper_mtc0_lladdr(arg);
+ gen_helper_mtc0_lladdr(cpu_env, arg);
rn = "LLAddr";
break;
default:
@@ -5290,7 +5308,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 18:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mtc0_watchlo, arg, sel);
+ gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
default:
@@ -5300,7 +5318,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 19:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mtc0_watchhi, arg, sel);
+ gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
default:
@@ -5311,7 +5329,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS3);
- gen_helper_mtc0_xcontext(arg);
+ gen_helper_mtc0_xcontext(cpu_env, arg);
rn = "XContext";
break;
default:
@@ -5322,7 +5340,7 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_helper_mtc0_framemask(arg);
+ gen_helper_mtc0_framemask(cpu_env, arg);
rn = "Framemask";
break;
default:
@@ -5336,32 +5354,32 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 23:
switch (sel) {
case 0:
- gen_helper_mtc0_debug(arg); /* EJTAG support */
+ gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Debug";
break;
case 1:
-// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceControl";
// break;
case 2:
-// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceControl2";
// break;
case 3:
-// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
+// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "UserTraceData";
// break;
case 4:
-// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
+// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceBPC";
@@ -5384,35 +5402,35 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 25:
switch (sel) {
case 0:
- gen_helper_mtc0_performance0(arg);
+ gen_helper_mtc0_performance0(cpu_env, arg);
rn = "Performance0";
break;
case 1:
-// gen_helper_mtc0_performance1(arg);
+// gen_helper_mtc0_performance1(cpu_env, arg);
rn = "Performance1";
// break;
case 2:
-// gen_helper_mtc0_performance2(arg);
+// gen_helper_mtc0_performance2(cpu_env, arg);
rn = "Performance2";
// break;
case 3:
-// gen_helper_mtc0_performance3(arg);
+// gen_helper_mtc0_performance3(cpu_env, arg);
rn = "Performance3";
// break;
case 4:
-// gen_helper_mtc0_performance4(arg);
+// gen_helper_mtc0_performance4(cpu_env, arg);
rn = "Performance4";
// break;
case 5:
-// gen_helper_mtc0_performance5(arg);
+// gen_helper_mtc0_performance5(cpu_env, arg);
rn = "Performance5";
// break;
case 6:
-// gen_helper_mtc0_performance6(arg);
+// gen_helper_mtc0_performance6(cpu_env, arg);
rn = "Performance6";
// break;
case 7:
-// gen_helper_mtc0_performance7(arg);
+// gen_helper_mtc0_performance7(cpu_env, arg);
rn = "Performance7";
// break;
default:
@@ -5439,14 +5457,14 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 2:
case 4:
case 6:
- gen_helper_mtc0_taglo(arg);
+ gen_helper_mtc0_taglo(cpu_env, arg);
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_helper_mtc0_datalo(arg);
+ gen_helper_mtc0_datalo(cpu_env, arg);
rn = "DataLo";
break;
default:
@@ -5459,14 +5477,14 @@ static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg,
case 2:
case 4:
case 6:
- gen_helper_mtc0_taghi(arg);
+ gen_helper_mtc0_taghi(cpu_env, arg);
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_helper_mtc0_datahi(arg);
+ gen_helper_mtc0_datahi(cpu_env, arg);
rn = "DataHi";
break;
default:
@@ -5533,10 +5551,10 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 1:
switch (sel) {
case 1:
- gen_helper_mftc0_vpecontrol(t0);
+ gen_helper_mftc0_vpecontrol(t0, cpu_env);
break;
case 2:
- gen_helper_mftc0_vpeconf0(t0);
+ gen_helper_mftc0_vpeconf0(t0, cpu_env);
break;
default:
goto die;
@@ -5546,25 +5564,25 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 2:
switch (sel) {
case 1:
- gen_helper_mftc0_tcstatus(t0);
+ gen_helper_mftc0_tcstatus(t0, cpu_env);
break;
case 2:
- gen_helper_mftc0_tcbind(t0);
+ gen_helper_mftc0_tcbind(t0, cpu_env);
break;
case 3:
- gen_helper_mftc0_tcrestart(t0);
+ gen_helper_mftc0_tcrestart(t0, cpu_env);
break;
case 4:
- gen_helper_mftc0_tchalt(t0);
+ gen_helper_mftc0_tchalt(t0, cpu_env);
break;
case 5:
- gen_helper_mftc0_tccontext(t0);
+ gen_helper_mftc0_tccontext(t0, cpu_env);
break;
case 6:
- gen_helper_mftc0_tcschedule(t0);
+ gen_helper_mftc0_tcschedule(t0, cpu_env);
break;
case 7:
- gen_helper_mftc0_tcschefback(t0);
+ gen_helper_mftc0_tcschefback(t0, cpu_env);
break;
default:
gen_mfc0(env, ctx, t0, rt, sel);
@@ -5574,7 +5592,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 10:
switch (sel) {
case 0:
- gen_helper_mftc0_entryhi(t0);
+ gen_helper_mftc0_entryhi(t0, cpu_env);
break;
default:
gen_mfc0(env, ctx, t0, rt, sel);
@@ -5583,7 +5601,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 12:
switch (sel) {
case 0:
- gen_helper_mftc0_status(t0);
+ gen_helper_mftc0_status(t0, cpu_env);
break;
default:
gen_mfc0(env, ctx, t0, rt, sel);
@@ -5592,7 +5610,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 13:
switch (sel) {
case 0:
- gen_helper_mftc0_cause(t0);
+ gen_helper_mftc0_cause(t0, cpu_env);
break;
default:
goto die;
@@ -5602,7 +5620,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 14:
switch (sel) {
case 0:
- gen_helper_mftc0_epc(t0);
+ gen_helper_mftc0_epc(t0, cpu_env);
break;
default:
goto die;
@@ -5612,7 +5630,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 15:
switch (sel) {
case 1:
- gen_helper_mftc0_ebase(t0);
+ gen_helper_mftc0_ebase(t0, cpu_env);
break;
default:
goto die;
@@ -5622,7 +5640,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 16:
switch (sel) {
case 0 ... 7:
- gen_helper_mftc0_configx(t0, tcg_const_tl(sel));
+ gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));
break;
default:
goto die;
@@ -5632,7 +5650,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 23:
switch (sel) {
case 0:
- gen_helper_mftc0_debug(t0);
+ gen_helper_mftc0_debug(t0, cpu_env);
break;
default:
gen_mfc0(env, ctx, t0, rt, sel);
@@ -5645,49 +5663,49 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
} else switch (sel) {
/* GPR registers. */
case 0:
- gen_helper_1i(mftgpr, t0, rt);
+ gen_helper_1e0i(mftgpr, t0, rt);
break;
/* Auxiliary CPU registers */
case 1:
switch (rt) {
case 0:
- gen_helper_1i(mftlo, t0, 0);
+ gen_helper_1e0i(mftlo, t0, 0);
break;
case 1:
- gen_helper_1i(mfthi, t0, 0);
+ gen_helper_1e0i(mfthi, t0, 0);
break;
case 2:
- gen_helper_1i(mftacx, t0, 0);
+ gen_helper_1e0i(mftacx, t0, 0);
break;
case 4:
- gen_helper_1i(mftlo, t0, 1);
+ gen_helper_1e0i(mftlo, t0, 1);
break;
case 5:
- gen_helper_1i(mfthi, t0, 1);
+ gen_helper_1e0i(mfthi, t0, 1);
break;
case 6:
- gen_helper_1i(mftacx, t0, 1);
+ gen_helper_1e0i(mftacx, t0, 1);
break;
case 8:
- gen_helper_1i(mftlo, t0, 2);
+ gen_helper_1e0i(mftlo, t0, 2);
break;
case 9:
- gen_helper_1i(mfthi, t0, 2);
+ gen_helper_1e0i(mfthi, t0, 2);
break;
case 10:
- gen_helper_1i(mftacx, t0, 2);
+ gen_helper_1e0i(mftacx, t0, 2);
break;
case 12:
- gen_helper_1i(mftlo, t0, 3);
+ gen_helper_1e0i(mftlo, t0, 3);
break;
case 13:
- gen_helper_1i(mfthi, t0, 3);
+ gen_helper_1e0i(mfthi, t0, 3);
break;
case 14:
- gen_helper_1i(mftacx, t0, 3);
+ gen_helper_1e0i(mftacx, t0, 3);
break;
case 16:
- gen_helper_mftdsp(t0);
+ gen_helper_mftdsp(t0, cpu_env);
break;
default:
goto die;
@@ -5712,7 +5730,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
break;
case 3:
/* XXX: For now we support only a single FPU context. */
- gen_helper_1i(cfc1, t0, rt);
+ gen_helper_1e0i(cfc1, t0, rt);
break;
/* COP2: Not implemented. */
case 4:
@@ -5751,10 +5769,10 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 1:
switch (sel) {
case 1:
- gen_helper_mttc0_vpecontrol(t0);
+ gen_helper_mttc0_vpecontrol(cpu_env, t0);
break;
case 2:
- gen_helper_mttc0_vpeconf0(t0);
+ gen_helper_mttc0_vpeconf0(cpu_env, t0);
break;
default:
goto die;
@@ -5764,25 +5782,25 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 2:
switch (sel) {
case 1:
- gen_helper_mttc0_tcstatus(t0);
+ gen_helper_mttc0_tcstatus(cpu_env, t0);
break;
case 2:
- gen_helper_mttc0_tcbind(t0);
+ gen_helper_mttc0_tcbind(cpu_env, t0);
break;
case 3:
- gen_helper_mttc0_tcrestart(t0);
+ gen_helper_mttc0_tcrestart(cpu_env, t0);
break;
case 4:
- gen_helper_mttc0_tchalt(t0);
+ gen_helper_mttc0_tchalt(cpu_env, t0);
break;
case 5:
- gen_helper_mttc0_tccontext(t0);
+ gen_helper_mttc0_tccontext(cpu_env, t0);
break;
case 6:
- gen_helper_mttc0_tcschedule(t0);
+ gen_helper_mttc0_tcschedule(cpu_env, t0);
break;
case 7:
- gen_helper_mttc0_tcschefback(t0);
+ gen_helper_mttc0_tcschefback(cpu_env, t0);
break;
default:
gen_mtc0(env, ctx, t0, rd, sel);
@@ -5792,7 +5810,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 10:
switch (sel) {
case 0:
- gen_helper_mttc0_entryhi(t0);
+ gen_helper_mttc0_entryhi(cpu_env, t0);
break;
default:
gen_mtc0(env, ctx, t0, rd, sel);
@@ -5801,7 +5819,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 12:
switch (sel) {
case 0:
- gen_helper_mttc0_status(t0);
+ gen_helper_mttc0_status(cpu_env, t0);
break;
default:
gen_mtc0(env, ctx, t0, rd, sel);
@@ -5810,7 +5828,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 13:
switch (sel) {
case 0:
- gen_helper_mttc0_cause(t0);
+ gen_helper_mttc0_cause(cpu_env, t0);
break;
default:
goto die;
@@ -5820,7 +5838,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 15:
switch (sel) {
case 1:
- gen_helper_mttc0_ebase(t0);
+ gen_helper_mttc0_ebase(cpu_env, t0);
break;
default:
goto die;
@@ -5830,7 +5848,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 23:
switch (sel) {
case 0:
- gen_helper_mttc0_debug(t0);
+ gen_helper_mttc0_debug(cpu_env, t0);
break;
default:
gen_mtc0(env, ctx, t0, rd, sel);
@@ -5843,49 +5861,49 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
} else switch (sel) {
/* GPR registers. */
case 0:
- gen_helper_1i(mttgpr, t0, rd);
+ gen_helper_0e1i(mttgpr, t0, rd);
break;
/* Auxiliary CPU registers */
case 1:
switch (rd) {
case 0:
- gen_helper_1i(mttlo, t0, 0);
+ gen_helper_0e1i(mttlo, t0, 0);
break;
case 1:
- gen_helper_1i(mtthi, t0, 0);
+ gen_helper_0e1i(mtthi, t0, 0);
break;
case 2:
- gen_helper_1i(mttacx, t0, 0);
+ gen_helper_0e1i(mttacx, t0, 0);
break;
case 4:
- gen_helper_1i(mttlo, t0, 1);
+ gen_helper_0e1i(mttlo, t0, 1);
break;
case 5:
- gen_helper_1i(mtthi, t0, 1);
+ gen_helper_0e1i(mtthi, t0, 1);
break;
case 6:
- gen_helper_1i(mttacx, t0, 1);
+ gen_helper_0e1i(mttacx, t0, 1);
break;
case 8:
- gen_helper_1i(mttlo, t0, 2);
+ gen_helper_0e1i(mttlo, t0, 2);
break;
case 9:
- gen_helper_1i(mtthi, t0, 2);
+ gen_helper_0e1i(mtthi, t0, 2);
break;
case 10:
- gen_helper_1i(mttacx, t0, 2);
+ gen_helper_0e1i(mttacx, t0, 2);
break;
case 12:
- gen_helper_1i(mttlo, t0, 3);
+ gen_helper_0e1i(mttlo, t0, 3);
break;
case 13:
- gen_helper_1i(mtthi, t0, 3);
+ gen_helper_0e1i(mtthi, t0, 3);
break;
case 14:
- gen_helper_1i(mttacx, t0, 3);
+ gen_helper_0e1i(mttacx, t0, 3);
break;
case 16:
- gen_helper_mttdsp(t0);
+ gen_helper_mttdsp(cpu_env, t0);
break;
default:
goto die;
@@ -5910,7 +5928,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
break;
case 3:
/* XXX: For now we support only a single FPU context. */
- gen_helper_1i(ctc1, t0, rd);
+ gen_helper_0e1i(ctc1, t0, rd);
break;
/* COP2: Not implemented. */
case 4:
@@ -5995,30 +6013,30 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
opn = "tlbwi";
if (!env->tlb->helper_tlbwi)
goto die;
- gen_helper_tlbwi();
+ gen_helper_tlbwi(cpu_env);
break;
case OPC_TLBWR:
opn = "tlbwr";
if (!env->tlb->helper_tlbwr)
goto die;
- gen_helper_tlbwr();
+ gen_helper_tlbwr(cpu_env);
break;
case OPC_TLBP:
opn = "tlbp";
if (!env->tlb->helper_tlbp)
goto die;
- gen_helper_tlbp();
+ gen_helper_tlbp(cpu_env);
break;
case OPC_TLBR:
opn = "tlbr";
if (!env->tlb->helper_tlbr)
goto die;
- gen_helper_tlbr();
+ gen_helper_tlbr(cpu_env);
break;
case OPC_ERET:
opn = "eret";
check_insn(env, ctx, ISA_MIPS2);
- gen_helper_eret();
+ gen_helper_eret(cpu_env);
ctx->bstate = BS_EXCP;
break;
case OPC_DERET:
@@ -6028,7 +6046,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
} else {
- gen_helper_deret();
+ gen_helper_deret(cpu_env);
ctx->bstate = BS_EXCP;
}
break;
@@ -6039,7 +6057,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
ctx->pc += 4;
save_cpu_state(ctx, 1);
ctx->pc -= 4;
- gen_helper_wait();
+ gen_helper_wait(cpu_env);
ctx->bstate = BS_EXCP;
break;
default:
@@ -6340,13 +6358,13 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
opn = "mtc1";
break;
case OPC_CFC1:
- gen_helper_1i(cfc1, t0, fs);
+ gen_helper_1e0i(cfc1, t0, fs);
gen_store_gpr(t0, rt);
opn = "cfc1";
break;
case OPC_CTC1:
gen_load_gpr(t0, rt);
- gen_helper_1i(ctc1, t0, fs);
+ gen_helper_0e1i(ctc1, t0, fs);
opn = "ctc1";
break;
#if defined(TARGET_MIPS64)
@@ -6543,7 +6561,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
- gen_helper_float_add_s(fp0, fp0, fp1);
+ gen_helper_float_add_s(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
@@ -6558,7 +6576,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
- gen_helper_float_sub_s(fp0, fp0, fp1);
+ gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
@@ -6573,7 +6591,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
- gen_helper_float_mul_s(fp0, fp0, fp1);
+ gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
@@ -6588,7 +6606,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
- gen_helper_float_div_s(fp0, fp0, fp1);
+ gen_helper_float_div_s(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
@@ -6601,7 +6619,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_sqrt_s(fp0, fp0);
+ gen_helper_float_sqrt_s(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -6646,7 +6664,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- gen_helper_float_roundl_s(fp64, fp32);
+ gen_helper_float_roundl_s(fp64, cpu_env, fp32);
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -6660,7 +6678,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- gen_helper_float_truncl_s(fp64, fp32);
+ gen_helper_float_truncl_s(fp64, cpu_env, fp32);
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -6674,7 +6692,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- gen_helper_float_ceill_s(fp64, fp32);
+ gen_helper_float_ceill_s(fp64, cpu_env, fp32);
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -6688,7 +6706,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- gen_helper_float_floorl_s(fp64, fp32);
+ gen_helper_float_floorl_s(fp64, cpu_env, fp32);
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -6700,7 +6718,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_roundw_s(fp0, fp0);
+ gen_helper_float_roundw_s(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -6711,7 +6729,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_truncw_s(fp0, fp0);
+ gen_helper_float_truncw_s(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -6722,7 +6740,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_ceilw_s(fp0, fp0);
+ gen_helper_float_ceilw_s(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -6733,7 +6751,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_floorw_s(fp0, fp0);
+ gen_helper_float_floorw_s(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -6781,7 +6799,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_recip_s(fp0, fp0);
+ gen_helper_float_recip_s(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -6793,7 +6811,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_rsqrt_s(fp0, fp0);
+ gen_helper_float_rsqrt_s(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -6807,7 +6825,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
- gen_helper_float_recip2_s(fp0, fp0, fp1);
+ gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
@@ -6820,7 +6838,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_recip1_s(fp0, fp0);
+ gen_helper_float_recip1_s(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -6832,7 +6850,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_rsqrt1_s(fp0, fp0);
+ gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -6846,7 +6864,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
- gen_helper_float_rsqrt2_s(fp0, fp0, fp1);
+ gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
@@ -6860,7 +6878,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- gen_helper_float_cvtd_s(fp64, fp32);
+ gen_helper_float_cvtd_s(fp64, cpu_env, fp32);
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -6872,7 +6890,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_cvtw_s(fp0, fp0);
+ gen_helper_float_cvtw_s(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -6885,7 +6903,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- gen_helper_float_cvtl_s(fp64, fp32);
+ gen_helper_float_cvtl_s(fp64, cpu_env, fp32);
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -6941,7 +6959,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_add_d(fp0, fp0, fp1);
+ gen_helper_float_add_d(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -6957,7 +6975,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_sub_d(fp0, fp0, fp1);
+ gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -6973,7 +6991,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_mul_d(fp0, fp0, fp1);
+ gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -6989,7 +7007,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_div_d(fp0, fp0, fp1);
+ gen_helper_float_div_d(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -7003,7 +7021,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_sqrt_d(fp0, fp0);
+ gen_helper_float_sqrt_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7050,7 +7068,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_roundl_d(fp0, fp0);
+ gen_helper_float_roundl_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7062,7 +7080,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_truncl_d(fp0, fp0);
+ gen_helper_float_truncl_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7074,7 +7092,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_ceill_d(fp0, fp0);
+ gen_helper_float_ceill_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7086,7 +7104,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_floorl_d(fp0, fp0);
+ gen_helper_float_floorl_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7099,7 +7117,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_roundw_d(fp32, fp64);
+ gen_helper_float_roundw_d(fp32, cpu_env, fp64);
tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
tcg_temp_free_i32(fp32);
@@ -7113,7 +7131,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_truncw_d(fp32, fp64);
+ gen_helper_float_truncw_d(fp32, cpu_env, fp64);
tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
tcg_temp_free_i32(fp32);
@@ -7127,7 +7145,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_ceilw_d(fp32, fp64);
+ gen_helper_float_ceilw_d(fp32, cpu_env, fp64);
tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
tcg_temp_free_i32(fp32);
@@ -7141,7 +7159,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_floorw_d(fp32, fp64);
+ gen_helper_float_floorw_d(fp32, cpu_env, fp64);
tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
tcg_temp_free_i32(fp32);
@@ -7190,7 +7208,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_recip_d(fp0, fp0);
+ gen_helper_float_recip_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7202,7 +7220,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_rsqrt_d(fp0, fp0);
+ gen_helper_float_rsqrt_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7216,7 +7234,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_recip2_d(fp0, fp0, fp1);
+ gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -7229,7 +7247,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_recip1_d(fp0, fp0);
+ gen_helper_float_recip1_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7241,7 +7259,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_rsqrt1_d(fp0, fp0);
+ gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7255,7 +7273,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_rsqrt2_d(fp0, fp0, fp1);
+ gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -7293,7 +7311,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_cvts_d(fp32, fp64);
+ gen_helper_float_cvts_d(fp32, cpu_env, fp64);
tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
tcg_temp_free_i32(fp32);
@@ -7307,7 +7325,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_cvtw_d(fp32, fp64);
+ gen_helper_float_cvtw_d(fp32, cpu_env, fp64);
tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
tcg_temp_free_i32(fp32);
@@ -7320,7 +7338,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_cvtl_d(fp0, fp0);
+ gen_helper_float_cvtl_d(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7331,7 +7349,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_cvts_w(fp0, fp0);
+ gen_helper_float_cvts_w(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -7344,7 +7362,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- gen_helper_float_cvtd_w(fp64, fp32);
+ gen_helper_float_cvtd_w(fp64, cpu_env, fp32);
tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
tcg_temp_free_i64(fp64);
@@ -7358,7 +7376,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_cvts_l(fp32, fp64);
+ gen_helper_float_cvts_l(fp32, cpu_env, fp64);
tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
tcg_temp_free_i32(fp32);
@@ -7371,7 +7389,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_cvtd_l(fp0, fp0);
+ gen_helper_float_cvtd_l(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7383,7 +7401,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_cvtps_pw(fp0, fp0);
+ gen_helper_float_cvtps_pw(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7397,7 +7415,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_add_ps(fp0, fp0, fp1);
+ gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -7412,7 +7430,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_sub_ps(fp0, fp0, fp1);
+ gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -7427,7 +7445,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_mul_ps(fp0, fp0, fp1);
+ gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -7515,7 +7533,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, ft);
gen_load_fpr64(ctx, fp1, fs);
- gen_helper_float_addr_ps(fp0, fp0, fp1);
+ gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -7530,7 +7548,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, ft);
gen_load_fpr64(ctx, fp1, fs);
- gen_helper_float_mulr_ps(fp0, fp0, fp1);
+ gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -7545,7 +7563,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_recip2_ps(fp0, fp0, fp1);
+ gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -7558,7 +7576,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_recip1_ps(fp0, fp0);
+ gen_helper_float_recip1_ps(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7570,7 +7588,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_rsqrt1_ps(fp0, fp0);
+ gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7584,7 +7602,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_rsqrt2_ps(fp0, fp0, fp1);
+ gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
@@ -7597,7 +7615,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32h(fp0, fs);
- gen_helper_float_cvts_pu(fp0, fp0);
+ gen_helper_float_cvts_pu(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -7609,7 +7627,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_cvtpw_ps(fp0, fp0);
+ gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -7621,7 +7639,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- gen_helper_float_cvts_pl(fp0, fp0);
+ gen_helper_float_cvts_pl(fp0, cpu_env, fp0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -7887,7 +7905,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
gen_load_fpr32(fp2, fr);
- gen_helper_float_muladd_s(fp2, fp0, fp1, fp2);
+ gen_helper_float_muladd_s(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
gen_store_fpr32(fp2, fd);
@@ -7906,7 +7924,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_muladd_d(fp2, fp0, fp1, fp2);
+ gen_helper_float_muladd_d(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i64(fp0);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
@@ -7924,7 +7942,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_muladd_ps(fp2, fp0, fp1, fp2);
+ gen_helper_float_muladd_ps(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i64(fp0);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
@@ -7942,7 +7960,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
gen_load_fpr32(fp2, fr);
- gen_helper_float_mulsub_s(fp2, fp0, fp1, fp2);
+ gen_helper_float_mulsub_s(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
gen_store_fpr32(fp2, fd);
@@ -7961,7 +7979,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_mulsub_d(fp2, fp0, fp1, fp2);
+ gen_helper_float_mulsub_d(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i64(fp0);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
@@ -7979,7 +7997,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_mulsub_ps(fp2, fp0, fp1, fp2);
+ gen_helper_float_mulsub_ps(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i64(fp0);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
@@ -7997,7 +8015,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
gen_load_fpr32(fp2, fr);
- gen_helper_float_nmuladd_s(fp2, fp0, fp1, fp2);
+ gen_helper_float_nmuladd_s(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
gen_store_fpr32(fp2, fd);
@@ -8016,7 +8034,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmuladd_d(fp2, fp0, fp1, fp2);
+ gen_helper_float_nmuladd_d(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i64(fp0);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
@@ -8034,7 +8052,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmuladd_ps(fp2, fp0, fp1, fp2);
+ gen_helper_float_nmuladd_ps(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i64(fp0);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
@@ -8052,7 +8070,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
gen_load_fpr32(fp2, fr);
- gen_helper_float_nmulsub_s(fp2, fp0, fp1, fp2);
+ gen_helper_float_nmulsub_s(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i32(fp0);
tcg_temp_free_i32(fp1);
gen_store_fpr32(fp2, fd);
@@ -8071,7 +8089,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmulsub_d(fp2, fp0, fp1, fp2);
+ gen_helper_float_nmulsub_d(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i64(fp0);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
@@ -8089,7 +8107,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmulsub_ps(fp2, fp0, fp1, fp2);
+ gen_helper_float_nmulsub_ps(fp2, cpu_env, fp0, fp1, fp2);
tcg_temp_free_i64(fp0);
tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
@@ -8122,22 +8140,22 @@ gen_rdhwr (CPUMIPSState *env, DisasContext *ctx, int rt, int rd)
switch (rd) {
case 0:
save_cpu_state(ctx, 1);
- gen_helper_rdhwr_cpunum(t0);
+ gen_helper_rdhwr_cpunum(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
case 1:
save_cpu_state(ctx, 1);
- gen_helper_rdhwr_synci_step(t0);
+ gen_helper_rdhwr_synci_step(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
case 2:
save_cpu_state(ctx, 1);
- gen_helper_rdhwr_cc(t0);
+ gen_helper_rdhwr_cc(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
case 3:
save_cpu_state(ctx, 1);
- gen_helper_rdhwr_ccres(t0);
+ gen_helper_rdhwr_ccres(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
case 29:
@@ -8214,7 +8232,7 @@ static void handle_delay_slot (CPUMIPSState *env, DisasContext *ctx,
}
if (ctx->singlestep_enabled) {
save_cpu_state(ctx, 0);
- gen_helper_0i(raise_exception, EXCP_DEBUG);
+ gen_helper_0e0i(raise_exception, EXCP_DEBUG);
}
tcg_gen_exit_tb(0);
break;
@@ -8678,7 +8696,7 @@ static void decode_i64_mips16 (CPUMIPSState *env, DisasContext *ctx,
static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx,
int *is_branch)
{
- int extend = lduw_code(ctx->pc + 2);
+ int extend = cpu_lduw_code(env, ctx->pc + 2);
int op, rx, ry, funct, sa;
int16_t imm, offset;
@@ -8904,7 +8922,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx,
/* No delay slot, so just process as a normal instruction */
break;
case M16_OPC_JAL:
- offset = lduw_code(ctx->pc + 2);
+ offset = cpu_lduw_code(env, ctx->pc + 2);
offset = (((ctx->opcode & 0x1f) << 21)
| ((ctx->opcode >> 5) & 0x1f) << 16
| offset) << 2;
@@ -9855,17 +9873,17 @@ static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist,
save_cpu_state(ctx, 1);
switch (opc) {
case LWM32:
- gen_helper_lwm(t0, t1, t2);
+ gen_helper_lwm(cpu_env, t0, t1, t2);
break;
case SWM32:
- gen_helper_swm(t0, t1, t2);
+ gen_helper_swm(cpu_env, t0, t1, t2);
break;
#ifdef TARGET_MIPS64
case LDM:
- gen_helper_ldm(t0, t1, t2);
+ gen_helper_ldm(cpu_env, t0, t1, t2);
break;
case SDM:
- gen_helper_sdm(t0, t1, t2);
+ gen_helper_sdm(cpu_env, t0, t1, t2);
break;
#endif
}
@@ -10287,7 +10305,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs,
TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1);
- gen_helper_di(t0);
+ gen_helper_di(t0, cpu_env);
gen_store_gpr(t0, rs);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -10300,7 +10318,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs,
TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1);
- gen_helper_ei(t0);
+ gen_helper_ei(t0, cpu_env);
gen_store_gpr(t0, rs);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -10635,7 +10653,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
uint32_t op, minor, mips32_op;
uint32_t cond, fmt, cc;
- insn = lduw_code(ctx->pc + 2);
+ insn = cpu_lduw_code(env, ctx->pc + 2);
ctx->opcode = (ctx->opcode << 16) | insn;
rt = (ctx->opcode >> 21) & 0x1f;
@@ -11827,7 +11845,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
MIPS_INVAL("PMON / selsl");
generate_exception(ctx, EXCP_RI);
#else
- gen_helper_0i(pmon, sa);
+ gen_helper_0e0i(pmon, sa);
#endif
break;
case OPC_SYSCALL:
@@ -12045,7 +12063,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
save_cpu_state(ctx, 1);
gen_load_gpr(t0, rs);
- gen_helper_yield(t0, t0);
+ gen_helper_yield(t0, cpu_env, t0);
gen_store_gpr(t0, rd);
tcg_temp_free(t0);
}
@@ -12144,18 +12162,18 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
break;
case OPC_DVPE:
check_insn(env, ctx, ASE_MT);
- gen_helper_dvpe(t0);
+ gen_helper_dvpe(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
case OPC_EVPE:
check_insn(env, ctx, ASE_MT);
- gen_helper_evpe(t0);
+ gen_helper_evpe(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
case OPC_DI:
check_insn(env, ctx, ISA_MIPS32R2);
save_cpu_state(ctx, 1);
- gen_helper_di(t0);
+ gen_helper_di(t0, cpu_env);
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -12163,7 +12181,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
case OPC_EI:
check_insn(env, ctx, ISA_MIPS32R2);
save_cpu_state(ctx, 1);
- gen_helper_ei(t0);
+ gen_helper_ei(t0, cpu_env);
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -12432,7 +12450,7 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb,
if (bp->pc == ctx.pc) {
save_cpu_state(&ctx, 1);
ctx.bstate = BS_BRANCH;
- gen_helper_0i(raise_exception, EXCP_DEBUG);
+ gen_helper_0e0i(raise_exception, EXCP_DEBUG);
/* Include the breakpoint location or the tb won't
* be flushed when it must be. */
ctx.pc += 4;
@@ -12458,14 +12476,14 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb,
is_branch = 0;
if (!(ctx.hflags & MIPS_HFLAG_M16)) {
- ctx.opcode = ldl_code(ctx.pc);
+ ctx.opcode = cpu_ldl_code(env, ctx.pc);
insn_bytes = 4;
decode_opc(env, &ctx, &is_branch);
} else if (env->insn_flags & ASE_MICROMIPS) {
- ctx.opcode = lduw_code(ctx.pc);
+ ctx.opcode = cpu_lduw_code(env, ctx.pc);
insn_bytes = decode_micromips_opc(env, &ctx, &is_branch);
} else if (env->insn_flags & ASE_MIPS16) {
- ctx.opcode = lduw_code(ctx.pc);
+ ctx.opcode = cpu_lduw_code(env, ctx.pc);
insn_bytes = decode_mips16_opc(env, &ctx, &is_branch);
} else {
generate_exception(&ctx, EXCP_RI);
@@ -12502,7 +12520,7 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb,
gen_io_end();
if (env->singlestep_enabled && ctx.bstate != BS_BRANCH) {
save_cpu_state(&ctx, ctx.bstate == BS_NONE);
- gen_helper_0i(raise_exception, EXCP_DEBUG);
+ gen_helper_0e0i(raise_exception, EXCP_DEBUG);
} else {
switch (ctx.bstate) {
case BS_STOP:
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 20/21] target-mips: switch to AREG0 free mode
2012-09-02 17:33 ` [Qemu-devel] [PATCH 20/21] target-mips: " Blue Swirl
@ 2012-09-03 15:50 ` Aurelien Jarno
2012-09-03 19:15 ` Blue Swirl
0 siblings, 1 reply; 64+ messages in thread
From: Aurelien Jarno @ 2012-09-03 15:50 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel
On Sun, Sep 02, 2012 at 05:33:49PM +0000, Blue Swirl wrote:
> Add an explicit CPUState parameter instead of relying on AREG0
> and switch to AREG0 free mode.
>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> ---
> configure | 2 +-
> target-mips/Makefile.objs | 2 -
> target-mips/cpu.h | 16 +-
> target-mips/helper.h | 410 +++++++++---------
> target-mips/op_helper.c | 1065 ++++++++++++++++++++++++---------------------
> target-mips/translate.c | 754 ++++++++++++++++----------------
> 6 files changed, 1163 insertions(+), 1086 deletions(-)
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Please commit this patch asap after the 1.2 release, even if the patches
for the other targets are not ready, so that it doesn't hold the
development.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 20/21] target-mips: switch to AREG0 free mode
2012-09-03 15:50 ` Aurelien Jarno
@ 2012-09-03 19:15 ` Blue Swirl
2012-09-03 19:49 ` Aurelien Jarno
0 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-03 19:15 UTC (permalink / raw)
To: Aurelien Jarno, Ethan Hunt; +Cc: qemu-devel
On Mon, Sep 3, 2012 at 3:50 PM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Sun, Sep 02, 2012 at 05:33:49PM +0000, Blue Swirl wrote:
>> Add an explicit CPUState parameter instead of relying on AREG0
>> and switch to AREG0 free mode.
>>
>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>> ---
>> configure | 2 +-
>> target-mips/Makefile.objs | 2 -
>> target-mips/cpu.h | 16 +-
>> target-mips/helper.h | 410 +++++++++---------
>> target-mips/op_helper.c | 1065 ++++++++++++++++++++++++---------------------
>> target-mips/translate.c | 754 ++++++++++++++++----------------
>> 6 files changed, 1163 insertions(+), 1086 deletions(-)
>
> Acked-by: Aurelien Jarno <aurelien@aurel32.net>
>
> Please commit this patch asap after the 1.2 release, even if the patches
> for the other targets are not ready, so that it doesn't hold the
> development.
Thanks. There's at least Jia Liu's MIPS DSP series, it probably does
not conflict so much but it hasn't been converted to new AREG0-free
order either.
>
> --
> Aurelien Jarno GPG: 1024D/F1BCDB73
> aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 20/21] target-mips: switch to AREG0 free mode
2012-09-03 19:15 ` Blue Swirl
@ 2012-09-03 19:49 ` Aurelien Jarno
0 siblings, 0 replies; 64+ messages in thread
From: Aurelien Jarno @ 2012-09-03 19:49 UTC (permalink / raw)
To: Blue Swirl; +Cc: Ethan Hunt, qemu-devel
On Mon, Sep 03, 2012 at 07:15:29PM +0000, Blue Swirl wrote:
> On Mon, Sep 3, 2012 at 3:50 PM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> > On Sun, Sep 02, 2012 at 05:33:49PM +0000, Blue Swirl wrote:
> >> Add an explicit CPUState parameter instead of relying on AREG0
> >> and switch to AREG0 free mode.
> >>
> >> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> >> ---
> >> configure | 2 +-
> >> target-mips/Makefile.objs | 2 -
> >> target-mips/cpu.h | 16 +-
> >> target-mips/helper.h | 410 +++++++++---------
> >> target-mips/op_helper.c | 1065 ++++++++++++++++++++++++---------------------
> >> target-mips/translate.c | 754 ++++++++++++++++----------------
> >> 6 files changed, 1163 insertions(+), 1086 deletions(-)
> >
> > Acked-by: Aurelien Jarno <aurelien@aurel32.net>
> >
> > Please commit this patch asap after the 1.2 release, even if the patches
> > for the other targets are not ready, so that it doesn't hold the
> > development.
>
> Thanks. There's at least Jia Liu's MIPS DSP series, it probably does
> not conflict so much but it hasn't been converted to new AREG0-free
> order either.
>
I am still reviewing it, but I don't think it is ready yet, so it's
better to get the AREG0 patches first.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread
* [Qemu-devel] [PATCH 21/21] Remove unused CONFIG_TCG_PASS_AREG0 and dead code
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (19 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 20/21] target-mips: " Blue Swirl
@ 2012-09-02 17:33 ` Blue Swirl
2012-09-06 15:30 ` Aurelien Jarno
2012-09-04 18:52 ` [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Richard Henderson
21 siblings, 1 reply; 64+ messages in thread
From: Blue Swirl @ 2012-09-02 17:33 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Weil, Alexander Graf, blauwirbel, Paul Brook,
Aurelien Jarno, Richard Henderson
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,
remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.
Remove dyngen-exec.h and all references to it. Although included by
hw/spapr_hcall.c, it does not seem to use it.
Remove unused HELPER_CFLAGS.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
Makefile.target | 8 -----
configure | 11 -------
cpu-all.h | 11 -------
cputlb.c | 4 --
dyngen-exec.h | 70 ------------------------------------------
exec-all.h | 4 --
hw/spapr_hcall.c | 1 -
softmmu_defs.h | 21 -------------
| 63 ++++++++++++--------------------------
softmmu_template.h | 72 ++++++++++++++++---------------------------
target-m68k/op_helper.c | 3 --
target-sparc/Makefile.objs | 2 -
tcg/arm/tcg-target.c | 31 ++-----------------
tcg/arm/tcg-target.h | 1 -
tcg/hppa/tcg-target.c | 24 --------------
tcg/hppa/tcg-target.h | 1 -
tcg/i386/tcg-target.c | 30 ------------------
tcg/i386/tcg-target.h | 1 -
tcg/ia64/tcg-target.c | 34 --------------------
tcg/ia64/tcg-target.h | 1 -
tcg/mips/tcg-target.c | 31 ++-----------------
tcg/mips/tcg-target.h | 1 -
tcg/ppc/tcg-target.c | 38 -----------------------
tcg/ppc64/tcg-target.c | 28 -----------------
tcg/s390/tcg-target.c | 24 --------------
tcg/s390/tcg-target.h | 1 -
tcg/sparc/tcg-target.c | 30 ------------------
tcg/sparc/tcg-target.h | 1 -
tcg/tci/tcg-target.c | 4 --
tci.c | 12 -------
user-exec.c | 14 --------
31 files changed, 53 insertions(+), 524 deletions(-)
delete mode 100644 dyngen-exec.h
diff --git a/Makefile.target b/Makefile.target
index 7892a8d..d9d54b8 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -80,14 +80,6 @@ obj-$(CONFIG_GDBSTUB_XML) += gdbstub-xml.o
tci-dis.o: QEMU_CFLAGS += -I$(SRC_PATH)/tcg -I$(SRC_PATH)/tcg/tci
-# HELPER_CFLAGS is used for all the legacy code compiled with static register
-# variables
-user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
-
-# Note: this is a workaround. The real fix is to avoid compiling
-# cpu_signal_handler() in user-exec.c.
-%/signal.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
-
#########################################################
# Linux user emulator target
diff --git a/configure b/configure
index f60a4b6..e7d333b 100755
--- a/configure
+++ b/configure
@@ -118,7 +118,6 @@ audio_card_list="ac97 es1370 sb16 hda"
audio_possible_cards="ac97 es1370 sb16 cs4231a adlib gus hda"
block_drv_whitelist=""
host_cc="gcc"
-helper_cflags=""
libs_softmmu=""
libs_tools=""
audio_pt_int=""
@@ -894,7 +893,6 @@ case "$cpu" in
QEMU_CFLAGS="-m32 -ffixed-g2 -ffixed-g3 $QEMU_CFLAGS"
if test "$solaris" = "no" ; then
QEMU_CFLAGS="-ffixed-g1 -ffixed-g6 $QEMU_CFLAGS"
- helper_cflags="-ffixed-i0"
fi
;;
sparc64)
@@ -919,7 +917,6 @@ case "$cpu" in
QEMU_CFLAGS="-m32 $QEMU_CFLAGS"
LDFLAGS="-m32 $LDFLAGS"
cc_i386='$(CC) -m32'
- helper_cflags="-fomit-frame-pointer"
host_guest_base="yes"
;;
x86_64)
@@ -3572,7 +3569,6 @@ if test "$sparse" = "yes" ; then
echo "HOST_CC := REAL_CC=\"\$(HOST_CC)\" cgcc" >> $config_host_mak
echo "QEMU_CFLAGS += -Wbitwise -Wno-transparent-union -Wno-old-initializer -Wno-non-pointer-null" >> $config_host_mak
fi
-echo "HELPER_CFLAGS=$helper_cflags" >> $config_host_mak
echo "LDFLAGS=$LDFLAGS" >> $config_host_mak
echo "ARLIBS_BEGIN=$arlibs_begin" >> $config_host_mak
echo "ARLIBS_END=$arlibs_end" >> $config_host_mak
@@ -3827,13 +3823,6 @@ fi
symlink "$source_path/Makefile.target" "$target_dir/Makefile"
-
-case "$target_arch2" in
- alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | mips* | or32 | s390x | sh4* | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
- echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
- ;;
-esac
-
upper() {
echo "$@"| LC_ALL=C tr '[a-z]' '[A-Z]'
}
diff --git a/cpu-all.h b/cpu-all.h
index 5e07d28..74d3681 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -260,14 +260,6 @@ extern unsigned long reserved_va;
#define stfl(p, v) stfl_raw(p, v)
#define stfq(p, v) stfq_raw(p, v)
-#ifndef CONFIG_TCG_PASS_AREG0
-#define ldub_code(p) ldub_raw(p)
-#define ldsb_code(p) ldsb_raw(p)
-#define lduw_code(p) lduw_raw(p)
-#define ldsw_code(p) ldsw_raw(p)
-#define ldl_code(p) ldl_raw(p)
-#define ldq_code(p) ldq_raw(p)
-#else
#define cpu_ldub_code(env1, p) ldub_raw(p)
#define cpu_ldsb_code(env1, p) ldsb_raw(p)
#define cpu_lduw_code(env1, p) lduw_raw(p)
@@ -296,7 +288,6 @@ extern unsigned long reserved_va;
#define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
#define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
#define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)
-#endif
#define ldub_kernel(p) ldub_raw(p)
#define ldsb_kernel(p) ldsb_raw(p)
@@ -313,7 +304,6 @@ extern unsigned long reserved_va;
#define stfl_kernel(p, v) stfl_raw(p, v)
#define stfq_kernel(p, vt) stfq_raw(p, v)
-#ifdef CONFIG_TCG_PASS_AREG0
#define cpu_ldub_data(env, addr) ldub_raw(addr)
#define cpu_lduw_data(env, addr) lduw_raw(addr)
#define cpu_ldl_data(env, addr) ldl_raw(addr)
@@ -321,7 +311,6 @@ extern unsigned long reserved_va;
#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
-#endif
#endif /* defined(CONFIG_USER_ONLY) */
/* page related stuff */
diff --git a/cputlb.c b/cputlb.c
index d3e7b25..8468517 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -325,11 +325,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
mmu_idx = cpu_mmu_index(env1);
if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
(addr & TARGET_PAGE_MASK))) {
-#ifdef CONFIG_TCG_PASS_AREG0
cpu_ldub_code(env1, addr);
-#else
- ldub_code(addr);
-#endif
}
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
mr = iotlb_to_region(pd);
diff --git a/dyngen-exec.h b/dyngen-exec.h
deleted file mode 100644
index 083e20b..0000000
--- a/dyngen-exec.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * dyngen defines for micro operation code
- *
- * Copyright (c) 2003 Fabrice Bellard
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-#if !defined(__DYNGEN_EXEC_H__)
-#define __DYNGEN_EXEC_H__
-
-#if defined(CONFIG_TCG_INTERPRETER)
-/* The TCG interpreter does not need a special register AREG0,
- * but it is possible to use one by defining AREG0.
- * On i386, register edi seems to work. */
-/* Run without special register AREG0 or use a value defined elsewhere. */
-#elif defined(__i386__)
-#define AREG0 "ebp"
-#elif defined(__x86_64__)
-#define AREG0 "r14"
-#elif defined(_ARCH_PPC)
-#define AREG0 "r27"
-#elif defined(__arm__)
-#define AREG0 "r6"
-#elif defined(__hppa__)
-#define AREG0 "r17"
-#elif defined(__mips__)
-#define AREG0 "s0"
-#elif defined(__sparc__)
-#ifdef CONFIG_SOLARIS
-#define AREG0 "g2"
-#else
-#ifdef __sparc_v9__
-#define AREG0 "g5"
-#else
-#define AREG0 "g6"
-#endif
-#endif
-#elif defined(__s390__)
-#define AREG0 "r10"
-#elif defined(__alpha__)
-/* Note $15 is the frame pointer, so anything in op-i386.c that would
- require a frame pointer, like alloca, would probably loose. */
-#define AREG0 "$15"
-#elif defined(__mc68000)
-#define AREG0 "%a5"
-#elif defined(__ia64__)
-#define AREG0 "r7"
-#else
-#error unsupported CPU
-#endif
-
-#if defined(AREG0)
-register CPUArchState *env asm(AREG0);
-#else
-/* TODO: Try env = cpu_single_env. */
-extern CPUArchState *env;
-#endif
-
-#endif /* !defined(__DYNGEN_EXEC_H__) */
diff --git a/exec-all.h b/exec-all.h
index c5ec8e1..c5d3a13 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -323,9 +323,6 @@ void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
#define ACCESS_TYPE (NB_MMU_MODES + 1)
#define MEMSUFFIX _code
-#ifndef CONFIG_TCG_PASS_AREG0
-#define env cpu_single_env
-#endif
#define DATA_SIZE 1
#include "softmmu_header.h"
@@ -341,7 +338,6 @@ void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
#undef ACCESS_TYPE
#undef MEMSUFFIX
-#undef env
#endif
diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c
index a5990a9..abd847f 100644
--- a/hw/spapr_hcall.c
+++ b/hw/spapr_hcall.c
@@ -1,6 +1,5 @@
#include "sysemu.h"
#include "cpu.h"
-#include "dyngen-exec.h"
#include "qemu-char.h"
#include "sysemu.h"
#include "qemu-char.h"
diff --git a/softmmu_defs.h b/softmmu_defs.h
index 8d59f9d..1f25e33 100644
--- a/softmmu_defs.h
+++ b/softmmu_defs.h
@@ -9,25 +9,6 @@
#ifndef SOFTMMU_DEFS_H
#define SOFTMMU_DEFS_H
-#ifndef CONFIG_TCG_PASS_AREG0
-uint8_t __ldb_mmu(target_ulong addr, int mmu_idx);
-void __stb_mmu(target_ulong addr, uint8_t val, int mmu_idx);
-uint16_t __ldw_mmu(target_ulong addr, int mmu_idx);
-void __stw_mmu(target_ulong addr, uint16_t val, int mmu_idx);
-uint32_t __ldl_mmu(target_ulong addr, int mmu_idx);
-void __stl_mmu(target_ulong addr, uint32_t val, int mmu_idx);
-uint64_t __ldq_mmu(target_ulong addr, int mmu_idx);
-void __stq_mmu(target_ulong addr, uint64_t val, int mmu_idx);
-
-uint8_t __ldb_cmmu(target_ulong addr, int mmu_idx);
-void __stb_cmmu(target_ulong addr, uint8_t val, int mmu_idx);
-uint16_t __ldw_cmmu(target_ulong addr, int mmu_idx);
-void __stw_cmmu(target_ulong addr, uint16_t val, int mmu_idx);
-uint32_t __ldl_cmmu(target_ulong addr, int mmu_idx);
-void __stl_cmmu(target_ulong addr, uint32_t val, int mmu_idx);
-uint64_t __ldq_cmmu(target_ulong addr, int mmu_idx);
-void __stq_cmmu(target_ulong addr, uint64_t val, int mmu_idx);
-#else
uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
int mmu_idx);
@@ -54,5 +35,3 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
void helper_stq_cmmu(CPUArchState *env, target_ulong addr, uint64_t val,
int mmu_idx);
#endif
-
-#endif
--git a/softmmu_header.h b/softmmu_header.h
index cf1aa38..d8d9c81 100644
--- a/softmmu_header.h
+++ b/softmmu_header.h
@@ -78,23 +78,10 @@
#define ADDR_READ addr_read
#endif
-#ifndef CONFIG_TCG_PASS_AREG0
-#define ENV_PARAM
-#define ENV_VAR
-#define CPU_PREFIX
-#define HELPER_PREFIX __
-#else
-#define ENV_PARAM CPUArchState *env,
-#define ENV_VAR env,
-#define CPU_PREFIX cpu_
-#define HELPER_PREFIX helper_
-#endif
-
/* generic load/store macros */
static inline RES_TYPE
-glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
- target_ulong ptr)
+glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
{
int page_index;
RES_TYPE res;
@@ -106,9 +93,7 @@ glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
mmu_idx = CPU_MMU_INDEX;
if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
- res = glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_VAR
- addr,
- mmu_idx);
+ res = glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx);
} else {
uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
res = glue(glue(ld, USUFFIX), _raw)(hostaddr);
@@ -118,8 +103,7 @@ glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
#if DATA_SIZE <= 2
static inline int
-glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
- target_ulong ptr)
+glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
{
int res, page_index;
target_ulong addr;
@@ -130,8 +114,8 @@ glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
mmu_idx = CPU_MMU_INDEX;
if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
- res = (DATA_STYPE)glue(glue(glue(HELPER_PREFIX, ld), SUFFIX),
- MMUSUFFIX)(ENV_VAR addr, mmu_idx);
+ res = (DATA_STYPE)glue(glue(helper_ld, SUFFIX),
+ MMUSUFFIX)(env, addr, mmu_idx);
} else {
uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
res = glue(glue(lds, SUFFIX), _raw)(hostaddr);
@@ -145,8 +129,8 @@ glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
/* generic store macro */
static inline void
-glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
- RES_TYPE v)
+glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
+ RES_TYPE v)
{
int page_index;
target_ulong addr;
@@ -157,8 +141,7 @@ glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
mmu_idx = CPU_MMU_INDEX;
if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
- glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_VAR addr, v,
- mmu_idx);
+ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(env, addr, v, mmu_idx);
} else {
uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
glue(glue(st, SUFFIX), _raw)(hostaddr, v);
@@ -170,52 +153,50 @@ glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
#if ACCESS_TYPE != (NB_MMU_MODES + 1)
#if DATA_SIZE == 8
-static inline float64 glue(glue(CPU_PREFIX, ldfq), MEMSUFFIX)(ENV_PARAM
- target_ulong ptr)
+static inline float64 glue(cpu_ldfq, MEMSUFFIX)(CPUArchState *env,
+ target_ulong ptr)
{
union {
float64 d;
uint64_t i;
} u;
- u.i = glue(glue(CPU_PREFIX, ldq), MEMSUFFIX)(ENV_VAR ptr);
+ u.i = glue(cpu_ldq, MEMSUFFIX)(env, ptr);
return u.d;
}
-static inline void glue(glue(CPU_PREFIX, stfq), MEMSUFFIX)(ENV_PARAM
- target_ulong ptr,
- float64 v)
+static inline void glue(cpu_stfq, MEMSUFFIX)(CPUArchState *env,
+ target_ulong ptr, float64 v)
{
union {
float64 d;
uint64_t i;
} u;
u.d = v;
- glue(glue(CPU_PREFIX, stq), MEMSUFFIX)(ENV_VAR ptr, u.i);
+ glue(cpu_stq, MEMSUFFIX)(env, ptr, u.i);
}
#endif /* DATA_SIZE == 8 */
#if DATA_SIZE == 4
-static inline float32 glue(glue(CPU_PREFIX, ldfl), MEMSUFFIX)(ENV_PARAM
- target_ulong ptr)
+static inline float32 glue(cpu_ldfl, MEMSUFFIX)(CPUArchState *env,
+ target_ulong ptr)
{
union {
float32 f;
uint32_t i;
} u;
- u.i = glue(glue(CPU_PREFIX, ldl), MEMSUFFIX)(ENV_VAR ptr);
+ u.i = glue(cpu_ldl, MEMSUFFIX)(env, ptr);
return u.f;
}
-static inline void glue(glue(CPU_PREFIX, stfl), MEMSUFFIX)(ENV_PARAM
- target_ulong ptr,
- float32 v)
+static inline void glue(cpu_stfl, MEMSUFFIX)(CPUArchState *env,
+ target_ulong ptr, float32 v)
{
union {
float32 f;
uint32_t i;
} u;
u.f = v;
- glue(glue(CPU_PREFIX, stl), MEMSUFFIX)(ENV_VAR ptr, u.i);
+ glue(cpu_stl, MEMSUFFIX)(env, ptr, u.i);
}
#endif /* DATA_SIZE == 4 */
@@ -230,7 +211,3 @@ static inline void glue(glue(CPU_PREFIX, stfl), MEMSUFFIX)(ENV_PARAM
#undef CPU_MMU_INDEX
#undef MMUSUFFIX
#undef ADDR_READ
-#undef ENV_PARAM
-#undef ENV_VAR
-#undef CPU_PREFIX
-#undef HELPER_PREFIX
diff --git a/softmmu_template.h b/softmmu_template.h
index b8bd700..e2490f0 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -54,23 +54,11 @@
#define ADDR_READ addr_read
#endif
-#ifndef CONFIG_TCG_PASS_AREG0
-#define ENV_PARAM
-#define ENV_VAR
-#define CPU_PREFIX
-#define HELPER_PREFIX __
-#else
-#define ENV_PARAM CPUArchState *env,
-#define ENV_VAR env,
-#define CPU_PREFIX cpu_
-#define HELPER_PREFIX helper_
-#endif
-
-static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
+static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
target_ulong addr,
int mmu_idx,
uintptr_t retaddr);
-static inline DATA_TYPE glue(io_read, SUFFIX)(ENV_PARAM
+static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
target_phys_addr_t physaddr,
target_ulong addr,
uintptr_t retaddr)
@@ -104,9 +92,8 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(ENV_PARAM
/* handle all cases except unaligned access which span two pages */
DATA_TYPE
-glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
- target_ulong addr,
- int mmu_idx)
+glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
+ int mmu_idx)
{
DATA_TYPE res;
int index;
@@ -126,15 +113,15 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
goto do_unaligned_access;
retaddr = GETPC();
ioaddr = env->iotlb[mmu_idx][index];
- res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
+ res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
/* slow unaligned access (it spans two pages or IO) */
do_unaligned_access:
retaddr = GETPC();
#ifdef ALIGNED_ONLY
- do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
+ do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
- res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr,
+ res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr,
mmu_idx, retaddr);
} else {
/* unaligned/aligned access in the same page */
@@ -142,7 +129,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
#ifdef ALIGNED_ONLY
if ((addr & (DATA_SIZE - 1)) != 0) {
retaddr = GETPC();
- do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
+ do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
}
#endif
addend = env->tlb_table[mmu_idx][index].addend;
@@ -154,7 +141,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
retaddr = GETPC();
#ifdef ALIGNED_ONLY
if ((addr & (DATA_SIZE - 1)) != 0)
- do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
+ do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
goto redo;
@@ -164,7 +151,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
/* handle all unaligned cases */
static DATA_TYPE
-glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
+glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
target_ulong addr,
int mmu_idx,
uintptr_t retaddr)
@@ -183,15 +170,15 @@ glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
if ((addr & (DATA_SIZE - 1)) != 0)
goto do_unaligned_access;
ioaddr = env->iotlb[mmu_idx][index];
- res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
+ res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
do_unaligned_access:
/* slow unaligned access (it spans two pages) */
addr1 = addr & ~(DATA_SIZE - 1);
addr2 = addr1 + DATA_SIZE;
- res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr1,
+ res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr1,
mmu_idx, retaddr);
- res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr2,
+ res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr2,
mmu_idx, retaddr);
shift = (addr & (DATA_SIZE - 1)) * 8;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -216,13 +203,13 @@ glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
#ifndef SOFTMMU_CODE_ACCESS
-static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
+static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
target_ulong addr,
DATA_TYPE val,
int mmu_idx,
uintptr_t retaddr);
-static inline void glue(io_write, SUFFIX)(ENV_PARAM
+static inline void glue(io_write, SUFFIX)(CPUArchState *env,
target_phys_addr_t physaddr,
DATA_TYPE val,
target_ulong addr,
@@ -253,10 +240,9 @@ static inline void glue(io_write, SUFFIX)(ENV_PARAM
#endif /* SHIFT > 2 */
}
-void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
- target_ulong addr,
- DATA_TYPE val,
- int mmu_idx)
+void glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
+ target_ulong addr, DATA_TYPE val,
+ int mmu_idx)
{
target_phys_addr_t ioaddr;
target_ulong tlb_addr;
@@ -273,14 +259,14 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
goto do_unaligned_access;
retaddr = GETPC();
ioaddr = env->iotlb[mmu_idx][index];
- glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
+ glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
do_unaligned_access:
retaddr = GETPC();
#ifdef ALIGNED_ONLY
- do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
+ do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
#endif
- glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_VAR addr, val,
+ glue(glue(slow_st, SUFFIX), MMUSUFFIX)(env, addr, val,
mmu_idx, retaddr);
} else {
/* aligned/unaligned access in the same page */
@@ -288,7 +274,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
#ifdef ALIGNED_ONLY
if ((addr & (DATA_SIZE - 1)) != 0) {
retaddr = GETPC();
- do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
+ do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
}
#endif
addend = env->tlb_table[mmu_idx][index].addend;
@@ -300,7 +286,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
retaddr = GETPC();
#ifdef ALIGNED_ONLY
if ((addr & (DATA_SIZE - 1)) != 0)
- do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
+ do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
#endif
tlb_fill(env, addr, 1, mmu_idx, retaddr);
goto redo;
@@ -308,7 +294,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
}
/* handles all unaligned cases */
-static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
+static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
target_ulong addr,
DATA_TYPE val,
int mmu_idx,
@@ -327,7 +313,7 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
if ((addr & (DATA_SIZE - 1)) != 0)
goto do_unaligned_access;
ioaddr = env->iotlb[mmu_idx][index];
- glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
+ glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
do_unaligned_access:
/* XXX: not efficient, but simple */
@@ -335,11 +321,11 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
* previous page from the TLB cache. */
for(i = DATA_SIZE - 1; i >= 0; i--) {
#ifdef TARGET_WORDS_BIGENDIAN
- glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
+ glue(slow_stb, MMUSUFFIX)(env, addr + i,
val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
mmu_idx, retaddr);
#else
- glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
+ glue(slow_stb, MMUSUFFIX)(env, addr + i,
val >> (i * 8),
mmu_idx, retaddr);
#endif
@@ -366,7 +352,3 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
#undef USUFFIX
#undef DATA_SIZE
#undef ADDR_READ
-#undef ENV_PARAM
-#undef ENV_VAR
-#undef CPU_PREFIX
-#undef HELPER_PREFIX
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 3116287..aa00504 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -192,9 +192,6 @@ void HELPER(divu)(CPUM68KState *env, uint32_t word)
quot = num / den;
rem = num % den;
flags = 0;
- /* Avoid using a PARAM1 of zero. This breaks dyngen because it uses
- the address of a symbol, and gcc knows symbols can't have address
- zero. */
if (word && quot > 0xffff)
flags |= CCF_V;
if (quot == 0)
diff --git a/target-sparc/Makefile.objs b/target-sparc/Makefile.objs
index a93e07d..9fc42ea 100644
--- a/target-sparc/Makefile.objs
+++ b/target-sparc/Makefile.objs
@@ -4,5 +4,3 @@ obj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
obj-$(TARGET_SPARC) += int32_helper.o
obj-$(TARGET_SPARC64) += int64_helper.o
obj-$(TARGET_SPARC64) += vis_helper.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index cf0ca3d..aed3b53 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -176,7 +176,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
so don't use these. */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
-#if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
+#if TARGET_LONG_BITS == 64
/* If we're passing env to the helper as r0 and need a regpair
* for the address then r2 will be overwritten as we're setting
* up the args to the helper.
@@ -204,8 +204,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
use these. */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
-#if defined(CONFIG_SOFTMMU) && \
- defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
+#if defined(CONFIG_SOFTMMU) && (TARGET_LONG_BITS == 64)
/* Avoid clashes with registers being used for helper args */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
@@ -223,7 +222,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
#ifdef CONFIG_SOFTMMU
/* r2 is still needed to load data_reg, so don't use it. */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
-#if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
+#if TARGET_LONG_BITS == 64
/* Avoid clashes with registers being used for helper args */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
#endif
@@ -954,7 +953,6 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
#include "../../softmmu_defs.h"
-#ifdef CONFIG_TCG_PASS_AREG0
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
int mmu_idx) */
static const void * const qemu_ld_helpers[4] = {
@@ -972,25 +970,6 @@ static const void * const qemu_st_helpers[4] = {
helper_stl_mmu,
helper_stq_mmu,
};
-#else
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
- mmu_idx) */
-static void *qemu_ld_helpers[4] = {
- __ldb_mmu,
- __ldw_mmu,
- __ldl_mmu,
- __ldq_mmu,
-};
-
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
- int mmu_idx) */
-static void *qemu_st_helpers[4] = {
- __stb_mmu,
- __stw_mmu,
- __stl_mmu,
- __stq_mmu,
-};
-#endif
/* Helper routines for marshalling helper function arguments into
* the correct registers and stack.
@@ -1203,9 +1182,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
* trash by moving the earlier arguments into them.
*/
argreg = TCG_REG_R0;
-#ifdef CONFIG_TCG_PASS_AREG0
argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
-#endif
#if TARGET_LONG_BITS == 64
argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
#else
@@ -1421,9 +1398,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
* trash by moving the earlier arguments into them.
*/
argreg = TCG_REG_R0;
-#ifdef CONFIG_TCG_PASS_AREG0
argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
-#endif
#if TARGET_LONG_BITS == 64
argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
#else
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index f90b834..c0b8f72 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -77,7 +77,6 @@ typedef enum {
#define TCG_TARGET_HAS_GUEST_BASE
enum {
- /* Note: must be synced with dyngen-exec.h */
TCG_AREG0 = TCG_REG_R6,
};
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index 2885212..8b81b70 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -882,7 +882,6 @@ static void tcg_out_setcond2(TCGContext *s, int cond, TCGArg ret,
#if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h"
-#ifdef CONFIG_TCG_PASS_AREG0
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
int mmu_idx) */
static const void * const qemu_ld_helpers[4] = {
@@ -900,25 +899,6 @@ static const void * const qemu_st_helpers[4] = {
helper_stl_mmu,
helper_stq_mmu,
};
-#else
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
- mmu_idx) */
-static void *qemu_ld_helpers[4] = {
- __ldb_mmu,
- __ldw_mmu,
- __ldl_mmu,
- __ldq_mmu,
-};
-
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
- int mmu_idx) */
-static void *qemu_st_helpers[4] = {
- __stb_mmu,
- __stw_mmu,
- __stl_mmu,
- __stq_mmu,
-};
-#endif
/* Load and compare a TLB entry, and branch if TLB miss. OFFSET is set to
the offset of the first ADDR_READ or ADDR_WRITE member of the appropriate
@@ -1085,7 +1065,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
}
tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
-#ifdef CONFIG_TCG_PASS_AREG0
/* XXX/FIXME: suboptimal */
tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2],
tcg_target_call_iarg_regs[1]);
@@ -1093,7 +1072,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_target_call_iarg_regs[0]);
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
TCG_AREG0);
-#endif
tcg_out_call(s, qemu_ld_helpers[opc & 3]);
switch (opc) {
@@ -1245,7 +1223,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_abort();
}
-#ifdef CONFIG_TCG_PASS_AREG0
/* XXX/FIXME: suboptimal */
tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
tcg_target_call_iarg_regs[2]);
@@ -1255,7 +1232,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_target_call_iarg_regs[0]);
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
TCG_AREG0);
-#endif
tcg_out_call(s, qemu_st_helpers[opc]);
/* label2: */
diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
index d4bf6fe..01ef960 100644
--- a/tcg/hppa/tcg-target.h
+++ b/tcg/hppa/tcg-target.h
@@ -104,7 +104,6 @@ typedef enum {
#define TCG_TARGET_HAS_GUEST_BASE
-/* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_R17
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index da17bba..34c2df8 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -183,9 +183,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_set32(ct->u.regs, 0, 0xffff);
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
-#endif
} else {
tcg_regset_set32(ct->u.regs, 0, 0xff);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
@@ -965,7 +963,6 @@ static void tcg_out_jmp(TCGContext *s, tcg_target_long dest)
#include "../../softmmu_defs.h"
-#ifdef CONFIG_TCG_PASS_AREG0
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
int mmu_idx) */
static const void *qemu_ld_helpers[4] = {
@@ -983,25 +980,6 @@ static const void *qemu_st_helpers[4] = {
helper_stl_mmu,
helper_stq_mmu,
};
-#else
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
- mmu_idx) */
-static void *qemu_ld_helpers[4] = {
- __ldb_mmu,
- __ldw_mmu,
- __ldl_mmu,
- __ldq_mmu,
-};
-
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
- int mmu_idx) */
-static void *qemu_st_helpers[4] = {
- __stb_mmu,
- __stw_mmu,
- __stl_mmu,
- __stq_mmu,
-};
-#endif
/* Perform the TLB load and compare.
@@ -1220,16 +1198,13 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
}
tcg_out_push(s, args[addrlo_idx]);
stack_adjust += 4;
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_out_push(s, TCG_AREG0);
stack_adjust += 4;
-#endif
#else
/* The first argument is already loaded with addrlo. */
arg_idx = 1;
tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[arg_idx],
mem_index);
-#ifdef CONFIG_TCG_PASS_AREG0
/* XXX/FIXME: suboptimal */
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
tcg_target_call_iarg_regs[2]);
@@ -1240,7 +1215,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
TCG_AREG0);
#endif
-#endif
tcg_out_calli(s, (tcg_target_long)qemu_ld_helpers[s_bits]);
@@ -1436,16 +1410,13 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
}
tcg_out_push(s, args[addrlo_idx]);
stack_adjust += 4;
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_out_push(s, TCG_AREG0);
stack_adjust += 4;
-#endif
#else
tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32),
tcg_target_call_iarg_regs[1], data_reg);
tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], mem_index);
stack_adjust = 0;
-#ifdef CONFIG_TCG_PASS_AREG0
/* XXX/FIXME: suboptimal */
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
tcg_target_call_iarg_regs[2]);
@@ -1456,7 +1427,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
TCG_AREG0);
#endif
-#endif
tcg_out_calli(s, (tcg_target_long)qemu_st_helpers[s_bits]);
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index c3cfe05..8be42f3 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -116,7 +116,6 @@ typedef enum {
#define TCG_TARGET_HAS_GUEST_BASE
-/* Note: must be synced with dyngen-exec.h */
#if TCG_TARGET_REG_BITS == 64
# define TCG_AREG0 TCG_REG_R14
#else
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index dc588db..1745038 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -1452,7 +1452,6 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
TCG_REG_P7, TCG_REG_R3, TCG_REG_R57));
}
-#ifdef CONFIG_TCG_PASS_AREG0
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
int mmu_idx) */
static const void * const qemu_ld_helpers[4] = {
@@ -1461,16 +1460,6 @@ static const void * const qemu_ld_helpers[4] = {
helper_ldl_mmu,
helper_ldq_mmu,
};
-#else
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
- mmu_idx) */
-static void *qemu_ld_helpers[4] = {
- __ldb_mmu,
- __ldw_mmu,
- __ldl_mmu,
- __ldq_mmu,
-};
-#endif
static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
{
@@ -1530,7 +1519,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
}
-#ifdef CONFIG_TCG_PASS_AREG0
/* XXX/FIXME: suboptimal */
tcg_out_bundle(s, mII,
tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
@@ -1539,7 +1527,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
TCG_REG_R57, 0, TCG_REG_R56),
tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
TCG_REG_R56, 0, TCG_AREG0));
-#endif
if (!bswap || s_bits == 0) {
tcg_out_bundle(s, miB,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
@@ -1570,7 +1557,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
}
}
-#ifdef CONFIG_TCG_PASS_AREG0
/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
uintxx_t val, int mmu_idx) */
static const void * const qemu_st_helpers[4] = {
@@ -1579,16 +1565,6 @@ static const void * const qemu_st_helpers[4] = {
helper_stl_mmu,
helper_stq_mmu,
};
-#else
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
- int mmu_idx) */
-static void *qemu_st_helpers[4] = {
- __stb_mmu,
- __stw_mmu,
- __stl_mmu,
- __stq_mmu,
-};
-#endif
static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
{
@@ -1658,7 +1634,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
data_reg = TCG_REG_R2;
}
-#ifdef CONFIG_TCG_PASS_AREG0
/* XXX/FIXME: suboptimal */
tcg_out_bundle(s, mII,
tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
@@ -1674,15 +1649,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
TCG_REG_R56, 0, TCG_AREG0),
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
TCG_REG_B0, TCG_REG_B6));
-#else
- tcg_out_bundle(s, miB,
- tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
- data_reg, TCG_REG_R3),
- tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
- mem_index, TCG_REG_R0),
- tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
- TCG_REG_B0, TCG_REG_B6));
-#endif
}
#else /* !CONFIG_SOFTMMU */
diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
index 0631b9f..c22962a 100644
--- a/tcg/ia64/tcg-target.h
+++ b/tcg/ia64/tcg-target.h
@@ -140,7 +140,6 @@ typedef enum {
#define TCG_TARGET_HAS_not_i32 0 /* xor r1, -1, r3 */
#define TCG_TARGET_HAS_not_i64 0 /* xor r1, -1, r3 */
-/* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_R7
/* Guest base is supported */
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 1006e28..74db83d 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -217,7 +217,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_set(ct->u.regs, 0xffffffff);
#if defined(CONFIG_SOFTMMU)
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
-# if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
+# if (TARGET_LONG_BITS == 64)
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
# endif
#endif
@@ -227,12 +227,11 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_set(ct->u.regs, 0xffffffff);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
-# if (defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 32) || \
- (!defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 64)
+# if (TARGET_LONG_BITS == 32)
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
# endif
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
-# if defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 64
+# if TARGET_LONG_BITS == 64
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
# endif
#endif
@@ -821,7 +820,6 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond cond, int ret,
#include "../../softmmu_defs.h"
-#ifdef CONFIG_TCG_PASS_AREG0
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
int mmu_idx) */
static const void * const qemu_ld_helpers[4] = {
@@ -839,25 +837,6 @@ static const void * const qemu_st_helpers[4] = {
helper_stl_mmu,
helper_stq_mmu,
};
-#else
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
- mmu_idx) */
-static void *qemu_ld_helpers[4] = {
- __ldb_mmu,
- __ldw_mmu,
- __ldl_mmu,
- __ldq_mmu,
-};
-
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
- int mmu_idx) */
-static void *qemu_st_helpers[4] = {
- __stb_mmu,
- __stw_mmu,
- __stl_mmu,
- __stq_mmu,
-};
-#endif
#endif
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
@@ -942,9 +921,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
/* slow path */
arg_num = 0;
-# ifdef CONFIG_TCG_PASS_AREG0
tcg_out_call_iarg_reg32(s, &arg_num, TCG_AREG0);
-# endif
# if TARGET_LONG_BITS == 64
tcg_out_call_iarg_reg64(s, &arg_num, addr_regl, addr_regh);
# else
@@ -1127,9 +1104,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
/* slow path */
arg_num = 0;
-# ifdef CONFIG_TCG_PASS_AREG0
tcg_out_call_iarg_reg32(s, &arg_num, TCG_AREG0);
-# endif
# if TARGET_LONG_BITS == 64
tcg_out_call_iarg_reg64(s, &arg_num, addr_regl, addr_regh);
# else
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index d3c804d..1c61931 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -96,7 +96,6 @@ typedef enum {
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
-/* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_S0
/* guest base is supported */
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 0cff181..26c4b33 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -248,7 +248,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
#if TARGET_LONG_BITS == 64
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
@@ -256,11 +255,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
#endif
#endif
-#else /* !AREG0 */
-#if TARGET_LONG_BITS == 64
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
-#endif
-#endif
break;
case 'K': /* qemu_st[8..32] constraint */
ct->ct |= TCG_CT_REG;
@@ -268,7 +262,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
#if TARGET_LONG_BITS == 64
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
@@ -276,11 +269,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
#endif
#endif
-#else /* !AREG0 */
-#if TARGET_LONG_BITS == 64
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
-#endif
-#endif
break;
case 'M': /* qemu_st64 constraint */
ct->ct |= TCG_CT_REG;
@@ -290,12 +278,10 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
-#if defined(CONFIG_TCG_PASS_AREG0)
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
#ifdef TCG_TARGET_CALL_ALIGN_ARGS
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9);
#endif
-#endif
break;
#else
case 'L':
@@ -541,7 +527,6 @@ static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
#include "../../softmmu_defs.h"
-#ifdef CONFIG_TCG_PASS_AREG0
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
int mmu_idx) */
static const void * const qemu_ld_helpers[4] = {
@@ -559,25 +544,6 @@ static const void * const qemu_st_helpers[4] = {
helper_stl_mmu,
helper_stq_mmu,
};
-#else
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
- mmu_idx) */
-static void *qemu_ld_helpers[4] = {
- __ldb_mmu,
- __ldw_mmu,
- __ldl_mmu,
- __ldq_mmu,
-};
-
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
- mmu_idx) */
-static void *qemu_st_helpers[4] = {
- __stb_mmu,
- __stw_mmu,
- __stl_mmu,
- __stq_mmu,
-};
-#endif
#endif
static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
@@ -647,9 +613,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
/* slow path */
ir = 3;
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
-#endif
#if TARGET_LONG_BITS == 32
tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
#else
@@ -849,9 +813,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
/* slow path */
ir = 3;
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
-#endif
#if TARGET_LONG_BITS == 32
tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
#else
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 27a0ae8..337cd41 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -235,10 +235,8 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
#endif
-#endif
break;
case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG;
@@ -247,10 +245,8 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
#ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6);
#endif
-#endif
break;
case 'Z':
ct->ct |= TCG_CT_CONST_U32;
@@ -558,7 +554,6 @@ static void tcg_out_ldsta (TCGContext *s, int ret, int addr,
#include "../../softmmu_defs.h"
-#ifdef CONFIG_TCG_PASS_AREG0
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
int mmu_idx) */
static const void * const qemu_ld_helpers[4] = {
@@ -576,25 +571,6 @@ static const void * const qemu_st_helpers[4] = {
helper_stl_mmu,
helper_stq_mmu,
};
-#else
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
- mmu_idx) */
-static void *qemu_ld_helpers[4] = {
- __ldb_mmu,
- __ldw_mmu,
- __ldl_mmu,
- __ldq_mmu,
-};
-
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
- int mmu_idx) */
-static void *qemu_st_helpers[4] = {
- __stb_mmu,
- __stw_mmu,
- __stl_mmu,
- __stq_mmu,
-};
-#endif
static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
int addr_reg, int s_bits, int offset)
@@ -676,9 +652,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
/* slow path */
ir = 3;
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
-#endif
tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
@@ -827,9 +801,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
/* slow path */
ir = 3;
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
-#endif
tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
tcg_out_rld (s, RLDICL, ir++, data_reg, 0, 64 - (1 << (3 + opc)));
tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 04662c1..965e1d4 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -301,7 +301,6 @@ static const uint8_t tcg_cond_to_ltr_cond[10] = {
#include "../../softmmu_defs.h"
-#ifdef CONFIG_TCG_PASS_AREG0
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
int mmu_idx) */
static const void * const qemu_ld_helpers[4] = {
@@ -319,25 +318,6 @@ static const void * const qemu_st_helpers[4] = {
helper_stl_mmu,
helper_stq_mmu,
};
-#else
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
- mmu_idx) */
-static void *qemu_ld_helpers[4] = {
- __ldb_mmu,
- __ldw_mmu,
- __ldl_mmu,
- __ldq_mmu,
-};
-
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
- int mmu_idx) */
-static void *qemu_st_helpers[4] = {
- __stb_mmu,
- __stw_mmu,
- __stl_mmu,
- __stq_mmu,
-};
-#endif
#endif
static uint8_t *tb_ret_addr;
@@ -1507,7 +1487,6 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
tcg_abort();
}
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, mem_index);
-#ifdef CONFIG_TCG_PASS_AREG0
/* XXX/FIXME: suboptimal */
tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2],
tcg_target_call_iarg_regs[1]);
@@ -1515,11 +1494,9 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
tcg_target_call_iarg_regs[0]);
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
TCG_AREG0);
-#endif
tgen_calli(s, (tcg_target_ulong)qemu_st_helpers[s_bits]);
} else {
tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
-#ifdef CONFIG_TCG_PASS_AREG0
/* XXX/FIXME: suboptimal */
tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
tcg_target_call_iarg_regs[2]);
@@ -1529,7 +1506,6 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
tcg_target_call_iarg_regs[0]);
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
TCG_AREG0);
-#endif
tgen_calli(s, (tcg_target_ulong)qemu_ld_helpers[s_bits]);
/* sign extension */
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index d12f90b..4f7dfab 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -96,7 +96,6 @@ typedef enum TCGReg {
#define TCG_TARGET_EXTEND_ARGS 1
enum {
- /* Note: must be synced with dyngen-exec.h */
TCG_AREG0 = TCG_REG_R10,
};
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 247a278..baed3b4 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -59,11 +59,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
};
#endif
-#ifdef CONFIG_TCG_PASS_AREG0
#define ARG_OFFSET 1
-#else
-#define ARG_OFFSET 0
-#endif
static const int tcg_target_reg_alloc_order[] = {
TCG_REG_L0,
@@ -161,9 +157,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O3);
-#endif
break;
case 'I':
ct->ct |= TCG_CT_CONST_S11;
@@ -715,7 +709,6 @@ static void tcg_target_qemu_prologue(TCGContext *s)
#include "../../softmmu_defs.h"
-#ifdef CONFIG_TCG_PASS_AREG0
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
int mmu_idx) */
static const void * const qemu_ld_helpers[4] = {
@@ -733,25 +726,6 @@ static const void * const qemu_st_helpers[4] = {
helper_stl_mmu,
helper_stq_mmu,
};
-#else
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
- mmu_idx) */
-static const void * const qemu_ld_helpers[4] = {
- __ldb_mmu,
- __ldw_mmu,
- __ldl_mmu,
- __ldq_mmu,
-};
-
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
- int mmu_idx) */
-static const void * const qemu_st_helpers[4] = {
- __stb_mmu,
- __stw_mmu,
- __stl_mmu,
- __stq_mmu,
-};
-#endif
#endif
#if TARGET_LONG_BITS == 32
@@ -834,7 +808,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
/* mov */
tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
-#ifdef CONFIG_TCG_PASS_AREG0
/* XXX/FIXME: suboptimal */
tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
tcg_target_call_iarg_regs[2]);
@@ -844,7 +817,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
tcg_target_call_iarg_regs[0]);
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
TCG_AREG0);
-#endif
/* XXX: move that code at the end of the TB */
/* qemu_ld_helper[s_bits](arg0, arg1) */
@@ -1061,7 +1033,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
/* mov */
tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
-#ifdef CONFIG_TCG_PASS_AREG0
/* XXX/FIXME: suboptimal */
tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
tcg_target_call_iarg_regs[2]);
@@ -1071,7 +1042,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
tcg_target_call_iarg_regs[0]);
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
TCG_AREG0);
-#endif
/* XXX: move that code at the end of the TB */
/* qemu_st_helper[s_bits](arg0, arg1, arg2) */
tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index ee2274d..0ea87be 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -125,7 +125,6 @@ typedef enum {
#define TCG_TARGET_HAS_deposit_i64 0
#endif
-/* Note: must be synced with dyngen-exec.h */
#ifdef CONFIG_SOLARIS
#define TCG_AREG0 TCG_REG_G2
#elif defined(__sparc_v9__)
diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c
index ef8580f..003244c 100644
--- a/tcg/tci/tcg-target.c
+++ b/tcg/tci/tcg-target.c
@@ -798,9 +798,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_qemu_st8:
case INDEX_op_qemu_st16:
case INDEX_op_qemu_st32:
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_out_r(s, TCG_AREG0);
-#endif
tcg_out_r(s, *args++);
tcg_out_r(s, *args++);
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
@@ -811,9 +809,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
#endif
break;
case INDEX_op_qemu_st64:
-#ifdef CONFIG_TCG_PASS_AREG0
tcg_out_r(s, TCG_AREG0);
-#endif
tcg_out_r(s, *args++);
#if TCG_TARGET_REG_BITS == 32
tcg_out_r(s, *args++);
diff --git a/tci.c b/tci.c
index c79350d..ce8a988 100644
--- a/tci.c
+++ b/tci.c
@@ -25,7 +25,6 @@
#endif
#include "qemu-common.h"
-#include "dyngen-exec.h" /* env */
#include "exec-all.h" /* MAX_OPC_PARAM_IARGS */
#include "tcg-op.h"
@@ -63,17 +62,6 @@ uintptr_t tci_tb_ptr;
static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
-#if !defined(CONFIG_TCG_PASS_AREG0)
-# define helper_ldb_mmu(env, addr, mmu_idx) __ldb_mmu(addr, mmu_idx)
-# define helper_ldw_mmu(env, addr, mmu_idx) __ldw_mmu(addr, mmu_idx)
-# define helper_ldl_mmu(env, addr, mmu_idx) __ldl_mmu(addr, mmu_idx)
-# define helper_ldq_mmu(env, addr, mmu_idx) __ldq_mmu(addr, mmu_idx)
-# define helper_stb_mmu(env, addr, val, mmu_idx) __stb_mmu(addr, val, mmu_idx)
-# define helper_stw_mmu(env, addr, val, mmu_idx) __stw_mmu(addr, val, mmu_idx)
-# define helper_stl_mmu(env, addr, val, mmu_idx) __stl_mmu(addr, val, mmu_idx)
-# define helper_stq_mmu(env, addr, val, mmu_idx) __stq_mmu(addr, val, mmu_idx)
-#endif /* !CONFIG_TCG_PASS_AREG0 */
-
static tcg_target_ulong tci_read_reg(TCGReg index)
{
assert(index < ARRAY_SIZE(tci_reg));
diff --git a/user-exec.c b/user-exec.c
index b9ea9dd..ef9b172 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -18,9 +18,6 @@
*/
#include "config.h"
#include "cpu.h"
-#ifndef CONFIG_TCG_PASS_AREG0
-#include "dyngen-exec.h"
-#endif
#include "disas.h"
#include "tcg.h"
@@ -60,12 +57,6 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc)
struct sigcontext *uc = puc;
#endif
-#ifndef CONFIG_TCG_PASS_AREG0
- env = env1;
-
- /* XXX: restore cpu registers saved in host registers */
-#endif
-
if (puc) {
/* XXX: use siglongjmp ? */
#ifdef __linux__
@@ -93,11 +84,6 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
TranslationBlock *tb;
int ret;
-#ifndef CONFIG_TCG_PASS_AREG0
- if (cpu_single_env) {
- env = cpu_single_env; /* XXX: find a correct solution for multithread */
- }
-#endif
#if defined(DEBUG_SIGNAL)
qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
pc, address, is_write, *(unsigned long *)old_set);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 21/21] Remove unused CONFIG_TCG_PASS_AREG0 and dead code
2012-09-02 17:33 ` [Qemu-devel] [PATCH 21/21] Remove unused CONFIG_TCG_PASS_AREG0 and dead code Blue Swirl
@ 2012-09-06 15:30 ` Aurelien Jarno
2012-09-08 7:21 ` Blue Swirl
0 siblings, 1 reply; 64+ messages in thread
From: Aurelien Jarno @ 2012-09-06 15:30 UTC (permalink / raw)
To: Blue Swirl
Cc: Stefan Weil, Paul Brook, Richard Henderson, qemu-devel,
Alexander Graf
On Sun, Sep 02, 2012 at 05:33:50PM +0000, Blue Swirl wrote:
> Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,
> remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.
>
> Remove dyngen-exec.h and all references to it. Although included by
> hw/spapr_hcall.c, it does not seem to use it.
>
> Remove unused HELPER_CFLAGS.
>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> ---
> Makefile.target | 8 -----
> configure | 11 -------
> cpu-all.h | 11 -------
> cputlb.c | 4 --
> dyngen-exec.h | 70 ------------------------------------------
> exec-all.h | 4 --
> hw/spapr_hcall.c | 1 -
> softmmu_defs.h | 21 -------------
> softmmu_header.h | 63 ++++++++++++--------------------------
> softmmu_template.h | 72 ++++++++++++++++---------------------------
> target-m68k/op_helper.c | 3 --
> target-sparc/Makefile.objs | 2 -
> tcg/arm/tcg-target.c | 31 ++-----------------
> tcg/arm/tcg-target.h | 1 -
> tcg/hppa/tcg-target.c | 24 --------------
> tcg/hppa/tcg-target.h | 1 -
> tcg/i386/tcg-target.c | 30 ------------------
> tcg/i386/tcg-target.h | 1 -
> tcg/ia64/tcg-target.c | 34 --------------------
> tcg/ia64/tcg-target.h | 1 -
> tcg/mips/tcg-target.c | 31 ++-----------------
> tcg/mips/tcg-target.h | 1 -
> tcg/ppc/tcg-target.c | 38 -----------------------
> tcg/ppc64/tcg-target.c | 28 -----------------
> tcg/s390/tcg-target.c | 24 --------------
> tcg/s390/tcg-target.h | 1 -
> tcg/sparc/tcg-target.c | 30 ------------------
> tcg/sparc/tcg-target.h | 1 -
> tcg/tci/tcg-target.c | 4 --
> tci.c | 12 -------
> user-exec.c | 14 --------
> 31 files changed, 53 insertions(+), 524 deletions(-)
> delete mode 100644 dyngen-exec.h
>
> diff --git a/Makefile.target b/Makefile.target
> index 7892a8d..d9d54b8 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -80,14 +80,6 @@ obj-$(CONFIG_GDBSTUB_XML) += gdbstub-xml.o
>
> tci-dis.o: QEMU_CFLAGS += -I$(SRC_PATH)/tcg -I$(SRC_PATH)/tcg/tci
>
> -# HELPER_CFLAGS is used for all the legacy code compiled with static register
> -# variables
> -user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> -
> -# Note: this is a workaround. The real fix is to avoid compiling
> -# cpu_signal_handler() in user-exec.c.
> -%/signal.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> -
> #########################################################
> # Linux user emulator target
>
> diff --git a/configure b/configure
> index f60a4b6..e7d333b 100755
> --- a/configure
> +++ b/configure
> @@ -118,7 +118,6 @@ audio_card_list="ac97 es1370 sb16 hda"
> audio_possible_cards="ac97 es1370 sb16 cs4231a adlib gus hda"
> block_drv_whitelist=""
> host_cc="gcc"
> -helper_cflags=""
> libs_softmmu=""
> libs_tools=""
> audio_pt_int=""
> @@ -894,7 +893,6 @@ case "$cpu" in
> QEMU_CFLAGS="-m32 -ffixed-g2 -ffixed-g3 $QEMU_CFLAGS"
> if test "$solaris" = "no" ; then
> QEMU_CFLAGS="-ffixed-g1 -ffixed-g6 $QEMU_CFLAGS"
> - helper_cflags="-ffixed-i0"
> fi
> ;;
> sparc64)
> @@ -919,7 +917,6 @@ case "$cpu" in
> QEMU_CFLAGS="-m32 $QEMU_CFLAGS"
> LDFLAGS="-m32 $LDFLAGS"
> cc_i386='$(CC) -m32'
> - helper_cflags="-fomit-frame-pointer"
> host_guest_base="yes"
> ;;
> x86_64)
> @@ -3572,7 +3569,6 @@ if test "$sparse" = "yes" ; then
> echo "HOST_CC := REAL_CC=\"\$(HOST_CC)\" cgcc" >> $config_host_mak
> echo "QEMU_CFLAGS += -Wbitwise -Wno-transparent-union -Wno-old-initializer -Wno-non-pointer-null" >> $config_host_mak
> fi
> -echo "HELPER_CFLAGS=$helper_cflags" >> $config_host_mak
> echo "LDFLAGS=$LDFLAGS" >> $config_host_mak
> echo "ARLIBS_BEGIN=$arlibs_begin" >> $config_host_mak
> echo "ARLIBS_END=$arlibs_end" >> $config_host_mak
> @@ -3827,13 +3823,6 @@ fi
>
> symlink "$source_path/Makefile.target" "$target_dir/Makefile"
>
> -
> -case "$target_arch2" in
> - alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | mips* | or32 | s390x | sh4* | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> - echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
> - ;;
> -esac
> -
> upper() {
> echo "$@"| LC_ALL=C tr '[a-z]' '[A-Z]'
> }
> diff --git a/cpu-all.h b/cpu-all.h
> index 5e07d28..74d3681 100644
> --- a/cpu-all.h
> +++ b/cpu-all.h
> @@ -260,14 +260,6 @@ extern unsigned long reserved_va;
> #define stfl(p, v) stfl_raw(p, v)
> #define stfq(p, v) stfq_raw(p, v)
>
> -#ifndef CONFIG_TCG_PASS_AREG0
> -#define ldub_code(p) ldub_raw(p)
> -#define ldsb_code(p) ldsb_raw(p)
> -#define lduw_code(p) lduw_raw(p)
> -#define ldsw_code(p) ldsw_raw(p)
> -#define ldl_code(p) ldl_raw(p)
> -#define ldq_code(p) ldq_raw(p)
> -#else
> #define cpu_ldub_code(env1, p) ldub_raw(p)
> #define cpu_ldsb_code(env1, p) ldsb_raw(p)
> #define cpu_lduw_code(env1, p) lduw_raw(p)
> @@ -296,7 +288,6 @@ extern unsigned long reserved_va;
> #define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
> #define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
> #define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)
> -#endif
>
> #define ldub_kernel(p) ldub_raw(p)
> #define ldsb_kernel(p) ldsb_raw(p)
> @@ -313,7 +304,6 @@ extern unsigned long reserved_va;
> #define stfl_kernel(p, v) stfl_raw(p, v)
> #define stfq_kernel(p, vt) stfq_raw(p, v)
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> #define cpu_ldub_data(env, addr) ldub_raw(addr)
> #define cpu_lduw_data(env, addr) lduw_raw(addr)
> #define cpu_ldl_data(env, addr) ldl_raw(addr)
> @@ -321,7 +311,6 @@ extern unsigned long reserved_va;
> #define cpu_stb_data(env, addr, data) stb_raw(addr, data)
> #define cpu_stw_data(env, addr, data) stw_raw(addr, data)
> #define cpu_stl_data(env, addr, data) stl_raw(addr, data)
> -#endif
> #endif /* defined(CONFIG_USER_ONLY) */
>
> /* page related stuff */
> diff --git a/cputlb.c b/cputlb.c
> index d3e7b25..8468517 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -325,11 +325,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
> mmu_idx = cpu_mmu_index(env1);
> if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
> (addr & TARGET_PAGE_MASK))) {
> -#ifdef CONFIG_TCG_PASS_AREG0
> cpu_ldub_code(env1, addr);
> -#else
> - ldub_code(addr);
> -#endif
> }
> pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
> mr = iotlb_to_region(pd);
> diff --git a/dyngen-exec.h b/dyngen-exec.h
> deleted file mode 100644
> index 083e20b..0000000
> --- a/dyngen-exec.h
> +++ /dev/null
> @@ -1,70 +0,0 @@
> -/*
> - * dyngen defines for micro operation code
> - *
> - * Copyright (c) 2003 Fabrice Bellard
> - *
> - * This library is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU Lesser General Public
> - * License as published by the Free Software Foundation; either
> - * version 2 of the License, or (at your option) any later version.
> - *
> - * This library is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> - * Lesser General Public License for more details.
> - *
> - * You should have received a copy of the GNU Lesser General Public
> - * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> - */
> -#if !defined(__DYNGEN_EXEC_H__)
> -#define __DYNGEN_EXEC_H__
> -
> -#if defined(CONFIG_TCG_INTERPRETER)
> -/* The TCG interpreter does not need a special register AREG0,
> - * but it is possible to use one by defining AREG0.
> - * On i386, register edi seems to work. */
> -/* Run without special register AREG0 or use a value defined elsewhere. */
> -#elif defined(__i386__)
> -#define AREG0 "ebp"
> -#elif defined(__x86_64__)
> -#define AREG0 "r14"
> -#elif defined(_ARCH_PPC)
> -#define AREG0 "r27"
> -#elif defined(__arm__)
> -#define AREG0 "r6"
> -#elif defined(__hppa__)
> -#define AREG0 "r17"
> -#elif defined(__mips__)
> -#define AREG0 "s0"
> -#elif defined(__sparc__)
> -#ifdef CONFIG_SOLARIS
> -#define AREG0 "g2"
> -#else
> -#ifdef __sparc_v9__
> -#define AREG0 "g5"
> -#else
> -#define AREG0 "g6"
> -#endif
> -#endif
> -#elif defined(__s390__)
> -#define AREG0 "r10"
> -#elif defined(__alpha__)
> -/* Note $15 is the frame pointer, so anything in op-i386.c that would
> - require a frame pointer, like alloca, would probably loose. */
> -#define AREG0 "$15"
> -#elif defined(__mc68000)
> -#define AREG0 "%a5"
> -#elif defined(__ia64__)
> -#define AREG0 "r7"
> -#else
> -#error unsupported CPU
> -#endif
> -
> -#if defined(AREG0)
> -register CPUArchState *env asm(AREG0);
> -#else
> -/* TODO: Try env = cpu_single_env. */
> -extern CPUArchState *env;
> -#endif
> -
> -#endif /* !defined(__DYNGEN_EXEC_H__) */
> diff --git a/exec-all.h b/exec-all.h
> index c5ec8e1..c5d3a13 100644
> --- a/exec-all.h
> +++ b/exec-all.h
> @@ -323,9 +323,6 @@ void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
>
> #define ACCESS_TYPE (NB_MMU_MODES + 1)
> #define MEMSUFFIX _code
> -#ifndef CONFIG_TCG_PASS_AREG0
> -#define env cpu_single_env
> -#endif
>
> #define DATA_SIZE 1
> #include "softmmu_header.h"
> @@ -341,7 +338,6 @@ void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
>
> #undef ACCESS_TYPE
> #undef MEMSUFFIX
> -#undef env
>
> #endif
>
> diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c
> index a5990a9..abd847f 100644
> --- a/hw/spapr_hcall.c
> +++ b/hw/spapr_hcall.c
> @@ -1,6 +1,5 @@
> #include "sysemu.h"
> #include "cpu.h"
> -#include "dyngen-exec.h"
> #include "qemu-char.h"
> #include "sysemu.h"
> #include "qemu-char.h"
> diff --git a/softmmu_defs.h b/softmmu_defs.h
> index 8d59f9d..1f25e33 100644
> --- a/softmmu_defs.h
> +++ b/softmmu_defs.h
> @@ -9,25 +9,6 @@
> #ifndef SOFTMMU_DEFS_H
> #define SOFTMMU_DEFS_H
>
> -#ifndef CONFIG_TCG_PASS_AREG0
> -uint8_t __ldb_mmu(target_ulong addr, int mmu_idx);
> -void __stb_mmu(target_ulong addr, uint8_t val, int mmu_idx);
> -uint16_t __ldw_mmu(target_ulong addr, int mmu_idx);
> -void __stw_mmu(target_ulong addr, uint16_t val, int mmu_idx);
> -uint32_t __ldl_mmu(target_ulong addr, int mmu_idx);
> -void __stl_mmu(target_ulong addr, uint32_t val, int mmu_idx);
> -uint64_t __ldq_mmu(target_ulong addr, int mmu_idx);
> -void __stq_mmu(target_ulong addr, uint64_t val, int mmu_idx);
> -
> -uint8_t __ldb_cmmu(target_ulong addr, int mmu_idx);
> -void __stb_cmmu(target_ulong addr, uint8_t val, int mmu_idx);
> -uint16_t __ldw_cmmu(target_ulong addr, int mmu_idx);
> -void __stw_cmmu(target_ulong addr, uint16_t val, int mmu_idx);
> -uint32_t __ldl_cmmu(target_ulong addr, int mmu_idx);
> -void __stl_cmmu(target_ulong addr, uint32_t val, int mmu_idx);
> -uint64_t __ldq_cmmu(target_ulong addr, int mmu_idx);
> -void __stq_cmmu(target_ulong addr, uint64_t val, int mmu_idx);
> -#else
> uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
> void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
> int mmu_idx);
> @@ -54,5 +35,3 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
> void helper_stq_cmmu(CPUArchState *env, target_ulong addr, uint64_t val,
> int mmu_idx);
> #endif
> -
> -#endif
> diff --git a/softmmu_header.h b/softmmu_header.h
> index cf1aa38..d8d9c81 100644
> --- a/softmmu_header.h
> +++ b/softmmu_header.h
> @@ -78,23 +78,10 @@
> #define ADDR_READ addr_read
> #endif
>
> -#ifndef CONFIG_TCG_PASS_AREG0
> -#define ENV_PARAM
> -#define ENV_VAR
> -#define CPU_PREFIX
> -#define HELPER_PREFIX __
> -#else
> -#define ENV_PARAM CPUArchState *env,
> -#define ENV_VAR env,
> -#define CPU_PREFIX cpu_
> -#define HELPER_PREFIX helper_
> -#endif
> -
> /* generic load/store macros */
>
> static inline RES_TYPE
> -glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
> - target_ulong ptr)
> +glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
> {
> int page_index;
> RES_TYPE res;
> @@ -106,9 +93,7 @@ glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
> mmu_idx = CPU_MMU_INDEX;
> if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
> (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
> - res = glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_VAR
> - addr,
> - mmu_idx);
> + res = glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx);
> } else {
> uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
> res = glue(glue(ld, USUFFIX), _raw)(hostaddr);
> @@ -118,8 +103,7 @@ glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
>
> #if DATA_SIZE <= 2
> static inline int
> -glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
> - target_ulong ptr)
> +glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
> {
> int res, page_index;
> target_ulong addr;
> @@ -130,8 +114,8 @@ glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
> mmu_idx = CPU_MMU_INDEX;
> if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
> (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
> - res = (DATA_STYPE)glue(glue(glue(HELPER_PREFIX, ld), SUFFIX),
> - MMUSUFFIX)(ENV_VAR addr, mmu_idx);
> + res = (DATA_STYPE)glue(glue(helper_ld, SUFFIX),
> + MMUSUFFIX)(env, addr, mmu_idx);
> } else {
> uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
> res = glue(glue(lds, SUFFIX), _raw)(hostaddr);
> @@ -145,8 +129,8 @@ glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
> /* generic store macro */
>
> static inline void
> -glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
> - RES_TYPE v)
> +glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
> + RES_TYPE v)
> {
> int page_index;
> target_ulong addr;
> @@ -157,8 +141,7 @@ glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
> mmu_idx = CPU_MMU_INDEX;
> if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
> (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
> - glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_VAR addr, v,
> - mmu_idx);
> + glue(glue(helper_st, SUFFIX), MMUSUFFIX)(env, addr, v, mmu_idx);
> } else {
> uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
> glue(glue(st, SUFFIX), _raw)(hostaddr, v);
> @@ -170,52 +153,50 @@ glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
> #if ACCESS_TYPE != (NB_MMU_MODES + 1)
>
> #if DATA_SIZE == 8
> -static inline float64 glue(glue(CPU_PREFIX, ldfq), MEMSUFFIX)(ENV_PARAM
> - target_ulong ptr)
> +static inline float64 glue(cpu_ldfq, MEMSUFFIX)(CPUArchState *env,
> + target_ulong ptr)
> {
> union {
> float64 d;
> uint64_t i;
> } u;
> - u.i = glue(glue(CPU_PREFIX, ldq), MEMSUFFIX)(ENV_VAR ptr);
> + u.i = glue(cpu_ldq, MEMSUFFIX)(env, ptr);
> return u.d;
> }
>
> -static inline void glue(glue(CPU_PREFIX, stfq), MEMSUFFIX)(ENV_PARAM
> - target_ulong ptr,
> - float64 v)
> +static inline void glue(cpu_stfq, MEMSUFFIX)(CPUArchState *env,
> + target_ulong ptr, float64 v)
> {
> union {
> float64 d;
> uint64_t i;
> } u;
> u.d = v;
> - glue(glue(CPU_PREFIX, stq), MEMSUFFIX)(ENV_VAR ptr, u.i);
> + glue(cpu_stq, MEMSUFFIX)(env, ptr, u.i);
> }
> #endif /* DATA_SIZE == 8 */
>
> #if DATA_SIZE == 4
> -static inline float32 glue(glue(CPU_PREFIX, ldfl), MEMSUFFIX)(ENV_PARAM
> - target_ulong ptr)
> +static inline float32 glue(cpu_ldfl, MEMSUFFIX)(CPUArchState *env,
> + target_ulong ptr)
> {
> union {
> float32 f;
> uint32_t i;
> } u;
> - u.i = glue(glue(CPU_PREFIX, ldl), MEMSUFFIX)(ENV_VAR ptr);
> + u.i = glue(cpu_ldl, MEMSUFFIX)(env, ptr);
> return u.f;
> }
>
> -static inline void glue(glue(CPU_PREFIX, stfl), MEMSUFFIX)(ENV_PARAM
> - target_ulong ptr,
> - float32 v)
> +static inline void glue(cpu_stfl, MEMSUFFIX)(CPUArchState *env,
> + target_ulong ptr, float32 v)
> {
> union {
> float32 f;
> uint32_t i;
> } u;
> u.f = v;
> - glue(glue(CPU_PREFIX, stl), MEMSUFFIX)(ENV_VAR ptr, u.i);
> + glue(cpu_stl, MEMSUFFIX)(env, ptr, u.i);
> }
> #endif /* DATA_SIZE == 4 */
>
> @@ -230,7 +211,3 @@ static inline void glue(glue(CPU_PREFIX, stfl), MEMSUFFIX)(ENV_PARAM
> #undef CPU_MMU_INDEX
> #undef MMUSUFFIX
> #undef ADDR_READ
> -#undef ENV_PARAM
> -#undef ENV_VAR
> -#undef CPU_PREFIX
> -#undef HELPER_PREFIX
> diff --git a/softmmu_template.h b/softmmu_template.h
> index b8bd700..e2490f0 100644
> --- a/softmmu_template.h
> +++ b/softmmu_template.h
> @@ -54,23 +54,11 @@
> #define ADDR_READ addr_read
> #endif
>
> -#ifndef CONFIG_TCG_PASS_AREG0
> -#define ENV_PARAM
> -#define ENV_VAR
> -#define CPU_PREFIX
> -#define HELPER_PREFIX __
> -#else
> -#define ENV_PARAM CPUArchState *env,
> -#define ENV_VAR env,
> -#define CPU_PREFIX cpu_
> -#define HELPER_PREFIX helper_
> -#endif
> -
> -static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
> +static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
> target_ulong addr,
> int mmu_idx,
> uintptr_t retaddr);
> -static inline DATA_TYPE glue(io_read, SUFFIX)(ENV_PARAM
> +static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
> target_phys_addr_t physaddr,
> target_ulong addr,
> uintptr_t retaddr)
> @@ -104,9 +92,8 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(ENV_PARAM
>
> /* handle all cases except unaligned access which span two pages */
> DATA_TYPE
> -glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
> - target_ulong addr,
> - int mmu_idx)
> +glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
> + int mmu_idx)
> {
> DATA_TYPE res;
> int index;
> @@ -126,15 +113,15 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
> goto do_unaligned_access;
> retaddr = GETPC();
> ioaddr = env->iotlb[mmu_idx][index];
> - res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
> + res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
> } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
> /* slow unaligned access (it spans two pages or IO) */
> do_unaligned_access:
> retaddr = GETPC();
> #ifdef ALIGNED_ONLY
> - do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
> + do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
> #endif
> - res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr,
> + res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr,
> mmu_idx, retaddr);
> } else {
> /* unaligned/aligned access in the same page */
> @@ -142,7 +129,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
> #ifdef ALIGNED_ONLY
> if ((addr & (DATA_SIZE - 1)) != 0) {
> retaddr = GETPC();
> - do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
> + do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
> }
> #endif
> addend = env->tlb_table[mmu_idx][index].addend;
> @@ -154,7 +141,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
> retaddr = GETPC();
> #ifdef ALIGNED_ONLY
> if ((addr & (DATA_SIZE - 1)) != 0)
> - do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
> + do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
> #endif
> tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
> goto redo;
> @@ -164,7 +151,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
>
> /* handle all unaligned cases */
> static DATA_TYPE
> -glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
> +glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
> target_ulong addr,
> int mmu_idx,
> uintptr_t retaddr)
> @@ -183,15 +170,15 @@ glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
> if ((addr & (DATA_SIZE - 1)) != 0)
> goto do_unaligned_access;
> ioaddr = env->iotlb[mmu_idx][index];
> - res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
> + res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
> } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
> do_unaligned_access:
> /* slow unaligned access (it spans two pages) */
> addr1 = addr & ~(DATA_SIZE - 1);
> addr2 = addr1 + DATA_SIZE;
> - res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr1,
> + res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr1,
> mmu_idx, retaddr);
> - res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr2,
> + res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr2,
> mmu_idx, retaddr);
> shift = (addr & (DATA_SIZE - 1)) * 8;
> #ifdef TARGET_WORDS_BIGENDIAN
> @@ -216,13 +203,13 @@ glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
>
> #ifndef SOFTMMU_CODE_ACCESS
>
> -static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
> +static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
> target_ulong addr,
> DATA_TYPE val,
> int mmu_idx,
> uintptr_t retaddr);
>
> -static inline void glue(io_write, SUFFIX)(ENV_PARAM
> +static inline void glue(io_write, SUFFIX)(CPUArchState *env,
> target_phys_addr_t physaddr,
> DATA_TYPE val,
> target_ulong addr,
> @@ -253,10 +240,9 @@ static inline void glue(io_write, SUFFIX)(ENV_PARAM
> #endif /* SHIFT > 2 */
> }
>
> -void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
> - target_ulong addr,
> - DATA_TYPE val,
> - int mmu_idx)
> +void glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
> + target_ulong addr, DATA_TYPE val,
> + int mmu_idx)
> {
> target_phys_addr_t ioaddr;
> target_ulong tlb_addr;
> @@ -273,14 +259,14 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
> goto do_unaligned_access;
> retaddr = GETPC();
> ioaddr = env->iotlb[mmu_idx][index];
> - glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
> + glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
> } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
> do_unaligned_access:
> retaddr = GETPC();
> #ifdef ALIGNED_ONLY
> - do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
> + do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
> #endif
> - glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_VAR addr, val,
> + glue(glue(slow_st, SUFFIX), MMUSUFFIX)(env, addr, val,
> mmu_idx, retaddr);
> } else {
> /* aligned/unaligned access in the same page */
> @@ -288,7 +274,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
> #ifdef ALIGNED_ONLY
> if ((addr & (DATA_SIZE - 1)) != 0) {
> retaddr = GETPC();
> - do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
> + do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
> }
> #endif
> addend = env->tlb_table[mmu_idx][index].addend;
> @@ -300,7 +286,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
> retaddr = GETPC();
> #ifdef ALIGNED_ONLY
> if ((addr & (DATA_SIZE - 1)) != 0)
> - do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
> + do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
> #endif
> tlb_fill(env, addr, 1, mmu_idx, retaddr);
> goto redo;
> @@ -308,7 +294,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
> }
>
> /* handles all unaligned cases */
> -static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
> +static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
> target_ulong addr,
> DATA_TYPE val,
> int mmu_idx,
> @@ -327,7 +313,7 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
> if ((addr & (DATA_SIZE - 1)) != 0)
> goto do_unaligned_access;
> ioaddr = env->iotlb[mmu_idx][index];
> - glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
> + glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
> } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
> do_unaligned_access:
> /* XXX: not efficient, but simple */
> @@ -335,11 +321,11 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
> * previous page from the TLB cache. */
> for(i = DATA_SIZE - 1; i >= 0; i--) {
> #ifdef TARGET_WORDS_BIGENDIAN
> - glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
> + glue(slow_stb, MMUSUFFIX)(env, addr + i,
> val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
> mmu_idx, retaddr);
> #else
> - glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
> + glue(slow_stb, MMUSUFFIX)(env, addr + i,
> val >> (i * 8),
> mmu_idx, retaddr);
> #endif
> @@ -366,7 +352,3 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
> #undef USUFFIX
> #undef DATA_SIZE
> #undef ADDR_READ
> -#undef ENV_PARAM
> -#undef ENV_VAR
> -#undef CPU_PREFIX
> -#undef HELPER_PREFIX
> diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
> index 3116287..aa00504 100644
> --- a/target-m68k/op_helper.c
> +++ b/target-m68k/op_helper.c
> @@ -192,9 +192,6 @@ void HELPER(divu)(CPUM68KState *env, uint32_t word)
> quot = num / den;
> rem = num % den;
> flags = 0;
> - /* Avoid using a PARAM1 of zero. This breaks dyngen because it uses
> - the address of a symbol, and gcc knows symbols can't have address
> - zero. */
> if (word && quot > 0xffff)
> flags |= CCF_V;
> if (quot == 0)
I am not sure this hunk really belong to this patch, it should more
likely be moved to the "target-m68k: switch to AREG0 free mode" patch.
> diff --git a/target-sparc/Makefile.objs b/target-sparc/Makefile.objs
> index a93e07d..9fc42ea 100644
> --- a/target-sparc/Makefile.objs
> +++ b/target-sparc/Makefile.objs
> @@ -4,5 +4,3 @@ obj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
> obj-$(TARGET_SPARC) += int32_helper.o
> obj-$(TARGET_SPARC64) += int64_helper.o
> obj-$(TARGET_SPARC64) += vis_helper.o
> -
> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
> index cf0ca3d..aed3b53 100644
> --- a/tcg/arm/tcg-target.c
> +++ b/tcg/arm/tcg-target.c
> @@ -176,7 +176,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> so don't use these. */
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
> -#if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
> +#if TARGET_LONG_BITS == 64
> /* If we're passing env to the helper as r0 and need a regpair
> * for the address then r2 will be overwritten as we're setting
> * up the args to the helper.
> @@ -204,8 +204,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> use these. */
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
> -#if defined(CONFIG_SOFTMMU) && \
> - defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
> +#if defined(CONFIG_SOFTMMU) && (TARGET_LONG_BITS == 64)
> /* Avoid clashes with registers being used for helper args */
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
> @@ -223,7 +222,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> #ifdef CONFIG_SOFTMMU
> /* r2 is still needed to load data_reg, so don't use it. */
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
> -#if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
> +#if TARGET_LONG_BITS == 64
> /* Avoid clashes with registers being used for helper args */
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
> #endif
> @@ -954,7 +953,6 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
>
> #include "../../softmmu_defs.h"
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
> int mmu_idx) */
> static const void * const qemu_ld_helpers[4] = {
> @@ -972,25 +970,6 @@ static const void * const qemu_st_helpers[4] = {
> helper_stl_mmu,
> helper_stq_mmu,
> };
> -#else
> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
> - mmu_idx) */
> -static void *qemu_ld_helpers[4] = {
> - __ldb_mmu,
> - __ldw_mmu,
> - __ldl_mmu,
> - __ldq_mmu,
> -};
> -
> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
> - int mmu_idx) */
> -static void *qemu_st_helpers[4] = {
> - __stb_mmu,
> - __stw_mmu,
> - __stl_mmu,
> - __stq_mmu,
> -};
> -#endif
>
> /* Helper routines for marshalling helper function arguments into
> * the correct registers and stack.
> @@ -1203,9 +1182,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
> * trash by moving the earlier arguments into them.
> */
> argreg = TCG_REG_R0;
> -#ifdef CONFIG_TCG_PASS_AREG0
> argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
> -#endif
> #if TARGET_LONG_BITS == 64
> argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
> #else
> @@ -1421,9 +1398,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
> * trash by moving the earlier arguments into them.
> */
> argreg = TCG_REG_R0;
> -#ifdef CONFIG_TCG_PASS_AREG0
> argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
> -#endif
> #if TARGET_LONG_BITS == 64
> argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
> #else
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index f90b834..c0b8f72 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -77,7 +77,6 @@ typedef enum {
> #define TCG_TARGET_HAS_GUEST_BASE
>
> enum {
> - /* Note: must be synced with dyngen-exec.h */
> TCG_AREG0 = TCG_REG_R6,
> };
>
> diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
> index 2885212..8b81b70 100644
> --- a/tcg/hppa/tcg-target.c
> +++ b/tcg/hppa/tcg-target.c
> @@ -882,7 +882,6 @@ static void tcg_out_setcond2(TCGContext *s, int cond, TCGArg ret,
> #if defined(CONFIG_SOFTMMU)
> #include "../../softmmu_defs.h"
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
> int mmu_idx) */
> static const void * const qemu_ld_helpers[4] = {
> @@ -900,25 +899,6 @@ static const void * const qemu_st_helpers[4] = {
> helper_stl_mmu,
> helper_stq_mmu,
> };
> -#else
> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
> - mmu_idx) */
> -static void *qemu_ld_helpers[4] = {
> - __ldb_mmu,
> - __ldw_mmu,
> - __ldl_mmu,
> - __ldq_mmu,
> -};
> -
> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
> - int mmu_idx) */
> -static void *qemu_st_helpers[4] = {
> - __stb_mmu,
> - __stw_mmu,
> - __stl_mmu,
> - __stq_mmu,
> -};
> -#endif
>
> /* Load and compare a TLB entry, and branch if TLB miss. OFFSET is set to
> the offset of the first ADDR_READ or ADDR_WRITE member of the appropriate
> @@ -1085,7 +1065,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
> }
> tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* XXX/FIXME: suboptimal */
> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2],
> tcg_target_call_iarg_regs[1]);
> @@ -1093,7 +1072,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
> tcg_target_call_iarg_regs[0]);
> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
> TCG_AREG0);
> -#endif
> tcg_out_call(s, qemu_ld_helpers[opc & 3]);
>
> switch (opc) {
> @@ -1245,7 +1223,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
> tcg_abort();
> }
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* XXX/FIXME: suboptimal */
> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
> tcg_target_call_iarg_regs[2]);
> @@ -1255,7 +1232,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
> tcg_target_call_iarg_regs[0]);
> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
> TCG_AREG0);
> -#endif
> tcg_out_call(s, qemu_st_helpers[opc]);
>
> /* label2: */
> diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
> index d4bf6fe..01ef960 100644
> --- a/tcg/hppa/tcg-target.h
> +++ b/tcg/hppa/tcg-target.h
> @@ -104,7 +104,6 @@ typedef enum {
>
> #define TCG_TARGET_HAS_GUEST_BASE
>
> -/* Note: must be synced with dyngen-exec.h */
> #define TCG_AREG0 TCG_REG_R17
>
>
> diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
> index da17bba..34c2df8 100644
> --- a/tcg/i386/tcg-target.c
> +++ b/tcg/i386/tcg-target.c
> @@ -183,9 +183,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> tcg_regset_set32(ct->u.regs, 0, 0xffff);
> tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
> tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
> -#endif
> } else {
> tcg_regset_set32(ct->u.regs, 0, 0xff);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
> @@ -965,7 +963,6 @@ static void tcg_out_jmp(TCGContext *s, tcg_target_long dest)
>
> #include "../../softmmu_defs.h"
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
> int mmu_idx) */
> static const void *qemu_ld_helpers[4] = {
> @@ -983,25 +980,6 @@ static const void *qemu_st_helpers[4] = {
> helper_stl_mmu,
> helper_stq_mmu,
> };
> -#else
> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
> - mmu_idx) */
> -static void *qemu_ld_helpers[4] = {
> - __ldb_mmu,
> - __ldw_mmu,
> - __ldl_mmu,
> - __ldq_mmu,
> -};
> -
> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
> - int mmu_idx) */
> -static void *qemu_st_helpers[4] = {
> - __stb_mmu,
> - __stw_mmu,
> - __stl_mmu,
> - __stq_mmu,
> -};
> -#endif
>
> /* Perform the TLB load and compare.
>
> @@ -1220,16 +1198,13 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
> }
> tcg_out_push(s, args[addrlo_idx]);
> stack_adjust += 4;
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_out_push(s, TCG_AREG0);
> stack_adjust += 4;
> -#endif
> #else
> /* The first argument is already loaded with addrlo. */
> arg_idx = 1;
> tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[arg_idx],
> mem_index);
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* XXX/FIXME: suboptimal */
> tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
> tcg_target_call_iarg_regs[2]);
> @@ -1240,7 +1215,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
> tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
> TCG_AREG0);
> #endif
> -#endif
>
> tcg_out_calli(s, (tcg_target_long)qemu_ld_helpers[s_bits]);
>
> @@ -1436,16 +1410,13 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
> }
> tcg_out_push(s, args[addrlo_idx]);
> stack_adjust += 4;
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_out_push(s, TCG_AREG0);
> stack_adjust += 4;
> -#endif
> #else
> tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32),
> tcg_target_call_iarg_regs[1], data_reg);
> tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], mem_index);
> stack_adjust = 0;
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* XXX/FIXME: suboptimal */
> tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
> tcg_target_call_iarg_regs[2]);
> @@ -1456,7 +1427,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
> tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
> TCG_AREG0);
> #endif
> -#endif
>
> tcg_out_calli(s, (tcg_target_long)qemu_st_helpers[s_bits]);
>
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index c3cfe05..8be42f3 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -116,7 +116,6 @@ typedef enum {
>
> #define TCG_TARGET_HAS_GUEST_BASE
>
> -/* Note: must be synced with dyngen-exec.h */
> #if TCG_TARGET_REG_BITS == 64
> # define TCG_AREG0 TCG_REG_R14
> #else
> diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
> index dc588db..1745038 100644
> --- a/tcg/ia64/tcg-target.c
> +++ b/tcg/ia64/tcg-target.c
> @@ -1452,7 +1452,6 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
> TCG_REG_P7, TCG_REG_R3, TCG_REG_R57));
> }
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
> int mmu_idx) */
> static const void * const qemu_ld_helpers[4] = {
> @@ -1461,16 +1460,6 @@ static const void * const qemu_ld_helpers[4] = {
> helper_ldl_mmu,
> helper_ldq_mmu,
> };
> -#else
> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
> - mmu_idx) */
> -static void *qemu_ld_helpers[4] = {
> - __ldb_mmu,
> - __ldw_mmu,
> - __ldl_mmu,
> - __ldq_mmu,
> -};
> -#endif
>
> static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
> {
> @@ -1530,7 +1519,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
> tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
> tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
> }
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* XXX/FIXME: suboptimal */
> tcg_out_bundle(s, mII,
> tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
> @@ -1539,7 +1527,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
> TCG_REG_R57, 0, TCG_REG_R56),
> tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
> TCG_REG_R56, 0, TCG_AREG0));
> -#endif
> if (!bswap || s_bits == 0) {
> tcg_out_bundle(s, miB,
> tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
> @@ -1570,7 +1557,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
> }
> }
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
> uintxx_t val, int mmu_idx) */
> static const void * const qemu_st_helpers[4] = {
> @@ -1579,16 +1565,6 @@ static const void * const qemu_st_helpers[4] = {
> helper_stl_mmu,
> helper_stq_mmu,
> };
> -#else
> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
> - int mmu_idx) */
> -static void *qemu_st_helpers[4] = {
> - __stb_mmu,
> - __stw_mmu,
> - __stl_mmu,
> - __stq_mmu,
> -};
> -#endif
>
> static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
> {
> @@ -1658,7 +1634,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
> data_reg = TCG_REG_R2;
> }
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* XXX/FIXME: suboptimal */
> tcg_out_bundle(s, mII,
> tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
> @@ -1674,15 +1649,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
> TCG_REG_R56, 0, TCG_AREG0),
> tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
> TCG_REG_B0, TCG_REG_B6));
> -#else
> - tcg_out_bundle(s, miB,
> - tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
> - data_reg, TCG_REG_R3),
> - tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
> - mem_index, TCG_REG_R0),
> - tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
> - TCG_REG_B0, TCG_REG_B6));
> -#endif
> }
>
> #else /* !CONFIG_SOFTMMU */
> diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
> index 0631b9f..c22962a 100644
> --- a/tcg/ia64/tcg-target.h
> +++ b/tcg/ia64/tcg-target.h
> @@ -140,7 +140,6 @@ typedef enum {
> #define TCG_TARGET_HAS_not_i32 0 /* xor r1, -1, r3 */
> #define TCG_TARGET_HAS_not_i64 0 /* xor r1, -1, r3 */
>
> -/* Note: must be synced with dyngen-exec.h */
> #define TCG_AREG0 TCG_REG_R7
>
> /* Guest base is supported */
> diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
> index 1006e28..74db83d 100644
> --- a/tcg/mips/tcg-target.c
> +++ b/tcg/mips/tcg-target.c
> @@ -217,7 +217,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> tcg_regset_set(ct->u.regs, 0xffffffff);
> #if defined(CONFIG_SOFTMMU)
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
> -# if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
> +# if (TARGET_LONG_BITS == 64)
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
> # endif
> #endif
> @@ -227,12 +227,11 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> tcg_regset_set(ct->u.regs, 0xffffffff);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
> #if defined(CONFIG_SOFTMMU)
> -# if (defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 32) || \
> - (!defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 64)
> +# if (TARGET_LONG_BITS == 32)
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
> # endif
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
> -# if defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 64
> +# if TARGET_LONG_BITS == 64
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
> # endif
> #endif
> @@ -821,7 +820,6 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond cond, int ret,
>
> #include "../../softmmu_defs.h"
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
> int mmu_idx) */
> static const void * const qemu_ld_helpers[4] = {
> @@ -839,25 +837,6 @@ static const void * const qemu_st_helpers[4] = {
> helper_stl_mmu,
> helper_stq_mmu,
> };
> -#else
> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
> - mmu_idx) */
> -static void *qemu_ld_helpers[4] = {
> - __ldb_mmu,
> - __ldw_mmu,
> - __ldl_mmu,
> - __ldq_mmu,
> -};
> -
> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
> - int mmu_idx) */
> -static void *qemu_st_helpers[4] = {
> - __stb_mmu,
> - __stw_mmu,
> - __stl_mmu,
> - __stq_mmu,
> -};
> -#endif
> #endif
>
> static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
> @@ -942,9 +921,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
>
> /* slow path */
> arg_num = 0;
> -# ifdef CONFIG_TCG_PASS_AREG0
> tcg_out_call_iarg_reg32(s, &arg_num, TCG_AREG0);
> -# endif
> # if TARGET_LONG_BITS == 64
> tcg_out_call_iarg_reg64(s, &arg_num, addr_regl, addr_regh);
> # else
> @@ -1127,9 +1104,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
>
> /* slow path */
> arg_num = 0;
> -# ifdef CONFIG_TCG_PASS_AREG0
> tcg_out_call_iarg_reg32(s, &arg_num, TCG_AREG0);
> -# endif
> # if TARGET_LONG_BITS == 64
> tcg_out_call_iarg_reg64(s, &arg_num, addr_regl, addr_regh);
> # else
> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
> index d3c804d..1c61931 100644
> --- a/tcg/mips/tcg-target.h
> +++ b/tcg/mips/tcg-target.h
> @@ -96,7 +96,6 @@ typedef enum {
> #define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
> #define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
>
> -/* Note: must be synced with dyngen-exec.h */
> #define TCG_AREG0 TCG_REG_S0
>
> /* guest base is supported */
> diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
> index 0cff181..26c4b33 100644
> --- a/tcg/ppc/tcg-target.c
> +++ b/tcg/ppc/tcg-target.c
> @@ -248,7 +248,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
> #if TARGET_LONG_BITS == 64
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
> @@ -256,11 +255,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
> #endif
> #endif
> -#else /* !AREG0 */
> -#if TARGET_LONG_BITS == 64
> - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
> -#endif
> -#endif
> break;
> case 'K': /* qemu_st[8..32] constraint */
> ct->ct |= TCG_CT_REG;
> @@ -268,7 +262,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
> #if TARGET_LONG_BITS == 64
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
> @@ -276,11 +269,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
> #endif
> #endif
> -#else /* !AREG0 */
> -#if TARGET_LONG_BITS == 64
> - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
> -#endif
> -#endif
> break;
> case 'M': /* qemu_st64 constraint */
> ct->ct |= TCG_CT_REG;
> @@ -290,12 +278,10 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
> -#if defined(CONFIG_TCG_PASS_AREG0)
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
> #ifdef TCG_TARGET_CALL_ALIGN_ARGS
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9);
> #endif
> -#endif
> break;
> #else
> case 'L':
> @@ -541,7 +527,6 @@ static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
>
> #include "../../softmmu_defs.h"
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
> int mmu_idx) */
> static const void * const qemu_ld_helpers[4] = {
> @@ -559,25 +544,6 @@ static const void * const qemu_st_helpers[4] = {
> helper_stl_mmu,
> helper_stq_mmu,
> };
> -#else
> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
> - mmu_idx) */
> -static void *qemu_ld_helpers[4] = {
> - __ldb_mmu,
> - __ldw_mmu,
> - __ldl_mmu,
> - __ldq_mmu,
> -};
> -
> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
> - mmu_idx) */
> -static void *qemu_st_helpers[4] = {
> - __stb_mmu,
> - __stw_mmu,
> - __stl_mmu,
> - __stq_mmu,
> -};
> -#endif
> #endif
>
> static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
> @@ -647,9 +613,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
>
> /* slow path */
> ir = 3;
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
> -#endif
> #if TARGET_LONG_BITS == 32
> tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
> #else
> @@ -849,9 +813,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
>
> /* slow path */
> ir = 3;
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
> -#endif
> #if TARGET_LONG_BITS == 32
> tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
> #else
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index 27a0ae8..337cd41 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -235,10 +235,8 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
> #ifdef CONFIG_SOFTMMU
> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
> #endif
> -#endif
> break;
> case 'S': /* qemu_st constraint */
> ct->ct |= TCG_CT_REG;
> @@ -247,10 +245,8 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
> #ifdef CONFIG_SOFTMMU
> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6);
> #endif
> -#endif
> break;
> case 'Z':
> ct->ct |= TCG_CT_CONST_U32;
> @@ -558,7 +554,6 @@ static void tcg_out_ldsta (TCGContext *s, int ret, int addr,
>
> #include "../../softmmu_defs.h"
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
> int mmu_idx) */
> static const void * const qemu_ld_helpers[4] = {
> @@ -576,25 +571,6 @@ static const void * const qemu_st_helpers[4] = {
> helper_stl_mmu,
> helper_stq_mmu,
> };
> -#else
> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
> - mmu_idx) */
> -static void *qemu_ld_helpers[4] = {
> - __ldb_mmu,
> - __ldw_mmu,
> - __ldl_mmu,
> - __ldq_mmu,
> -};
> -
> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
> - int mmu_idx) */
> -static void *qemu_st_helpers[4] = {
> - __stb_mmu,
> - __stw_mmu,
> - __stl_mmu,
> - __stq_mmu,
> -};
> -#endif
>
> static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
> int addr_reg, int s_bits, int offset)
> @@ -676,9 +652,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
>
> /* slow path */
> ir = 3;
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
> -#endif
> tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
> tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
>
> @@ -827,9 +801,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
>
> /* slow path */
> ir = 3;
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
> -#endif
> tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
> tcg_out_rld (s, RLDICL, ir++, data_reg, 0, 64 - (1 << (3 + opc)));
> tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
> diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
> index 04662c1..965e1d4 100644
> --- a/tcg/s390/tcg-target.c
> +++ b/tcg/s390/tcg-target.c
> @@ -301,7 +301,6 @@ static const uint8_t tcg_cond_to_ltr_cond[10] = {
>
> #include "../../softmmu_defs.h"
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
> int mmu_idx) */
> static const void * const qemu_ld_helpers[4] = {
> @@ -319,25 +318,6 @@ static const void * const qemu_st_helpers[4] = {
> helper_stl_mmu,
> helper_stq_mmu,
> };
> -#else
> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
> - mmu_idx) */
> -static void *qemu_ld_helpers[4] = {
> - __ldb_mmu,
> - __ldw_mmu,
> - __ldl_mmu,
> - __ldq_mmu,
> -};
> -
> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
> - int mmu_idx) */
> -static void *qemu_st_helpers[4] = {
> - __stb_mmu,
> - __stw_mmu,
> - __stl_mmu,
> - __stq_mmu,
> -};
> -#endif
> #endif
>
> static uint8_t *tb_ret_addr;
> @@ -1507,7 +1487,6 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
> tcg_abort();
> }
> tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, mem_index);
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* XXX/FIXME: suboptimal */
> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2],
> tcg_target_call_iarg_regs[1]);
> @@ -1515,11 +1494,9 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
> tcg_target_call_iarg_regs[0]);
> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
> TCG_AREG0);
> -#endif
> tgen_calli(s, (tcg_target_ulong)qemu_st_helpers[s_bits]);
> } else {
> tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* XXX/FIXME: suboptimal */
> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
> tcg_target_call_iarg_regs[2]);
> @@ -1529,7 +1506,6 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
> tcg_target_call_iarg_regs[0]);
> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
> TCG_AREG0);
> -#endif
> tgen_calli(s, (tcg_target_ulong)qemu_ld_helpers[s_bits]);
>
> /* sign extension */
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index d12f90b..4f7dfab 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -96,7 +96,6 @@ typedef enum TCGReg {
> #define TCG_TARGET_EXTEND_ARGS 1
>
> enum {
> - /* Note: must be synced with dyngen-exec.h */
> TCG_AREG0 = TCG_REG_R10,
> };
>
> diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
> index 247a278..baed3b4 100644
> --- a/tcg/sparc/tcg-target.c
> +++ b/tcg/sparc/tcg-target.c
> @@ -59,11 +59,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
> };
> #endif
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> #define ARG_OFFSET 1
> -#else
> -#define ARG_OFFSET 0
> -#endif
>
> static const int tcg_target_reg_alloc_order[] = {
> TCG_REG_L0,
> @@ -161,9 +157,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_O3);
> -#endif
> break;
> case 'I':
> ct->ct |= TCG_CT_CONST_S11;
> @@ -715,7 +709,6 @@ static void tcg_target_qemu_prologue(TCGContext *s)
>
> #include "../../softmmu_defs.h"
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
> int mmu_idx) */
> static const void * const qemu_ld_helpers[4] = {
> @@ -733,25 +726,6 @@ static const void * const qemu_st_helpers[4] = {
> helper_stl_mmu,
> helper_stq_mmu,
> };
> -#else
> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
> - mmu_idx) */
> -static const void * const qemu_ld_helpers[4] = {
> - __ldb_mmu,
> - __ldw_mmu,
> - __ldl_mmu,
> - __ldq_mmu,
> -};
> -
> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
> - int mmu_idx) */
> -static const void * const qemu_st_helpers[4] = {
> - __stb_mmu,
> - __stw_mmu,
> - __stl_mmu,
> - __stq_mmu,
> -};
> -#endif
> #endif
>
> #if TARGET_LONG_BITS == 32
> @@ -834,7 +808,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
>
> /* mov */
> tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* XXX/FIXME: suboptimal */
> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
> tcg_target_call_iarg_regs[2]);
> @@ -844,7 +817,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
> tcg_target_call_iarg_regs[0]);
> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
> TCG_AREG0);
> -#endif
>
> /* XXX: move that code at the end of the TB */
> /* qemu_ld_helper[s_bits](arg0, arg1) */
> @@ -1061,7 +1033,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
> /* mov */
> tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
>
> -#ifdef CONFIG_TCG_PASS_AREG0
> /* XXX/FIXME: suboptimal */
> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
> tcg_target_call_iarg_regs[2]);
> @@ -1071,7 +1042,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
> tcg_target_call_iarg_regs[0]);
> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
> TCG_AREG0);
> -#endif
> /* XXX: move that code at the end of the TB */
> /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
> tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
> index ee2274d..0ea87be 100644
> --- a/tcg/sparc/tcg-target.h
> +++ b/tcg/sparc/tcg-target.h
> @@ -125,7 +125,6 @@ typedef enum {
> #define TCG_TARGET_HAS_deposit_i64 0
> #endif
>
> -/* Note: must be synced with dyngen-exec.h */
> #ifdef CONFIG_SOLARIS
> #define TCG_AREG0 TCG_REG_G2
> #elif defined(__sparc_v9__)
> diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c
> index ef8580f..003244c 100644
> --- a/tcg/tci/tcg-target.c
> +++ b/tcg/tci/tcg-target.c
> @@ -798,9 +798,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> case INDEX_op_qemu_st8:
> case INDEX_op_qemu_st16:
> case INDEX_op_qemu_st32:
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_out_r(s, TCG_AREG0);
> -#endif
> tcg_out_r(s, *args++);
> tcg_out_r(s, *args++);
> #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
> @@ -811,9 +809,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> #endif
> break;
> case INDEX_op_qemu_st64:
> -#ifdef CONFIG_TCG_PASS_AREG0
> tcg_out_r(s, TCG_AREG0);
> -#endif
> tcg_out_r(s, *args++);
> #if TCG_TARGET_REG_BITS == 32
> tcg_out_r(s, *args++);
> diff --git a/tci.c b/tci.c
> index c79350d..ce8a988 100644
> --- a/tci.c
> +++ b/tci.c
> @@ -25,7 +25,6 @@
> #endif
>
> #include "qemu-common.h"
> -#include "dyngen-exec.h" /* env */
> #include "exec-all.h" /* MAX_OPC_PARAM_IARGS */
> #include "tcg-op.h"
>
> @@ -63,17 +62,6 @@ uintptr_t tci_tb_ptr;
>
> static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
>
> -#if !defined(CONFIG_TCG_PASS_AREG0)
> -# define helper_ldb_mmu(env, addr, mmu_idx) __ldb_mmu(addr, mmu_idx)
> -# define helper_ldw_mmu(env, addr, mmu_idx) __ldw_mmu(addr, mmu_idx)
> -# define helper_ldl_mmu(env, addr, mmu_idx) __ldl_mmu(addr, mmu_idx)
> -# define helper_ldq_mmu(env, addr, mmu_idx) __ldq_mmu(addr, mmu_idx)
> -# define helper_stb_mmu(env, addr, val, mmu_idx) __stb_mmu(addr, val, mmu_idx)
> -# define helper_stw_mmu(env, addr, val, mmu_idx) __stw_mmu(addr, val, mmu_idx)
> -# define helper_stl_mmu(env, addr, val, mmu_idx) __stl_mmu(addr, val, mmu_idx)
> -# define helper_stq_mmu(env, addr, val, mmu_idx) __stq_mmu(addr, val, mmu_idx)
> -#endif /* !CONFIG_TCG_PASS_AREG0 */
> -
> static tcg_target_ulong tci_read_reg(TCGReg index)
> {
> assert(index < ARRAY_SIZE(tci_reg));
> diff --git a/user-exec.c b/user-exec.c
> index b9ea9dd..ef9b172 100644
> --- a/user-exec.c
> +++ b/user-exec.c
> @@ -18,9 +18,6 @@
> */
> #include "config.h"
> #include "cpu.h"
> -#ifndef CONFIG_TCG_PASS_AREG0
> -#include "dyngen-exec.h"
> -#endif
> #include "disas.h"
> #include "tcg.h"
>
> @@ -60,12 +57,6 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc)
> struct sigcontext *uc = puc;
> #endif
>
> -#ifndef CONFIG_TCG_PASS_AREG0
> - env = env1;
> -
> - /* XXX: restore cpu registers saved in host registers */
> -#endif
> -
> if (puc) {
> /* XXX: use siglongjmp ? */
> #ifdef __linux__
> @@ -93,11 +84,6 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
> TranslationBlock *tb;
> int ret;
>
> -#ifndef CONFIG_TCG_PASS_AREG0
> - if (cpu_single_env) {
> - env = cpu_single_env; /* XXX: find a correct solution for multithread */
> - }
> -#endif
> #if defined(DEBUG_SIGNAL)
> qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
> pc, address, is_write, *(unsigned long *)old_set);
> --
> 1.7.2.5
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [Qemu-devel] [PATCH 21/21] Remove unused CONFIG_TCG_PASS_AREG0 and dead code
2012-09-06 15:30 ` Aurelien Jarno
@ 2012-09-08 7:21 ` Blue Swirl
0 siblings, 0 replies; 64+ messages in thread
From: Blue Swirl @ 2012-09-08 7:21 UTC (permalink / raw)
To: Aurelien Jarno
Cc: Stefan Weil, Paul Brook, Richard Henderson, qemu-devel,
Alexander Graf
On Thu, Sep 6, 2012 at 3:30 PM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Sun, Sep 02, 2012 at 05:33:50PM +0000, Blue Swirl wrote:
>> Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,
>> remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.
>>
>> Remove dyngen-exec.h and all references to it. Although included by
>> hw/spapr_hcall.c, it does not seem to use it.
>>
>> Remove unused HELPER_CFLAGS.
>>
>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>> ---
>> Makefile.target | 8 -----
>> configure | 11 -------
>> cpu-all.h | 11 -------
>> cputlb.c | 4 --
>> dyngen-exec.h | 70 ------------------------------------------
>> exec-all.h | 4 --
>> hw/spapr_hcall.c | 1 -
>> softmmu_defs.h | 21 -------------
>> softmmu_header.h | 63 ++++++++++++--------------------------
>> softmmu_template.h | 72 ++++++++++++++++---------------------------
>> target-m68k/op_helper.c | 3 --
>> target-sparc/Makefile.objs | 2 -
>> tcg/arm/tcg-target.c | 31 ++-----------------
>> tcg/arm/tcg-target.h | 1 -
>> tcg/hppa/tcg-target.c | 24 --------------
>> tcg/hppa/tcg-target.h | 1 -
>> tcg/i386/tcg-target.c | 30 ------------------
>> tcg/i386/tcg-target.h | 1 -
>> tcg/ia64/tcg-target.c | 34 --------------------
>> tcg/ia64/tcg-target.h | 1 -
>> tcg/mips/tcg-target.c | 31 ++-----------------
>> tcg/mips/tcg-target.h | 1 -
>> tcg/ppc/tcg-target.c | 38 -----------------------
>> tcg/ppc64/tcg-target.c | 28 -----------------
>> tcg/s390/tcg-target.c | 24 --------------
>> tcg/s390/tcg-target.h | 1 -
>> tcg/sparc/tcg-target.c | 30 ------------------
>> tcg/sparc/tcg-target.h | 1 -
>> tcg/tci/tcg-target.c | 4 --
>> tci.c | 12 -------
>> user-exec.c | 14 --------
>> 31 files changed, 53 insertions(+), 524 deletions(-)
>> delete mode 100644 dyngen-exec.h
>>
>> diff --git a/Makefile.target b/Makefile.target
>> index 7892a8d..d9d54b8 100644
>> --- a/Makefile.target
>> +++ b/Makefile.target
>> @@ -80,14 +80,6 @@ obj-$(CONFIG_GDBSTUB_XML) += gdbstub-xml.o
>>
>> tci-dis.o: QEMU_CFLAGS += -I$(SRC_PATH)/tcg -I$(SRC_PATH)/tcg/tci
>>
>> -# HELPER_CFLAGS is used for all the legacy code compiled with static register
>> -# variables
>> -user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
>> -
>> -# Note: this is a workaround. The real fix is to avoid compiling
>> -# cpu_signal_handler() in user-exec.c.
>> -%/signal.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
>> -
>> #########################################################
>> # Linux user emulator target
>>
>> diff --git a/configure b/configure
>> index f60a4b6..e7d333b 100755
>> --- a/configure
>> +++ b/configure
>> @@ -118,7 +118,6 @@ audio_card_list="ac97 es1370 sb16 hda"
>> audio_possible_cards="ac97 es1370 sb16 cs4231a adlib gus hda"
>> block_drv_whitelist=""
>> host_cc="gcc"
>> -helper_cflags=""
>> libs_softmmu=""
>> libs_tools=""
>> audio_pt_int=""
>> @@ -894,7 +893,6 @@ case "$cpu" in
>> QEMU_CFLAGS="-m32 -ffixed-g2 -ffixed-g3 $QEMU_CFLAGS"
>> if test "$solaris" = "no" ; then
>> QEMU_CFLAGS="-ffixed-g1 -ffixed-g6 $QEMU_CFLAGS"
>> - helper_cflags="-ffixed-i0"
>> fi
>> ;;
>> sparc64)
>> @@ -919,7 +917,6 @@ case "$cpu" in
>> QEMU_CFLAGS="-m32 $QEMU_CFLAGS"
>> LDFLAGS="-m32 $LDFLAGS"
>> cc_i386='$(CC) -m32'
>> - helper_cflags="-fomit-frame-pointer"
>> host_guest_base="yes"
>> ;;
>> x86_64)
>> @@ -3572,7 +3569,6 @@ if test "$sparse" = "yes" ; then
>> echo "HOST_CC := REAL_CC=\"\$(HOST_CC)\" cgcc" >> $config_host_mak
>> echo "QEMU_CFLAGS += -Wbitwise -Wno-transparent-union -Wno-old-initializer -Wno-non-pointer-null" >> $config_host_mak
>> fi
>> -echo "HELPER_CFLAGS=$helper_cflags" >> $config_host_mak
>> echo "LDFLAGS=$LDFLAGS" >> $config_host_mak
>> echo "ARLIBS_BEGIN=$arlibs_begin" >> $config_host_mak
>> echo "ARLIBS_END=$arlibs_end" >> $config_host_mak
>> @@ -3827,13 +3823,6 @@ fi
>>
>> symlink "$source_path/Makefile.target" "$target_dir/Makefile"
>>
>> -
>> -case "$target_arch2" in
>> - alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | mips* | or32 | s390x | sh4* | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
>> - echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
>> - ;;
>> -esac
>> -
>> upper() {
>> echo "$@"| LC_ALL=C tr '[a-z]' '[A-Z]'
>> }
>> diff --git a/cpu-all.h b/cpu-all.h
>> index 5e07d28..74d3681 100644
>> --- a/cpu-all.h
>> +++ b/cpu-all.h
>> @@ -260,14 +260,6 @@ extern unsigned long reserved_va;
>> #define stfl(p, v) stfl_raw(p, v)
>> #define stfq(p, v) stfq_raw(p, v)
>>
>> -#ifndef CONFIG_TCG_PASS_AREG0
>> -#define ldub_code(p) ldub_raw(p)
>> -#define ldsb_code(p) ldsb_raw(p)
>> -#define lduw_code(p) lduw_raw(p)
>> -#define ldsw_code(p) ldsw_raw(p)
>> -#define ldl_code(p) ldl_raw(p)
>> -#define ldq_code(p) ldq_raw(p)
>> -#else
>> #define cpu_ldub_code(env1, p) ldub_raw(p)
>> #define cpu_ldsb_code(env1, p) ldsb_raw(p)
>> #define cpu_lduw_code(env1, p) lduw_raw(p)
>> @@ -296,7 +288,6 @@ extern unsigned long reserved_va;
>> #define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
>> #define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
>> #define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)
>> -#endif
>>
>> #define ldub_kernel(p) ldub_raw(p)
>> #define ldsb_kernel(p) ldsb_raw(p)
>> @@ -313,7 +304,6 @@ extern unsigned long reserved_va;
>> #define stfl_kernel(p, v) stfl_raw(p, v)
>> #define stfq_kernel(p, vt) stfq_raw(p, v)
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> #define cpu_ldub_data(env, addr) ldub_raw(addr)
>> #define cpu_lduw_data(env, addr) lduw_raw(addr)
>> #define cpu_ldl_data(env, addr) ldl_raw(addr)
>> @@ -321,7 +311,6 @@ extern unsigned long reserved_va;
>> #define cpu_stb_data(env, addr, data) stb_raw(addr, data)
>> #define cpu_stw_data(env, addr, data) stw_raw(addr, data)
>> #define cpu_stl_data(env, addr, data) stl_raw(addr, data)
>> -#endif
>> #endif /* defined(CONFIG_USER_ONLY) */
>>
>> /* page related stuff */
>> diff --git a/cputlb.c b/cputlb.c
>> index d3e7b25..8468517 100644
>> --- a/cputlb.c
>> +++ b/cputlb.c
>> @@ -325,11 +325,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
>> mmu_idx = cpu_mmu_index(env1);
>> if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
>> (addr & TARGET_PAGE_MASK))) {
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> cpu_ldub_code(env1, addr);
>> -#else
>> - ldub_code(addr);
>> -#endif
>> }
>> pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
>> mr = iotlb_to_region(pd);
>> diff --git a/dyngen-exec.h b/dyngen-exec.h
>> deleted file mode 100644
>> index 083e20b..0000000
>> --- a/dyngen-exec.h
>> +++ /dev/null
>> @@ -1,70 +0,0 @@
>> -/*
>> - * dyngen defines for micro operation code
>> - *
>> - * Copyright (c) 2003 Fabrice Bellard
>> - *
>> - * This library is free software; you can redistribute it and/or
>> - * modify it under the terms of the GNU Lesser General Public
>> - * License as published by the Free Software Foundation; either
>> - * version 2 of the License, or (at your option) any later version.
>> - *
>> - * This library is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> - * Lesser General Public License for more details.
>> - *
>> - * You should have received a copy of the GNU Lesser General Public
>> - * License along with this library; if not, see <http://www.gnu.org/licenses/>.
>> - */
>> -#if !defined(__DYNGEN_EXEC_H__)
>> -#define __DYNGEN_EXEC_H__
>> -
>> -#if defined(CONFIG_TCG_INTERPRETER)
>> -/* The TCG interpreter does not need a special register AREG0,
>> - * but it is possible to use one by defining AREG0.
>> - * On i386, register edi seems to work. */
>> -/* Run without special register AREG0 or use a value defined elsewhere. */
>> -#elif defined(__i386__)
>> -#define AREG0 "ebp"
>> -#elif defined(__x86_64__)
>> -#define AREG0 "r14"
>> -#elif defined(_ARCH_PPC)
>> -#define AREG0 "r27"
>> -#elif defined(__arm__)
>> -#define AREG0 "r6"
>> -#elif defined(__hppa__)
>> -#define AREG0 "r17"
>> -#elif defined(__mips__)
>> -#define AREG0 "s0"
>> -#elif defined(__sparc__)
>> -#ifdef CONFIG_SOLARIS
>> -#define AREG0 "g2"
>> -#else
>> -#ifdef __sparc_v9__
>> -#define AREG0 "g5"
>> -#else
>> -#define AREG0 "g6"
>> -#endif
>> -#endif
>> -#elif defined(__s390__)
>> -#define AREG0 "r10"
>> -#elif defined(__alpha__)
>> -/* Note $15 is the frame pointer, so anything in op-i386.c that would
>> - require a frame pointer, like alloca, would probably loose. */
>> -#define AREG0 "$15"
>> -#elif defined(__mc68000)
>> -#define AREG0 "%a5"
>> -#elif defined(__ia64__)
>> -#define AREG0 "r7"
>> -#else
>> -#error unsupported CPU
>> -#endif
>> -
>> -#if defined(AREG0)
>> -register CPUArchState *env asm(AREG0);
>> -#else
>> -/* TODO: Try env = cpu_single_env. */
>> -extern CPUArchState *env;
>> -#endif
>> -
>> -#endif /* !defined(__DYNGEN_EXEC_H__) */
>> diff --git a/exec-all.h b/exec-all.h
>> index c5ec8e1..c5d3a13 100644
>> --- a/exec-all.h
>> +++ b/exec-all.h
>> @@ -323,9 +323,6 @@ void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
>>
>> #define ACCESS_TYPE (NB_MMU_MODES + 1)
>> #define MEMSUFFIX _code
>> -#ifndef CONFIG_TCG_PASS_AREG0
>> -#define env cpu_single_env
>> -#endif
>>
>> #define DATA_SIZE 1
>> #include "softmmu_header.h"
>> @@ -341,7 +338,6 @@ void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
>>
>> #undef ACCESS_TYPE
>> #undef MEMSUFFIX
>> -#undef env
>>
>> #endif
>>
>> diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c
>> index a5990a9..abd847f 100644
>> --- a/hw/spapr_hcall.c
>> +++ b/hw/spapr_hcall.c
>> @@ -1,6 +1,5 @@
>> #include "sysemu.h"
>> #include "cpu.h"
>> -#include "dyngen-exec.h"
>> #include "qemu-char.h"
>> #include "sysemu.h"
>> #include "qemu-char.h"
>> diff --git a/softmmu_defs.h b/softmmu_defs.h
>> index 8d59f9d..1f25e33 100644
>> --- a/softmmu_defs.h
>> +++ b/softmmu_defs.h
>> @@ -9,25 +9,6 @@
>> #ifndef SOFTMMU_DEFS_H
>> #define SOFTMMU_DEFS_H
>>
>> -#ifndef CONFIG_TCG_PASS_AREG0
>> -uint8_t __ldb_mmu(target_ulong addr, int mmu_idx);
>> -void __stb_mmu(target_ulong addr, uint8_t val, int mmu_idx);
>> -uint16_t __ldw_mmu(target_ulong addr, int mmu_idx);
>> -void __stw_mmu(target_ulong addr, uint16_t val, int mmu_idx);
>> -uint32_t __ldl_mmu(target_ulong addr, int mmu_idx);
>> -void __stl_mmu(target_ulong addr, uint32_t val, int mmu_idx);
>> -uint64_t __ldq_mmu(target_ulong addr, int mmu_idx);
>> -void __stq_mmu(target_ulong addr, uint64_t val, int mmu_idx);
>> -
>> -uint8_t __ldb_cmmu(target_ulong addr, int mmu_idx);
>> -void __stb_cmmu(target_ulong addr, uint8_t val, int mmu_idx);
>> -uint16_t __ldw_cmmu(target_ulong addr, int mmu_idx);
>> -void __stw_cmmu(target_ulong addr, uint16_t val, int mmu_idx);
>> -uint32_t __ldl_cmmu(target_ulong addr, int mmu_idx);
>> -void __stl_cmmu(target_ulong addr, uint32_t val, int mmu_idx);
>> -uint64_t __ldq_cmmu(target_ulong addr, int mmu_idx);
>> -void __stq_cmmu(target_ulong addr, uint64_t val, int mmu_idx);
>> -#else
>> uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
>> void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
>> int mmu_idx);
>> @@ -54,5 +35,3 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
>> void helper_stq_cmmu(CPUArchState *env, target_ulong addr, uint64_t val,
>> int mmu_idx);
>> #endif
>> -
>> -#endif
>> diff --git a/softmmu_header.h b/softmmu_header.h
>> index cf1aa38..d8d9c81 100644
>> --- a/softmmu_header.h
>> +++ b/softmmu_header.h
>> @@ -78,23 +78,10 @@
>> #define ADDR_READ addr_read
>> #endif
>>
>> -#ifndef CONFIG_TCG_PASS_AREG0
>> -#define ENV_PARAM
>> -#define ENV_VAR
>> -#define CPU_PREFIX
>> -#define HELPER_PREFIX __
>> -#else
>> -#define ENV_PARAM CPUArchState *env,
>> -#define ENV_VAR env,
>> -#define CPU_PREFIX cpu_
>> -#define HELPER_PREFIX helper_
>> -#endif
>> -
>> /* generic load/store macros */
>>
>> static inline RES_TYPE
>> -glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
>> - target_ulong ptr)
>> +glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
>> {
>> int page_index;
>> RES_TYPE res;
>> @@ -106,9 +93,7 @@ glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
>> mmu_idx = CPU_MMU_INDEX;
>> if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
>> (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
>> - res = glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_VAR
>> - addr,
>> - mmu_idx);
>> + res = glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx);
>> } else {
>> uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
>> res = glue(glue(ld, USUFFIX), _raw)(hostaddr);
>> @@ -118,8 +103,7 @@ glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
>>
>> #if DATA_SIZE <= 2
>> static inline int
>> -glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
>> - target_ulong ptr)
>> +glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
>> {
>> int res, page_index;
>> target_ulong addr;
>> @@ -130,8 +114,8 @@ glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
>> mmu_idx = CPU_MMU_INDEX;
>> if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
>> (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
>> - res = (DATA_STYPE)glue(glue(glue(HELPER_PREFIX, ld), SUFFIX),
>> - MMUSUFFIX)(ENV_VAR addr, mmu_idx);
>> + res = (DATA_STYPE)glue(glue(helper_ld, SUFFIX),
>> + MMUSUFFIX)(env, addr, mmu_idx);
>> } else {
>> uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
>> res = glue(glue(lds, SUFFIX), _raw)(hostaddr);
>> @@ -145,8 +129,8 @@ glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
>> /* generic store macro */
>>
>> static inline void
>> -glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
>> - RES_TYPE v)
>> +glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
>> + RES_TYPE v)
>> {
>> int page_index;
>> target_ulong addr;
>> @@ -157,8 +141,7 @@ glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
>> mmu_idx = CPU_MMU_INDEX;
>> if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
>> (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
>> - glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_VAR addr, v,
>> - mmu_idx);
>> + glue(glue(helper_st, SUFFIX), MMUSUFFIX)(env, addr, v, mmu_idx);
>> } else {
>> uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
>> glue(glue(st, SUFFIX), _raw)(hostaddr, v);
>> @@ -170,52 +153,50 @@ glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
>> #if ACCESS_TYPE != (NB_MMU_MODES + 1)
>>
>> #if DATA_SIZE == 8
>> -static inline float64 glue(glue(CPU_PREFIX, ldfq), MEMSUFFIX)(ENV_PARAM
>> - target_ulong ptr)
>> +static inline float64 glue(cpu_ldfq, MEMSUFFIX)(CPUArchState *env,
>> + target_ulong ptr)
>> {
>> union {
>> float64 d;
>> uint64_t i;
>> } u;
>> - u.i = glue(glue(CPU_PREFIX, ldq), MEMSUFFIX)(ENV_VAR ptr);
>> + u.i = glue(cpu_ldq, MEMSUFFIX)(env, ptr);
>> return u.d;
>> }
>>
>> -static inline void glue(glue(CPU_PREFIX, stfq), MEMSUFFIX)(ENV_PARAM
>> - target_ulong ptr,
>> - float64 v)
>> +static inline void glue(cpu_stfq, MEMSUFFIX)(CPUArchState *env,
>> + target_ulong ptr, float64 v)
>> {
>> union {
>> float64 d;
>> uint64_t i;
>> } u;
>> u.d = v;
>> - glue(glue(CPU_PREFIX, stq), MEMSUFFIX)(ENV_VAR ptr, u.i);
>> + glue(cpu_stq, MEMSUFFIX)(env, ptr, u.i);
>> }
>> #endif /* DATA_SIZE == 8 */
>>
>> #if DATA_SIZE == 4
>> -static inline float32 glue(glue(CPU_PREFIX, ldfl), MEMSUFFIX)(ENV_PARAM
>> - target_ulong ptr)
>> +static inline float32 glue(cpu_ldfl, MEMSUFFIX)(CPUArchState *env,
>> + target_ulong ptr)
>> {
>> union {
>> float32 f;
>> uint32_t i;
>> } u;
>> - u.i = glue(glue(CPU_PREFIX, ldl), MEMSUFFIX)(ENV_VAR ptr);
>> + u.i = glue(cpu_ldl, MEMSUFFIX)(env, ptr);
>> return u.f;
>> }
>>
>> -static inline void glue(glue(CPU_PREFIX, stfl), MEMSUFFIX)(ENV_PARAM
>> - target_ulong ptr,
>> - float32 v)
>> +static inline void glue(cpu_stfl, MEMSUFFIX)(CPUArchState *env,
>> + target_ulong ptr, float32 v)
>> {
>> union {
>> float32 f;
>> uint32_t i;
>> } u;
>> u.f = v;
>> - glue(glue(CPU_PREFIX, stl), MEMSUFFIX)(ENV_VAR ptr, u.i);
>> + glue(cpu_stl, MEMSUFFIX)(env, ptr, u.i);
>> }
>> #endif /* DATA_SIZE == 4 */
>>
>> @@ -230,7 +211,3 @@ static inline void glue(glue(CPU_PREFIX, stfl), MEMSUFFIX)(ENV_PARAM
>> #undef CPU_MMU_INDEX
>> #undef MMUSUFFIX
>> #undef ADDR_READ
>> -#undef ENV_PARAM
>> -#undef ENV_VAR
>> -#undef CPU_PREFIX
>> -#undef HELPER_PREFIX
>> diff --git a/softmmu_template.h b/softmmu_template.h
>> index b8bd700..e2490f0 100644
>> --- a/softmmu_template.h
>> +++ b/softmmu_template.h
>> @@ -54,23 +54,11 @@
>> #define ADDR_READ addr_read
>> #endif
>>
>> -#ifndef CONFIG_TCG_PASS_AREG0
>> -#define ENV_PARAM
>> -#define ENV_VAR
>> -#define CPU_PREFIX
>> -#define HELPER_PREFIX __
>> -#else
>> -#define ENV_PARAM CPUArchState *env,
>> -#define ENV_VAR env,
>> -#define CPU_PREFIX cpu_
>> -#define HELPER_PREFIX helper_
>> -#endif
>> -
>> -static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
>> +static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
>> target_ulong addr,
>> int mmu_idx,
>> uintptr_t retaddr);
>> -static inline DATA_TYPE glue(io_read, SUFFIX)(ENV_PARAM
>> +static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
>> target_phys_addr_t physaddr,
>> target_ulong addr,
>> uintptr_t retaddr)
>> @@ -104,9 +92,8 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(ENV_PARAM
>>
>> /* handle all cases except unaligned access which span two pages */
>> DATA_TYPE
>> -glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
>> - target_ulong addr,
>> - int mmu_idx)
>> +glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
>> + int mmu_idx)
>> {
>> DATA_TYPE res;
>> int index;
>> @@ -126,15 +113,15 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
>> goto do_unaligned_access;
>> retaddr = GETPC();
>> ioaddr = env->iotlb[mmu_idx][index];
>> - res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
>> + res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
>> } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
>> /* slow unaligned access (it spans two pages or IO) */
>> do_unaligned_access:
>> retaddr = GETPC();
>> #ifdef ALIGNED_ONLY
>> - do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
>> + do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
>> #endif
>> - res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr,
>> + res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr,
>> mmu_idx, retaddr);
>> } else {
>> /* unaligned/aligned access in the same page */
>> @@ -142,7 +129,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
>> #ifdef ALIGNED_ONLY
>> if ((addr & (DATA_SIZE - 1)) != 0) {
>> retaddr = GETPC();
>> - do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
>> + do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
>> }
>> #endif
>> addend = env->tlb_table[mmu_idx][index].addend;
>> @@ -154,7 +141,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
>> retaddr = GETPC();
>> #ifdef ALIGNED_ONLY
>> if ((addr & (DATA_SIZE - 1)) != 0)
>> - do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
>> + do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
>> #endif
>> tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
>> goto redo;
>> @@ -164,7 +151,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
>>
>> /* handle all unaligned cases */
>> static DATA_TYPE
>> -glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
>> +glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
>> target_ulong addr,
>> int mmu_idx,
>> uintptr_t retaddr)
>> @@ -183,15 +170,15 @@ glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
>> if ((addr & (DATA_SIZE - 1)) != 0)
>> goto do_unaligned_access;
>> ioaddr = env->iotlb[mmu_idx][index];
>> - res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
>> + res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
>> } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
>> do_unaligned_access:
>> /* slow unaligned access (it spans two pages) */
>> addr1 = addr & ~(DATA_SIZE - 1);
>> addr2 = addr1 + DATA_SIZE;
>> - res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr1,
>> + res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr1,
>> mmu_idx, retaddr);
>> - res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr2,
>> + res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr2,
>> mmu_idx, retaddr);
>> shift = (addr & (DATA_SIZE - 1)) * 8;
>> #ifdef TARGET_WORDS_BIGENDIAN
>> @@ -216,13 +203,13 @@ glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
>>
>> #ifndef SOFTMMU_CODE_ACCESS
>>
>> -static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
>> +static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
>> target_ulong addr,
>> DATA_TYPE val,
>> int mmu_idx,
>> uintptr_t retaddr);
>>
>> -static inline void glue(io_write, SUFFIX)(ENV_PARAM
>> +static inline void glue(io_write, SUFFIX)(CPUArchState *env,
>> target_phys_addr_t physaddr,
>> DATA_TYPE val,
>> target_ulong addr,
>> @@ -253,10 +240,9 @@ static inline void glue(io_write, SUFFIX)(ENV_PARAM
>> #endif /* SHIFT > 2 */
>> }
>>
>> -void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
>> - target_ulong addr,
>> - DATA_TYPE val,
>> - int mmu_idx)
>> +void glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
>> + target_ulong addr, DATA_TYPE val,
>> + int mmu_idx)
>> {
>> target_phys_addr_t ioaddr;
>> target_ulong tlb_addr;
>> @@ -273,14 +259,14 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
>> goto do_unaligned_access;
>> retaddr = GETPC();
>> ioaddr = env->iotlb[mmu_idx][index];
>> - glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
>> + glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
>> } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
>> do_unaligned_access:
>> retaddr = GETPC();
>> #ifdef ALIGNED_ONLY
>> - do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
>> + do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
>> #endif
>> - glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_VAR addr, val,
>> + glue(glue(slow_st, SUFFIX), MMUSUFFIX)(env, addr, val,
>> mmu_idx, retaddr);
>> } else {
>> /* aligned/unaligned access in the same page */
>> @@ -288,7 +274,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
>> #ifdef ALIGNED_ONLY
>> if ((addr & (DATA_SIZE - 1)) != 0) {
>> retaddr = GETPC();
>> - do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
>> + do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
>> }
>> #endif
>> addend = env->tlb_table[mmu_idx][index].addend;
>> @@ -300,7 +286,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
>> retaddr = GETPC();
>> #ifdef ALIGNED_ONLY
>> if ((addr & (DATA_SIZE - 1)) != 0)
>> - do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
>> + do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
>> #endif
>> tlb_fill(env, addr, 1, mmu_idx, retaddr);
>> goto redo;
>> @@ -308,7 +294,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
>> }
>>
>> /* handles all unaligned cases */
>> -static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
>> +static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
>> target_ulong addr,
>> DATA_TYPE val,
>> int mmu_idx,
>> @@ -327,7 +313,7 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
>> if ((addr & (DATA_SIZE - 1)) != 0)
>> goto do_unaligned_access;
>> ioaddr = env->iotlb[mmu_idx][index];
>> - glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
>> + glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
>> } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
>> do_unaligned_access:
>> /* XXX: not efficient, but simple */
>> @@ -335,11 +321,11 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
>> * previous page from the TLB cache. */
>> for(i = DATA_SIZE - 1; i >= 0; i--) {
>> #ifdef TARGET_WORDS_BIGENDIAN
>> - glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
>> + glue(slow_stb, MMUSUFFIX)(env, addr + i,
>> val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
>> mmu_idx, retaddr);
>> #else
>> - glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
>> + glue(slow_stb, MMUSUFFIX)(env, addr + i,
>> val >> (i * 8),
>> mmu_idx, retaddr);
>> #endif
>> @@ -366,7 +352,3 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
>> #undef USUFFIX
>> #undef DATA_SIZE
>> #undef ADDR_READ
>> -#undef ENV_PARAM
>> -#undef ENV_VAR
>> -#undef CPU_PREFIX
>> -#undef HELPER_PREFIX
>> diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
>> index 3116287..aa00504 100644
>> --- a/target-m68k/op_helper.c
>> +++ b/target-m68k/op_helper.c
>> @@ -192,9 +192,6 @@ void HELPER(divu)(CPUM68KState *env, uint32_t word)
>> quot = num / den;
>> rem = num % den;
>> flags = 0;
>> - /* Avoid using a PARAM1 of zero. This breaks dyngen because it uses
>> - the address of a symbol, and gcc knows symbols can't have address
>> - zero. */
>> if (word && quot > 0xffff)
>> flags |= CCF_V;
>> if (quot == 0)
>
> I am not sure this hunk really belong to this patch, it should more
> likely be moved to the "target-m68k: switch to AREG0 free mode" patch.
It should have belonged to the commit that removed dyngen system,
PARAM1 hasn't meant anything for ages. It could be extracted to a
separate cleanup patch but I think it still fits the overall cleanup
that removes last remaining pieces of dyngen.
>
>
>> diff --git a/target-sparc/Makefile.objs b/target-sparc/Makefile.objs
>> index a93e07d..9fc42ea 100644
>> --- a/target-sparc/Makefile.objs
>> +++ b/target-sparc/Makefile.objs
>> @@ -4,5 +4,3 @@ obj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
>> obj-$(TARGET_SPARC) += int32_helper.o
>> obj-$(TARGET_SPARC64) += int64_helper.o
>> obj-$(TARGET_SPARC64) += vis_helper.o
>> -
>> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
>> diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
>> index cf0ca3d..aed3b53 100644
>> --- a/tcg/arm/tcg-target.c
>> +++ b/tcg/arm/tcg-target.c
>> @@ -176,7 +176,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> so don't use these. */
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
>> -#if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
>> +#if TARGET_LONG_BITS == 64
>> /* If we're passing env to the helper as r0 and need a regpair
>> * for the address then r2 will be overwritten as we're setting
>> * up the args to the helper.
>> @@ -204,8 +204,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> use these. */
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
>> -#if defined(CONFIG_SOFTMMU) && \
>> - defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
>> +#if defined(CONFIG_SOFTMMU) && (TARGET_LONG_BITS == 64)
>> /* Avoid clashes with registers being used for helper args */
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
>> @@ -223,7 +222,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> #ifdef CONFIG_SOFTMMU
>> /* r2 is still needed to load data_reg, so don't use it. */
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
>> -#if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
>> +#if TARGET_LONG_BITS == 64
>> /* Avoid clashes with registers being used for helper args */
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
>> #endif
>> @@ -954,7 +953,6 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
>>
>> #include "../../softmmu_defs.h"
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
>> int mmu_idx) */
>> static const void * const qemu_ld_helpers[4] = {
>> @@ -972,25 +970,6 @@ static const void * const qemu_st_helpers[4] = {
>> helper_stl_mmu,
>> helper_stq_mmu,
>> };
>> -#else
>> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
>> - mmu_idx) */
>> -static void *qemu_ld_helpers[4] = {
>> - __ldb_mmu,
>> - __ldw_mmu,
>> - __ldl_mmu,
>> - __ldq_mmu,
>> -};
>> -
>> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
>> - int mmu_idx) */
>> -static void *qemu_st_helpers[4] = {
>> - __stb_mmu,
>> - __stw_mmu,
>> - __stl_mmu,
>> - __stq_mmu,
>> -};
>> -#endif
>>
>> /* Helper routines for marshalling helper function arguments into
>> * the correct registers and stack.
>> @@ -1203,9 +1182,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
>> * trash by moving the earlier arguments into them.
>> */
>> argreg = TCG_REG_R0;
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
>> -#endif
>> #if TARGET_LONG_BITS == 64
>> argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
>> #else
>> @@ -1421,9 +1398,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
>> * trash by moving the earlier arguments into them.
>> */
>> argreg = TCG_REG_R0;
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
>> -#endif
>> #if TARGET_LONG_BITS == 64
>> argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
>> #else
>> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
>> index f90b834..c0b8f72 100644
>> --- a/tcg/arm/tcg-target.h
>> +++ b/tcg/arm/tcg-target.h
>> @@ -77,7 +77,6 @@ typedef enum {
>> #define TCG_TARGET_HAS_GUEST_BASE
>>
>> enum {
>> - /* Note: must be synced with dyngen-exec.h */
>> TCG_AREG0 = TCG_REG_R6,
>> };
>>
>> diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
>> index 2885212..8b81b70 100644
>> --- a/tcg/hppa/tcg-target.c
>> +++ b/tcg/hppa/tcg-target.c
>> @@ -882,7 +882,6 @@ static void tcg_out_setcond2(TCGContext *s, int cond, TCGArg ret,
>> #if defined(CONFIG_SOFTMMU)
>> #include "../../softmmu_defs.h"
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
>> int mmu_idx) */
>> static const void * const qemu_ld_helpers[4] = {
>> @@ -900,25 +899,6 @@ static const void * const qemu_st_helpers[4] = {
>> helper_stl_mmu,
>> helper_stq_mmu,
>> };
>> -#else
>> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
>> - mmu_idx) */
>> -static void *qemu_ld_helpers[4] = {
>> - __ldb_mmu,
>> - __ldw_mmu,
>> - __ldl_mmu,
>> - __ldq_mmu,
>> -};
>> -
>> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
>> - int mmu_idx) */
>> -static void *qemu_st_helpers[4] = {
>> - __stb_mmu,
>> - __stw_mmu,
>> - __stl_mmu,
>> - __stq_mmu,
>> -};
>> -#endif
>>
>> /* Load and compare a TLB entry, and branch if TLB miss. OFFSET is set to
>> the offset of the first ADDR_READ or ADDR_WRITE member of the appropriate
>> @@ -1085,7 +1065,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
>> }
>> tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* XXX/FIXME: suboptimal */
>> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2],
>> tcg_target_call_iarg_regs[1]);
>> @@ -1093,7 +1072,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
>> tcg_target_call_iarg_regs[0]);
>> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
>> TCG_AREG0);
>> -#endif
>> tcg_out_call(s, qemu_ld_helpers[opc & 3]);
>>
>> switch (opc) {
>> @@ -1245,7 +1223,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
>> tcg_abort();
>> }
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* XXX/FIXME: suboptimal */
>> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
>> tcg_target_call_iarg_regs[2]);
>> @@ -1255,7 +1232,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
>> tcg_target_call_iarg_regs[0]);
>> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
>> TCG_AREG0);
>> -#endif
>> tcg_out_call(s, qemu_st_helpers[opc]);
>>
>> /* label2: */
>> diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
>> index d4bf6fe..01ef960 100644
>> --- a/tcg/hppa/tcg-target.h
>> +++ b/tcg/hppa/tcg-target.h
>> @@ -104,7 +104,6 @@ typedef enum {
>>
>> #define TCG_TARGET_HAS_GUEST_BASE
>>
>> -/* Note: must be synced with dyngen-exec.h */
>> #define TCG_AREG0 TCG_REG_R17
>>
>>
>> diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
>> index da17bba..34c2df8 100644
>> --- a/tcg/i386/tcg-target.c
>> +++ b/tcg/i386/tcg-target.c
>> @@ -183,9 +183,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> tcg_regset_set32(ct->u.regs, 0, 0xffff);
>> tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
>> tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
>> -#endif
>> } else {
>> tcg_regset_set32(ct->u.regs, 0, 0xff);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
>> @@ -965,7 +963,6 @@ static void tcg_out_jmp(TCGContext *s, tcg_target_long dest)
>>
>> #include "../../softmmu_defs.h"
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
>> int mmu_idx) */
>> static const void *qemu_ld_helpers[4] = {
>> @@ -983,25 +980,6 @@ static const void *qemu_st_helpers[4] = {
>> helper_stl_mmu,
>> helper_stq_mmu,
>> };
>> -#else
>> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
>> - mmu_idx) */
>> -static void *qemu_ld_helpers[4] = {
>> - __ldb_mmu,
>> - __ldw_mmu,
>> - __ldl_mmu,
>> - __ldq_mmu,
>> -};
>> -
>> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
>> - int mmu_idx) */
>> -static void *qemu_st_helpers[4] = {
>> - __stb_mmu,
>> - __stw_mmu,
>> - __stl_mmu,
>> - __stq_mmu,
>> -};
>> -#endif
>>
>> /* Perform the TLB load and compare.
>>
>> @@ -1220,16 +1198,13 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
>> }
>> tcg_out_push(s, args[addrlo_idx]);
>> stack_adjust += 4;
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_out_push(s, TCG_AREG0);
>> stack_adjust += 4;
>> -#endif
>> #else
>> /* The first argument is already loaded with addrlo. */
>> arg_idx = 1;
>> tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[arg_idx],
>> mem_index);
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* XXX/FIXME: suboptimal */
>> tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
>> tcg_target_call_iarg_regs[2]);
>> @@ -1240,7 +1215,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
>> tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
>> TCG_AREG0);
>> #endif
>> -#endif
>>
>> tcg_out_calli(s, (tcg_target_long)qemu_ld_helpers[s_bits]);
>>
>> @@ -1436,16 +1410,13 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
>> }
>> tcg_out_push(s, args[addrlo_idx]);
>> stack_adjust += 4;
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_out_push(s, TCG_AREG0);
>> stack_adjust += 4;
>> -#endif
>> #else
>> tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32),
>> tcg_target_call_iarg_regs[1], data_reg);
>> tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], mem_index);
>> stack_adjust = 0;
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* XXX/FIXME: suboptimal */
>> tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
>> tcg_target_call_iarg_regs[2]);
>> @@ -1456,7 +1427,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
>> tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
>> TCG_AREG0);
>> #endif
>> -#endif
>>
>> tcg_out_calli(s, (tcg_target_long)qemu_st_helpers[s_bits]);
>>
>> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
>> index c3cfe05..8be42f3 100644
>> --- a/tcg/i386/tcg-target.h
>> +++ b/tcg/i386/tcg-target.h
>> @@ -116,7 +116,6 @@ typedef enum {
>>
>> #define TCG_TARGET_HAS_GUEST_BASE
>>
>> -/* Note: must be synced with dyngen-exec.h */
>> #if TCG_TARGET_REG_BITS == 64
>> # define TCG_AREG0 TCG_REG_R14
>> #else
>> diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
>> index dc588db..1745038 100644
>> --- a/tcg/ia64/tcg-target.c
>> +++ b/tcg/ia64/tcg-target.c
>> @@ -1452,7 +1452,6 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
>> TCG_REG_P7, TCG_REG_R3, TCG_REG_R57));
>> }
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
>> int mmu_idx) */
>> static const void * const qemu_ld_helpers[4] = {
>> @@ -1461,16 +1460,6 @@ static const void * const qemu_ld_helpers[4] = {
>> helper_ldl_mmu,
>> helper_ldq_mmu,
>> };
>> -#else
>> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
>> - mmu_idx) */
>> -static void *qemu_ld_helpers[4] = {
>> - __ldb_mmu,
>> - __ldw_mmu,
>> - __ldl_mmu,
>> - __ldq_mmu,
>> -};
>> -#endif
>>
>> static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
>> {
>> @@ -1530,7 +1519,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
>> tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
>> tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
>> }
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* XXX/FIXME: suboptimal */
>> tcg_out_bundle(s, mII,
>> tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
>> @@ -1539,7 +1527,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
>> TCG_REG_R57, 0, TCG_REG_R56),
>> tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
>> TCG_REG_R56, 0, TCG_AREG0));
>> -#endif
>> if (!bswap || s_bits == 0) {
>> tcg_out_bundle(s, miB,
>> tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
>> @@ -1570,7 +1557,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
>> }
>> }
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
>> uintxx_t val, int mmu_idx) */
>> static const void * const qemu_st_helpers[4] = {
>> @@ -1579,16 +1565,6 @@ static const void * const qemu_st_helpers[4] = {
>> helper_stl_mmu,
>> helper_stq_mmu,
>> };
>> -#else
>> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
>> - int mmu_idx) */
>> -static void *qemu_st_helpers[4] = {
>> - __stb_mmu,
>> - __stw_mmu,
>> - __stl_mmu,
>> - __stq_mmu,
>> -};
>> -#endif
>>
>> static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
>> {
>> @@ -1658,7 +1634,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
>> data_reg = TCG_REG_R2;
>> }
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* XXX/FIXME: suboptimal */
>> tcg_out_bundle(s, mII,
>> tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
>> @@ -1674,15 +1649,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
>> TCG_REG_R56, 0, TCG_AREG0),
>> tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
>> TCG_REG_B0, TCG_REG_B6));
>> -#else
>> - tcg_out_bundle(s, miB,
>> - tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
>> - data_reg, TCG_REG_R3),
>> - tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
>> - mem_index, TCG_REG_R0),
>> - tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
>> - TCG_REG_B0, TCG_REG_B6));
>> -#endif
>> }
>>
>> #else /* !CONFIG_SOFTMMU */
>> diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
>> index 0631b9f..c22962a 100644
>> --- a/tcg/ia64/tcg-target.h
>> +++ b/tcg/ia64/tcg-target.h
>> @@ -140,7 +140,6 @@ typedef enum {
>> #define TCG_TARGET_HAS_not_i32 0 /* xor r1, -1, r3 */
>> #define TCG_TARGET_HAS_not_i64 0 /* xor r1, -1, r3 */
>>
>> -/* Note: must be synced with dyngen-exec.h */
>> #define TCG_AREG0 TCG_REG_R7
>>
>> /* Guest base is supported */
>> diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
>> index 1006e28..74db83d 100644
>> --- a/tcg/mips/tcg-target.c
>> +++ b/tcg/mips/tcg-target.c
>> @@ -217,7 +217,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> tcg_regset_set(ct->u.regs, 0xffffffff);
>> #if defined(CONFIG_SOFTMMU)
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
>> -# if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
>> +# if (TARGET_LONG_BITS == 64)
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
>> # endif
>> #endif
>> @@ -227,12 +227,11 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> tcg_regset_set(ct->u.regs, 0xffffffff);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
>> #if defined(CONFIG_SOFTMMU)
>> -# if (defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 32) || \
>> - (!defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 64)
>> +# if (TARGET_LONG_BITS == 32)
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
>> # endif
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
>> -# if defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 64
>> +# if TARGET_LONG_BITS == 64
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
>> # endif
>> #endif
>> @@ -821,7 +820,6 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond cond, int ret,
>>
>> #include "../../softmmu_defs.h"
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
>> int mmu_idx) */
>> static const void * const qemu_ld_helpers[4] = {
>> @@ -839,25 +837,6 @@ static const void * const qemu_st_helpers[4] = {
>> helper_stl_mmu,
>> helper_stq_mmu,
>> };
>> -#else
>> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
>> - mmu_idx) */
>> -static void *qemu_ld_helpers[4] = {
>> - __ldb_mmu,
>> - __ldw_mmu,
>> - __ldl_mmu,
>> - __ldq_mmu,
>> -};
>> -
>> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
>> - int mmu_idx) */
>> -static void *qemu_st_helpers[4] = {
>> - __stb_mmu,
>> - __stw_mmu,
>> - __stl_mmu,
>> - __stq_mmu,
>> -};
>> -#endif
>> #endif
>>
>> static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
>> @@ -942,9 +921,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
>>
>> /* slow path */
>> arg_num = 0;
>> -# ifdef CONFIG_TCG_PASS_AREG0
>> tcg_out_call_iarg_reg32(s, &arg_num, TCG_AREG0);
>> -# endif
>> # if TARGET_LONG_BITS == 64
>> tcg_out_call_iarg_reg64(s, &arg_num, addr_regl, addr_regh);
>> # else
>> @@ -1127,9 +1104,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
>>
>> /* slow path */
>> arg_num = 0;
>> -# ifdef CONFIG_TCG_PASS_AREG0
>> tcg_out_call_iarg_reg32(s, &arg_num, TCG_AREG0);
>> -# endif
>> # if TARGET_LONG_BITS == 64
>> tcg_out_call_iarg_reg64(s, &arg_num, addr_regl, addr_regh);
>> # else
>> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
>> index d3c804d..1c61931 100644
>> --- a/tcg/mips/tcg-target.h
>> +++ b/tcg/mips/tcg-target.h
>> @@ -96,7 +96,6 @@ typedef enum {
>> #define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
>> #define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
>>
>> -/* Note: must be synced with dyngen-exec.h */
>> #define TCG_AREG0 TCG_REG_S0
>>
>> /* guest base is supported */
>> diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
>> index 0cff181..26c4b33 100644
>> --- a/tcg/ppc/tcg-target.c
>> +++ b/tcg/ppc/tcg-target.c
>> @@ -248,7 +248,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
>> #if TARGET_LONG_BITS == 64
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
>> @@ -256,11 +255,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
>> #endif
>> #endif
>> -#else /* !AREG0 */
>> -#if TARGET_LONG_BITS == 64
>> - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
>> -#endif
>> -#endif
>> break;
>> case 'K': /* qemu_st[8..32] constraint */
>> ct->ct |= TCG_CT_REG;
>> @@ -268,7 +262,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
>> #if TARGET_LONG_BITS == 64
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
>> @@ -276,11 +269,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
>> #endif
>> #endif
>> -#else /* !AREG0 */
>> -#if TARGET_LONG_BITS == 64
>> - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
>> -#endif
>> -#endif
>> break;
>> case 'M': /* qemu_st64 constraint */
>> ct->ct |= TCG_CT_REG;
>> @@ -290,12 +278,10 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
>> -#if defined(CONFIG_TCG_PASS_AREG0)
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
>> #ifdef TCG_TARGET_CALL_ALIGN_ARGS
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9);
>> #endif
>> -#endif
>> break;
>> #else
>> case 'L':
>> @@ -541,7 +527,6 @@ static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
>>
>> #include "../../softmmu_defs.h"
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
>> int mmu_idx) */
>> static const void * const qemu_ld_helpers[4] = {
>> @@ -559,25 +544,6 @@ static const void * const qemu_st_helpers[4] = {
>> helper_stl_mmu,
>> helper_stq_mmu,
>> };
>> -#else
>> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
>> - mmu_idx) */
>> -static void *qemu_ld_helpers[4] = {
>> - __ldb_mmu,
>> - __ldw_mmu,
>> - __ldl_mmu,
>> - __ldq_mmu,
>> -};
>> -
>> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
>> - mmu_idx) */
>> -static void *qemu_st_helpers[4] = {
>> - __stb_mmu,
>> - __stw_mmu,
>> - __stl_mmu,
>> - __stq_mmu,
>> -};
>> -#endif
>> #endif
>>
>> static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
>> @@ -647,9 +613,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
>>
>> /* slow path */
>> ir = 3;
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
>> -#endif
>> #if TARGET_LONG_BITS == 32
>> tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
>> #else
>> @@ -849,9 +813,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
>>
>> /* slow path */
>> ir = 3;
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
>> -#endif
>> #if TARGET_LONG_BITS == 32
>> tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
>> #else
>> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
>> index 27a0ae8..337cd41 100644
>> --- a/tcg/ppc64/tcg-target.c
>> +++ b/tcg/ppc64/tcg-target.c
>> @@ -235,10 +235,8 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
>> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
>> #ifdef CONFIG_SOFTMMU
>> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
>> #endif
>> -#endif
>> break;
>> case 'S': /* qemu_st constraint */
>> ct->ct |= TCG_CT_REG;
>> @@ -247,10 +245,8 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
>> #ifdef CONFIG_SOFTMMU
>> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
>> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6);
>> #endif
>> -#endif
>> break;
>> case 'Z':
>> ct->ct |= TCG_CT_CONST_U32;
>> @@ -558,7 +554,6 @@ static void tcg_out_ldsta (TCGContext *s, int ret, int addr,
>>
>> #include "../../softmmu_defs.h"
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
>> int mmu_idx) */
>> static const void * const qemu_ld_helpers[4] = {
>> @@ -576,25 +571,6 @@ static const void * const qemu_st_helpers[4] = {
>> helper_stl_mmu,
>> helper_stq_mmu,
>> };
>> -#else
>> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
>> - mmu_idx) */
>> -static void *qemu_ld_helpers[4] = {
>> - __ldb_mmu,
>> - __ldw_mmu,
>> - __ldl_mmu,
>> - __ldq_mmu,
>> -};
>> -
>> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
>> - int mmu_idx) */
>> -static void *qemu_st_helpers[4] = {
>> - __stb_mmu,
>> - __stw_mmu,
>> - __stl_mmu,
>> - __stq_mmu,
>> -};
>> -#endif
>>
>> static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
>> int addr_reg, int s_bits, int offset)
>> @@ -676,9 +652,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
>>
>> /* slow path */
>> ir = 3;
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
>> -#endif
>> tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
>> tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
>>
>> @@ -827,9 +801,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
>>
>> /* slow path */
>> ir = 3;
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
>> -#endif
>> tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
>> tcg_out_rld (s, RLDICL, ir++, data_reg, 0, 64 - (1 << (3 + opc)));
>> tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
>> diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
>> index 04662c1..965e1d4 100644
>> --- a/tcg/s390/tcg-target.c
>> +++ b/tcg/s390/tcg-target.c
>> @@ -301,7 +301,6 @@ static const uint8_t tcg_cond_to_ltr_cond[10] = {
>>
>> #include "../../softmmu_defs.h"
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
>> int mmu_idx) */
>> static const void * const qemu_ld_helpers[4] = {
>> @@ -319,25 +318,6 @@ static const void * const qemu_st_helpers[4] = {
>> helper_stl_mmu,
>> helper_stq_mmu,
>> };
>> -#else
>> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
>> - mmu_idx) */
>> -static void *qemu_ld_helpers[4] = {
>> - __ldb_mmu,
>> - __ldw_mmu,
>> - __ldl_mmu,
>> - __ldq_mmu,
>> -};
>> -
>> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
>> - int mmu_idx) */
>> -static void *qemu_st_helpers[4] = {
>> - __stb_mmu,
>> - __stw_mmu,
>> - __stl_mmu,
>> - __stq_mmu,
>> -};
>> -#endif
>> #endif
>>
>> static uint8_t *tb_ret_addr;
>> @@ -1507,7 +1487,6 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
>> tcg_abort();
>> }
>> tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, mem_index);
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* XXX/FIXME: suboptimal */
>> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2],
>> tcg_target_call_iarg_regs[1]);
>> @@ -1515,11 +1494,9 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
>> tcg_target_call_iarg_regs[0]);
>> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
>> TCG_AREG0);
>> -#endif
>> tgen_calli(s, (tcg_target_ulong)qemu_st_helpers[s_bits]);
>> } else {
>> tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* XXX/FIXME: suboptimal */
>> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
>> tcg_target_call_iarg_regs[2]);
>> @@ -1529,7 +1506,6 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
>> tcg_target_call_iarg_regs[0]);
>> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
>> TCG_AREG0);
>> -#endif
>> tgen_calli(s, (tcg_target_ulong)qemu_ld_helpers[s_bits]);
>>
>> /* sign extension */
>> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
>> index d12f90b..4f7dfab 100644
>> --- a/tcg/s390/tcg-target.h
>> +++ b/tcg/s390/tcg-target.h
>> @@ -96,7 +96,6 @@ typedef enum TCGReg {
>> #define TCG_TARGET_EXTEND_ARGS 1
>>
>> enum {
>> - /* Note: must be synced with dyngen-exec.h */
>> TCG_AREG0 = TCG_REG_R10,
>> };
>>
>> diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
>> index 247a278..baed3b4 100644
>> --- a/tcg/sparc/tcg-target.c
>> +++ b/tcg/sparc/tcg-target.c
>> @@ -59,11 +59,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
>> };
>> #endif
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> #define ARG_OFFSET 1
>> -#else
>> -#define ARG_OFFSET 0
>> -#endif
>>
>> static const int tcg_target_reg_alloc_order[] = {
>> TCG_REG_L0,
>> @@ -161,9 +157,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_regset_reset_reg(ct->u.regs, TCG_REG_O3);
>> -#endif
>> break;
>> case 'I':
>> ct->ct |= TCG_CT_CONST_S11;
>> @@ -715,7 +709,6 @@ static void tcg_target_qemu_prologue(TCGContext *s)
>>
>> #include "../../softmmu_defs.h"
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
>> int mmu_idx) */
>> static const void * const qemu_ld_helpers[4] = {
>> @@ -733,25 +726,6 @@ static const void * const qemu_st_helpers[4] = {
>> helper_stl_mmu,
>> helper_stq_mmu,
>> };
>> -#else
>> -/* legacy helper signature: __ld_mmu(target_ulong addr, int
>> - mmu_idx) */
>> -static const void * const qemu_ld_helpers[4] = {
>> - __ldb_mmu,
>> - __ldw_mmu,
>> - __ldl_mmu,
>> - __ldq_mmu,
>> -};
>> -
>> -/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
>> - int mmu_idx) */
>> -static const void * const qemu_st_helpers[4] = {
>> - __stb_mmu,
>> - __stw_mmu,
>> - __stl_mmu,
>> - __stq_mmu,
>> -};
>> -#endif
>> #endif
>>
>> #if TARGET_LONG_BITS == 32
>> @@ -834,7 +808,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
>>
>> /* mov */
>> tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* XXX/FIXME: suboptimal */
>> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
>> tcg_target_call_iarg_regs[2]);
>> @@ -844,7 +817,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
>> tcg_target_call_iarg_regs[0]);
>> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
>> TCG_AREG0);
>> -#endif
>>
>> /* XXX: move that code at the end of the TB */
>> /* qemu_ld_helper[s_bits](arg0, arg1) */
>> @@ -1061,7 +1033,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
>> /* mov */
>> tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
>>
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> /* XXX/FIXME: suboptimal */
>> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
>> tcg_target_call_iarg_regs[2]);
>> @@ -1071,7 +1042,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
>> tcg_target_call_iarg_regs[0]);
>> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
>> TCG_AREG0);
>> -#endif
>> /* XXX: move that code at the end of the TB */
>> /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
>> tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
>> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
>> index ee2274d..0ea87be 100644
>> --- a/tcg/sparc/tcg-target.h
>> +++ b/tcg/sparc/tcg-target.h
>> @@ -125,7 +125,6 @@ typedef enum {
>> #define TCG_TARGET_HAS_deposit_i64 0
>> #endif
>>
>> -/* Note: must be synced with dyngen-exec.h */
>> #ifdef CONFIG_SOLARIS
>> #define TCG_AREG0 TCG_REG_G2
>> #elif defined(__sparc_v9__)
>> diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c
>> index ef8580f..003244c 100644
>> --- a/tcg/tci/tcg-target.c
>> +++ b/tcg/tci/tcg-target.c
>> @@ -798,9 +798,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
>> case INDEX_op_qemu_st8:
>> case INDEX_op_qemu_st16:
>> case INDEX_op_qemu_st32:
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_out_r(s, TCG_AREG0);
>> -#endif
>> tcg_out_r(s, *args++);
>> tcg_out_r(s, *args++);
>> #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
>> @@ -811,9 +809,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
>> #endif
>> break;
>> case INDEX_op_qemu_st64:
>> -#ifdef CONFIG_TCG_PASS_AREG0
>> tcg_out_r(s, TCG_AREG0);
>> -#endif
>> tcg_out_r(s, *args++);
>> #if TCG_TARGET_REG_BITS == 32
>> tcg_out_r(s, *args++);
>> diff --git a/tci.c b/tci.c
>> index c79350d..ce8a988 100644
>> --- a/tci.c
>> +++ b/tci.c
>> @@ -25,7 +25,6 @@
>> #endif
>>
>> #include "qemu-common.h"
>> -#include "dyngen-exec.h" /* env */
>> #include "exec-all.h" /* MAX_OPC_PARAM_IARGS */
>> #include "tcg-op.h"
>>
>> @@ -63,17 +62,6 @@ uintptr_t tci_tb_ptr;
>>
>> static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
>>
>> -#if !defined(CONFIG_TCG_PASS_AREG0)
>> -# define helper_ldb_mmu(env, addr, mmu_idx) __ldb_mmu(addr, mmu_idx)
>> -# define helper_ldw_mmu(env, addr, mmu_idx) __ldw_mmu(addr, mmu_idx)
>> -# define helper_ldl_mmu(env, addr, mmu_idx) __ldl_mmu(addr, mmu_idx)
>> -# define helper_ldq_mmu(env, addr, mmu_idx) __ldq_mmu(addr, mmu_idx)
>> -# define helper_stb_mmu(env, addr, val, mmu_idx) __stb_mmu(addr, val, mmu_idx)
>> -# define helper_stw_mmu(env, addr, val, mmu_idx) __stw_mmu(addr, val, mmu_idx)
>> -# define helper_stl_mmu(env, addr, val, mmu_idx) __stl_mmu(addr, val, mmu_idx)
>> -# define helper_stq_mmu(env, addr, val, mmu_idx) __stq_mmu(addr, val, mmu_idx)
>> -#endif /* !CONFIG_TCG_PASS_AREG0 */
>> -
>> static tcg_target_ulong tci_read_reg(TCGReg index)
>> {
>> assert(index < ARRAY_SIZE(tci_reg));
>> diff --git a/user-exec.c b/user-exec.c
>> index b9ea9dd..ef9b172 100644
>> --- a/user-exec.c
>> +++ b/user-exec.c
>> @@ -18,9 +18,6 @@
>> */
>> #include "config.h"
>> #include "cpu.h"
>> -#ifndef CONFIG_TCG_PASS_AREG0
>> -#include "dyngen-exec.h"
>> -#endif
>> #include "disas.h"
>> #include "tcg.h"
>>
>> @@ -60,12 +57,6 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc)
>> struct sigcontext *uc = puc;
>> #endif
>>
>> -#ifndef CONFIG_TCG_PASS_AREG0
>> - env = env1;
>> -
>> - /* XXX: restore cpu registers saved in host registers */
>> -#endif
>> -
>> if (puc) {
>> /* XXX: use siglongjmp ? */
>> #ifdef __linux__
>> @@ -93,11 +84,6 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
>> TranslationBlock *tb;
>> int ret;
>>
>> -#ifndef CONFIG_TCG_PASS_AREG0
>> - if (cpu_single_env) {
>> - env = cpu_single_env; /* XXX: find a correct solution for multithread */
>> - }
>> -#endif
>> #if defined(DEBUG_SIGNAL)
>> qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
>> pc, address, is_write, *(unsigned long *)old_set);
>> --
>> 1.7.2.5
>>
>>
>>
>
> --
> Aurelien Jarno GPG: 1024D/F1BCDB73
> aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [Qemu-devel] [PATCH 00/21] AREG0 patches, final round
2012-09-02 17:33 [Qemu-devel] [PATCH 00/21] AREG0 patches, final round Blue Swirl
` (20 preceding siblings ...)
2012-09-02 17:33 ` [Qemu-devel] [PATCH 21/21] Remove unused CONFIG_TCG_PASS_AREG0 and dead code Blue Swirl
@ 2012-09-04 18:52 ` Richard Henderson
21 siblings, 0 replies; 64+ messages in thread
From: Richard Henderson @ 2012-09-04 18:52 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel
On 09/02/2012 10:33 AM, Blue Swirl wrote:
> target-s390x: fix style
> target-s390x: split FPU ops
> target-s390x: split condition code helpers
> target-s390x: split integer helpers
> target-s390x: split memory access helpers
> target-s390x: rename op_helper.c to misc_helper.c
> target-s390x: avoid AREG0 for FPU helpers
> target-s390x: avoid AREG0 for integer helpers
> target-s390x: avoid AREG0 for condition code helpers
> target-s390x: avoid AREG0 for misc helpers
> target-s390x: switch to AREG0 free mode
> target-s390x: split helper.c
Reviewed-by: Richard Henderson <rth@twiddle.net>
> Remove unused CONFIG_TCG_PASS_AREG0 and dead code
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
^ permalink raw reply [flat|nested] 64+ messages in thread