From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:51494) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TB5KG-0006Ok-KU for qemu-devel@nongnu.org; Mon, 10 Sep 2012 10:51:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TB5KC-0004XV-8c for qemu-devel@nongnu.org; Mon, 10 Sep 2012 10:51:00 -0400 Received: from hub021-nj-7.exch021.serverdata.net ([206.225.164.223]:41645) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TB5KC-0004XL-4L for qemu-devel@nongnu.org; Mon, 10 Sep 2012 10:50:56 -0400 Message-ID: <504DFE4E.4030106@CloudSwitch.Com> Date: Mon, 10 Sep 2012 10:50:54 -0400 From: Don Slutz MIME-Version: 1.0 References: <1346877673-9136-1-git-send-email-ehabkost@redhat.com> <1346877673-9136-5-git-send-email-ehabkost@redhat.com> <20120910141838.19636d67@nial.usersys.redhat.com> <20120910143149.500ba268@nial.usersys.redhat.com> <20120910150430.7a425e92@nial.usersys.redhat.com> In-Reply-To: <20120910150430.7a425e92@nial.usersys.redhat.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Igor Mammedov Cc: qemu-devel@nongnu.org, Peter Maydell , =?ISO-8859-1?Q?Andreas_F=E4?= =?ISO-8859-1?Q?rber?= , Anthony Liguori , Eduardo Habkost On 09/10/12 09:04, Igor Mammedov wrote: > On Mon, 10 Sep 2012 14:31:49 +0200 > Igor Mammedov wrote: > >> On Mon, 10 Sep 2012 14:18:38 +0200 >> Igor Mammedov wrote: >> >>> On Wed, 5 Sep 2012 17:41:10 -0300 >>> Eduardo Habkost wrote: >>> >>>> Those models are maintained by QEMU and may require compatibility code >>>> to be added when making some changes. Keeping the data in the C source >>>> code should make it simpler to handle those details. >>>> >>>> Signed-off-by: Eduardo Habkost >>>> --- >>>> sysconfigs/target/cpus-x86_64.conf | 129 +--------------------- >>>> target-i386/cpu.c | 219 >>>> +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 >>>> insertions(+), 128 deletions(-) >>>> >>>> diff --git a/sysconfigs/target/cpus-x86_64.conf >>>> b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644 >>>> --- a/sysconfigs/target/cpus-x86_64.conf >>>> +++ b/sysconfigs/target/cpus-x86_64.conf >>>> @@ -1,128 +1 @@ >>>> -# x86 CPU MODELS >>>> - >>>> -[cpudef] >>>> - name =3D "Conroe" >>>> - level =3D "2" >>>> - vendor =3D "GenuineIntel" >>>> - family =3D "6" >>>> - model =3D "2" >>>> - stepping =3D "3" >>>> - feature_edx =3D "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge = mtrr >>>> sep apic cx8 mce pae msr tsc pse de fpu" >>>> - feature_ecx =3D "ssse3 sse3" >>>> - extfeature_edx =3D "i64 xd syscall" >>> ... >>>> + .ext2_features =3D CPUID_EXT2_LM | CPUID_EXT2_NX | >>>> CPUID_EXT2_SYSCALL, >>> Silent fix, replacing i64 with CPUID_EXT2_LM >>> looks like "i64" is mistake and never worked. In Intel & AMD cpuid guid= es >> Actually it works when setting feature fields because it uses >> setfeatures(), however setting i64 will set wrong bit if it's set using >> add_flagname_to_bitmaps() > I'm wrong, and sorry for noise. I mixed up ia64 from feature_name with i6= 4 > from ext2_feature_name. > > But question unrelated to this patch is still stand if ia64 is valid bit = for > 01.EDX[30]? > > Intel=AE Processor Identification and the CPUID Instruction Application Note 485 January 2006 Order Number: 241618-030 ... Updated Table 3-5 to include the feature flag definition (EDX[30]) for=20 IA64 capabilities. ... 30 IA64 IA64 Capabilities The processor is a member of the Intel=AE=20 Itanium=AE processor family and currently operating in IA32 emulation mode. --------------- Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and=20 http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64) But the newest version I found (241618-037, January 2011) is back to=20 Reserved. -Don Slutz