From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:33889) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TCGzh-0006qM-QN for qemu-devel@nongnu.org; Thu, 13 Sep 2012 17:30:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TCGzg-0000C5-7T for qemu-devel@nongnu.org; Thu, 13 Sep 2012 17:30:41 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:34012) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TCGzg-0000Bo-16 for qemu-devel@nongnu.org; Thu, 13 Sep 2012 17:30:40 -0400 Received: by pbbrp12 with SMTP id rp12so4815827pbb.4 for ; Thu, 13 Sep 2012 14:30:39 -0700 (PDT) Sender: Richard Henderson Message-ID: <5052507C.7010603@twiddle.net> Date: Thu, 13 Sep 2012 14:30:36 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1347557866-7256-1-git-send-email-sw@weilnetz.de> <1347557866-7256-3-git-send-email-sw@weilnetz.de> <20120913212157.GA840@ohm.aurel32.net> In-Reply-To: <20120913212157.GA840@ohm.aurel32.net> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/4] tcg/i386: Add shortcuts for registers used in L constraint List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: Peter Maydell , Stefan Weil , qemu-devel@nongnu.org, Alexander Graf , Blue Swirl On 09/13/2012 02:21 PM, Aurelien Jarno wrote: >> > #if TCG_TARGET_REG_BITS == 32 >> > tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, >> > (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); >> > - tcg_out_ld(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[1], TCG_REG_ESP, >> > + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L1, TCG_REG_ESP, >> > (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4); >> > #else >> > - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); >> > + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_L0); >> > #endif >> > tcg_out_addi(s, TCG_REG_ESP, -stack_addend); >> > >> > /* jmp *tb. */ >> > - tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); >> > + tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_L1); > I don't think this is correct here. This has nothing to do with the L > constraint, it's really refers to the first and seconds argument passed > to the prologue. > In the 32-bit case, our use of TCG_REG_L1 really is just a temporary. We loaded it from the stack just above there. For the 64-bit case you're right. But that's exactly how we set up the Ln macros, so I think that's ok. r~