From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37679) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDelo-0006aw-4l for qemu-devel@nongnu.org; Mon, 17 Sep 2012 13:06:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TDelb-0003U6-5y for qemu-devel@nongnu.org; Mon, 17 Sep 2012 13:06:04 -0400 Received: from mail-qa0-f45.google.com ([209.85.216.45]:40429) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDela-0003Tp-Vu for qemu-devel@nongnu.org; Mon, 17 Sep 2012 13:05:51 -0400 Received: by qadc10 with SMTP id c10so1698954qad.4 for ; Mon, 17 Sep 2012 10:05:50 -0700 (PDT) Sender: Richard Henderson Message-ID: <5057586A.6010809@twiddle.net> Date: Mon, 17 Sep 2012 10:05:46 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1347895732-22212-1-git-send-email-rth@twiddle.net> <1347895732-22212-5-git-send-email-rth@twiddle.net> <50574A07.5030009@suse.de> In-Reply-To: <50574A07.5030009@suse.de> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 04/13] tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-15?Q?Andreas_F=E4rber?= Cc: blauwirbel@gmail.com, qemu-devel@nongnu.org On 09/17/2012 09:04 AM, Andreas Färber wrote: > Without knowing the code, this does not strike me as the best of ideas: > SPARC CPUs are rather uncommon these days, so being able to emulate it > in sparc32-softmmu may be helpful for keeping it working. > > Could you elaborate on what exactly is broken and what would need to be > done as alternative? See, for instance, patch 2. INDEX_op_qemu_ld64 and INDEX_op_qemu_st64 were unimplemented, caught during tcg startup with --enable-tcg-debug, and crashing later without. Handling only sparcv9 host cpus means that lots of code paths are able to be cleaned up: (1) Multiply and divide insns are available (Conditional support for these is not easy.) (2) Endian-swapping load/store insns are available (Vastly cleans up qemu_ld/st; by the end of my patch set the fast path through the tlb is a single insn in the delay slot of the branch over the call to the helper.) (3) Conditional move insns are available (For setcond this is tidier than playing subtract-with-borrow games). But sparcv9 is now coming up on 20 years old. The amount of hardware still live that isn't v9 capable is bound to be vanishingly small -- in much the same way that i386 hosts without i486 bswap. I don't think we need to use the QEMU TCG code generator as a test case that keeps sparcv7 code alive. r~