From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:57406) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TEIYo-0005u1-O8 for qemu-devel@nongnu.org; Wed, 19 Sep 2012 07:35:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TEIYn-000436-AM for qemu-devel@nongnu.org; Wed, 19 Sep 2012 07:35:18 -0400 Received: from mx1.redhat.com ([209.132.183.28]:14344) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TEIYn-00042U-1l for qemu-devel@nongnu.org; Wed, 19 Sep 2012 07:35:17 -0400 Message-ID: <5059ADED.9000504@redhat.com> Date: Wed, 19 Sep 2012 13:35:09 +0200 From: Gerd Hoffmann MIME-Version: 1.0 References: <1347961897-28554-1-git-send-email-kraxel@redhat.com> <50598D7E.8010909@redhat.com> In-Reply-To: <50598D7E.8010909@redhat.com> Content-Type: multipart/mixed; boundary="------------000907050405070608060304" Subject: Re: [Qemu-devel] [RfC PATCH] vga: add mmio bar to standard vga List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org This is a multi-part message in MIME format. --------------000907050405070608060304 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit >> + * 0x0400 -> 0x041f vga ioports (0x3c0 -> 0x3df), remapped 1:1 > > Do they support word accesses to set both index and data? > >> + * 0x0500 -> 0x0515 bochs dispi interface registers, mapped flat without >> + * index/data ports. Use (index << 1) as offset for >> + * (16bit) register access. >> + */ > > BAR should disappear with -M old. Sure. I have a patch in flight which adds the pc-1.3 machine type, once this is in I can easily add the compat stuff. >> +static const MemoryRegionOps pci_vga_ioport_ops = { >> + .read = pci_vga_ioport_read, >> + .write = pci_vga_ioport_write, >> + .valid.min_access_size = 1, >> + .valid.max_access_size = 4, >> + .impl.min_access_size = 1, >> + .impl.max_access_size = 1, >> + .endianness = DEVICE_LITTLE_ENDIAN, >> +}; > > Looks like word writes are supported provided the memory API breaks up > writes in little endian order. Better to make it explicit. Like the attached incremental patch? cheers, Gerd --------------000907050405070608060304 Content-Type: text/plain; name="0001-fixup-vga-mmio.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0001-fixup-vga-mmio.patch" >>From d46b14dfd74dcc37fe187dc76cd681ad7dbff2d5 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Wed, 19 Sep 2012 13:31:04 +0200 Subject: [PATCH] [fixup] vga mmio Signed-off-by: Gerd Hoffmann --- hw/vga-pci.c | 25 ++++++++++++++++++++++--- 1 files changed, 22 insertions(+), 3 deletions(-) diff --git a/hw/vga-pci.c b/hw/vga-pci.c index e05e2ef..7fd305d 100644 --- a/hw/vga-pci.c +++ b/hw/vga-pci.c @@ -78,14 +78,33 @@ static uint64_t pci_vga_ioport_read(void *ptr, target_phys_addr_t addr, unsigned size) { PCIVGAState *d = ptr; - return vga_ioport_read(&d->vga, addr); + uint64_t ret = 0; + + switch (size) { + case 1: + ret = vga_ioport_read(&d->vga, addr); + break; + case 2: + ret = vga_ioport_read(&d->vga, addr); + ret |= vga_ioport_read(&d->vga, addr+1) << 8; + break; + } + return ret; } static void pci_vga_ioport_write(void *ptr, target_phys_addr_t addr, uint64_t val, unsigned size) { PCIVGAState *d = ptr; - vga_ioport_write(&d->vga, addr, val); + switch (size) { + case 1: + vga_ioport_write(&d->vga, addr, val); + break; + case 2: + vga_ioport_write(&d->vga, addr, val & 0xff); + vga_ioport_write(&d->vga, addr+1, (val >> 8) & 0xff); + break; + } } static const MemoryRegionOps pci_vga_ioport_ops = { @@ -94,7 +113,7 @@ static const MemoryRegionOps pci_vga_ioport_ops = { .valid.min_access_size = 1, .valid.max_access_size = 4, .impl.min_access_size = 1, - .impl.max_access_size = 1, + .impl.max_access_size = 2, .endianness = DEVICE_LITTLE_ENDIAN, }; -- 1.7.1 --------------000907050405070608060304--