Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions

[Weiwei Li <liweiwei@iscas.ac.cn>]

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在 2022/4/27 上午10:07, eop Chen 写道:
>
>
>>
>> 在 2022/4/27 上午2:20, eop Chen 写道:
>>>
>>>> Weiwei Li <liweiwei@iscas.ac.cn <mailto:liweiwei@iscas.ac.cn>> 於 
>>>> 2022年4月26日 下午4:47 寫道：
>>>> 在 2022/3/17 下午3:26, ~eopxd 写道:
>>>>> From: Yueh-Ting (eop) Chen<eop.chen@sifive.com>
>>>>>
>>>>> This is the first commit regarding the mask agnostic behavior.
>>>>> Added option 'rvv_ma_all_1s' to enable the behavior, the option
>>>>> is default to false.
>>>>>
>>>>> Signed-off-by: eop Chen<eop.chen@sifive.com>
>>>>> Reviewed-by: Frank Chang<frank.chang@sifive.com>
>>>>
>>>> Similar to our last discussion, vext_set_elems_1s_fns array can be 
>>>> simplified to single vext_set_elems_1s,
>>>>
>>>> since the fourth argement can be used as the start offset.
>>>>
>>>> Another question, may be not related to this patchset, in section 
>>>> 3.4.3 of the spec:
>>>>
>>>> /"Mask destination tail elements are always treated as 
>>>> tail-agnostic, regardless of the setting of vta."/
>>>>
>>>> What does "Mask destination tail elements" mean?
>>>>
>>>> Regards,
>>>>
>>>> Weiwei Li
>>>>
>>>
>>> I have just updated a new version for the tail agnostic patch set, 
>>> it also includes a bug fix discovered today.
>>>
>>> Regarding the question, mask / masked-off are for body elements and 
>>> respects the mask policy, and tail elements respect the tail policy.
>>>
>>> Regards,
>>>
>>> eop Chen
>>
>> I find another descriptions in the spec. For the instructions that 
>> write mask register (such as vmadc, vmseq,vmsne,vmfeq...), they all 
>> have similar description
>>
>> (You can search "tail-agnostic" in the spec):
>>
>> /Section 11.4: "Because these instructions produce a mask value, they 
>> always operate with a tail-agnostic policy"//
>> /
>>
>> /Section 11.8/13.13: "Compares //write mask registers, and so always 
>> operate under a tail-agnostic policy"//
>> /
>>
>> /Section 15.1: "Mask elements past vl, the tail elements, are always 
>> updated with a tail-agnostic policy"//
>> /
>>
>> //
>>
>> /Section 15.4/15.5/15.6: "The tail elements in the destination mask 
>> register are updated under a tail-agnostic policy"/
>>
>> So I think "Mask destination tail elements" may means the tail 
>> element for instructions that take mask register as destination 
>> register.  For these instructions,
>>
>> maybe the setting of VTA can be ignored.
>>
>> Regards,
>>
>> Weiwei Li
>>
>
> Yes, the setting of VTA should be ignored when v-spec specifies.
> I think the implementation of the tail agnostic patch set don’t need 
> to change on this.

Sorry. I don't get your idea?

In current patch, these instructions seems need to set the tail elements 
to 1s when vta is true which means

VTA is setted and rvv_ta_all_1s is enabled. If setting of VTA should be 
ignored for these instrucitons,

they will set the tail elements to 1s only when rvv_ta_all_1s is enabled.

Regards,

Weiwei Li

>
> Regards,
>
> eop Chen
>
>
>

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