From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:34886) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLH1Y-00071o-9M for qemu-devel@nongnu.org; Mon, 08 Oct 2012 13:21:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLH1V-0001nf-Cj for qemu-devel@nongnu.org; Mon, 08 Oct 2012 13:21:47 -0400 Message-ID: <50730BA3.5000005@suse.de> Date: Mon, 08 Oct 2012 19:21:39 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1349714816-12618-1-git-send-email-Bharat.Bhushan@freescale.com> <1349714816-12618-3-git-send-email-Bharat.Bhushan@freescale.com> In-Reply-To: <1349714816-12618-3-git-send-email-Bharat.Bhushan@freescale.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 2/3] e500: Adding CCSR memory region List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bharat Bhushan , agraf@suse.de, Avi Kivity Cc: Bharat Bhushan , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Am 08.10.2012 18:46, schrieb Bharat Bhushan: > All devices are also placed under CCSR memory region. > The CCSR memory region is exported to pci device. The MSI interrupt > generation is the main reason to export the CCSR region to PCI device. > This put the requirement to move mpic under CCSR region, but logically > all devices should be under CCSR. So this patch places all emulated > devices under ccsr region. >=20 > Signed-off-by: Bharat Bhushan > --- > hw/ppc/e500.c | 61 +++++++++++++++++++++++++++++++++++--------------= ------- > 1 files changed, 38 insertions(+), 23 deletions(-) >=20 > diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c > index 1949c81..b3e6a1e 100644 > --- a/hw/ppc/e500.c > +++ b/hw/ppc/e500.c > @@ -46,14 +46,16 @@ > /* TODO: parameterize */ > #define MPC8544_CCSRBAR_BASE 0xE0000000ULL > #define MPC8544_CCSRBAR_SIZE 0x00100000ULL > -#define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000ULL) > -#define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500ULL) > -#define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600ULL) > -#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000ULL) > +#define MPC8544_MPIC_REGS_OFFSET 0x40000ULL > +#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL > +#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL > +#define MPC8544_PCI_REGS_OFFSET 0x8000ULL > +#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \ > + MPC8544_PCI_REGS_OFFSET) > #define MPC8544_PCI_REGS_SIZE 0x1000ULL > #define MPC8544_PCI_IO 0xE1000000ULL > #define MPC8544_PCI_IOLEN 0x10000ULL > -#define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000ULL) > +#define MPC8544_UTIL_OFFSET 0xe0000ULL > #define MPC8544_SPIN_BASE 0xEF000000ULL > =20 > struct boot_info > @@ -268,13 +270,12 @@ static int ppce500_load_device_tree(CPUPPCState *= env, > /* XXX should contain a reasonable value */ > qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); > =20 > - snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, > - MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE); > + snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS= _OFFSET); > qemu_devtree_add_subnode(fdt, mpic); > qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic"); > qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pi= c"); > - qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_BAS= E - > - MPC8544_CCSRBAR_BASE, 0x40000); > + qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFF= SET, > + 0x40000); > qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0); > qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2); > mpic_ph =3D qemu_devtree_alloc_phandle(fdt); > @@ -287,17 +288,16 @@ static int ppce500_load_device_tree(CPUPPCState *= env, > * device it finds in the dt as serial output device. And we gener= ate > * devices in reverse order to the dt. > */ > - dt_serial_create(fdt, MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_= BASE, > + dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, > soc, mpic, "serial1", 1, false); > - dt_serial_create(fdt, MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_= BASE, > + dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, > soc, mpic, "serial0", 0, true); > =20 > snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, > - MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE); > + MPC8544_UTIL_OFFSET); > qemu_devtree_add_subnode(fdt, gutil); > qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544= -guts"); > - qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_BASE - > - MPC8544_CCSRBAR_BASE, 0x1000); > + qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET,= 0x1000); > qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); > =20 > snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); > @@ -423,6 +423,8 @@ void ppce500_init(PPCE500Params *params) > qemu_irq **irqs, *mpic; > DeviceState *dev; > CPUPPCState *firstenv =3D NULL; > + MemoryRegion *ccsr; > + SysBusDevice *s; > =20 > /* Setup CPUs */ > if (params->cpu_model =3D=3D NULL) { > @@ -451,7 +453,8 @@ void ppce500_init(PPCE500Params *params) > irqs[i][OPENPIC_OUTPUT_INT] =3D input[PPCE500_INPUT_INT]; > irqs[i][OPENPIC_OUTPUT_CINT] =3D input[PPCE500_INPUT_CINT]; > env->spr[SPR_BOOKE_PIR] =3D env->cpu_index =3D i; > - env->mpic_cpu_base =3D MPC8544_MPIC_REGS_BASE + 0x20000; > + env->mpic_cpu_base =3D MPC8544_CCSRBAR_BASE + > + MPC8544_MPIC_REGS_OFFSET + 0x20000; > =20 > ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500); > =20 > @@ -478,8 +481,12 @@ void ppce500_init(PPCE500Params *params) > vmstate_register_ram_global(ram); > memory_region_add_subregion(address_space_mem, 0, ram); > =20 > + ccsr =3D g_malloc0(sizeof(MemoryRegion)); > + memory_region_init(ccsr, "e500-cssr", MPC8544_CCSRBAR_SIZE); > + memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BAS= E, ccsr); > + > /* MPIC */ > - mpic =3D mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, > + mpic =3D mpic_init(ccsr, MPC8544_MPIC_REGS_OFFSET, > smp_cpus, irqs, NULL); > =20 > if (!mpic) { > @@ -488,25 +495,33 @@ void ppce500_init(PPCE500Params *params) > =20 > /* Serial */ > if (serial_hds[0]) { > - serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE, > + serial_mm_init(ccsr, MPC8544_SERIAL0_REGS_OFFSET, > 0, mpic[12+26], 399193, > serial_hds[0], DEVICE_BIG_ENDIAN); > } > =20 > if (serial_hds[1]) { > - serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE, > + serial_mm_init(ccsr, MPC8544_SERIAL1_REGS_OFFSET, > 0, mpic[12+26], 399193, > serial_hds[1], DEVICE_BIG_ENDIAN); > } > =20 > /* General Utility device */ > - sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL); > + dev =3D qdev_create(NULL, "mpc8544-guts"); > + qdev_init_nofail(dev); > + s =3D sysbus_from_qdev(dev); s =3D SYS_BUS_DEVICE(dev); > + memory_region_add_subregion(ccsr, MPC8544_UTIL_OFFSET, s->mmio[0].= memory); Hmm ... > =20 > /* PCI */ > - dev =3D sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BAS= E, > - mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs= [1]], > - mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs= [3]], > - NULL); > + dev =3D qdev_create(NULL, "e500-pcihost"); > + qdev_init_nofail(dev); > + s =3D sysbus_from_qdev(dev); (dito) > + sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]); > + sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]); > + sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]); > + sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]); > + memory_region_add_subregion(ccsr, MPC8544_PCI_REGS_OFFSET, s->mmio= [0].memory); ... I wonder if fiddling with SysBus MMIO is a good idea. s->mmio[0].addr is not getting assigned this way, which is checked as condition for deleting the subregion. But sysbus_mmio_map() only adds to / deletes from get_system_memory(). The alternative would be using a custom field rather than the SysBus-internal one. Avi/Alex? > + > pci_bus =3D (PCIBus *)qdev_get_child_bus(dev, "pci.0"); > if (!pci_bus) > printf("couldn't create PCI controller!\n"); >=20 Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg