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From: "Andreas Färber" <afaerber@suse.de>
To: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
Cc: linnj@xilinx.com, peter.maydell@linaro.org,
	qemu-devel@nongnu.org, john.williams@petalogix.com,
	edgar.iglesias@gmail.com
Subject: Re: [Qemu-devel] [PATCH v2 4/4] zynq_slcr: Implement CPU reset and halting
Date: Tue, 09 Oct 2012 14:42:02 +0200	[thread overview]
Message-ID: <50741B9A.90803@suse.de> (raw)
In-Reply-To: <ca19ed9b547b5d5d9191e445e524ab44d1c11c7e.1349308835.git.peter.crosthwaite@xilinx.com>

Am 04.10.2012 02:16, schrieb Peter Crosthwaite:
> From: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
> 
> Implement the CPU reset and halt functions of the A9_CPU_RST_CTRL register
> (offset 0x244).
> 
> Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
> ---
> 
>  hw/zynq_slcr.c |   18 ++++++++++++++++++
>  1 files changed, 18 insertions(+), 0 deletions(-)
> 
> diff --git a/hw/zynq_slcr.c b/hw/zynq_slcr.c
> index 6eafad5..c1922fc 100644
> --- a/hw/zynq_slcr.c
> +++ b/hw/zynq_slcr.c
> @@ -116,6 +116,9 @@ typedef enum {
>    RESET_MAX
>  } ResetValues;
>  
> +#define A9_CPU_RST_CTRL_RST_SHIFT 0
> +#define A9_CPU_RST_CTRL_CLKSTOP_SHIFT 4
> +
>  typedef struct {
>      SysBusDevice busdev;
>      MemoryRegion iomem;
> @@ -346,6 +349,7 @@ static void zynq_slcr_write(void *opaque, target_phys_addr_t offset,
>                            uint64_t val, unsigned size)
>  {
>      ZynqSLCRState *s = (ZynqSLCRState *)opaque;
> +    int i;
>  
>      DB_PRINT("offset: %08x data: %08x\n", offset, (unsigned)val);
>  
> @@ -400,6 +404,20 @@ static void zynq_slcr_write(void *opaque, target_phys_addr_t offset,
>                  goto bad_reg;
>              }
>              s->reset[(offset - 0x200) / 4] = val;
> +            if (offset - 0x200 == A9_CPU * 4) { /* CPU Reset */
> +                for (i = 0; i < NUM_CPUS && s->cpus[i]; ++i) {
> +                    bool is_rst = val & (1 << (A9_CPU_RST_CTRL_RST_SHIFT + i));
> +                    bool is_clkstop = val &
> +                                    (1 << (A9_CPU_RST_CTRL_CLKSTOP_SHIFT + i));
> +                    if (is_rst) {
> +                        CPU_GET_CLASS(CPU(s->cpus[i]))->reset(CPU(s->cpus[i]));

Isn't that just cpu_reset(CPU(s->cpus[i]));? Please prefer that over
open-coding.

Thanks,
Andreas

> +                        DB_PRINT("resetting cpu %d\n", i);
> +                    }
> +                    s->cpus[i]->env.halted = is_rst || is_clkstop;
> +                    DB_PRINT("%shalting cpu %d\n", s->cpus[i]->env.halted ?
> +                             "" : "un", i);
> +                }
> +            }
>              break;
>          case 0x300:
>              s->apu_ctrl = val;
> 


-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

  parent reply	other threads:[~2012-10-09 12:42 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-04  0:16 [Qemu-devel] [PATCH v2 0/4] Xilinx-Zynq boot process patches Peter Crosthwaite
2012-10-04  0:16 ` [Qemu-devel] [PATCH v2 1/4] xilinx_zynq: added smp support Peter Crosthwaite
2012-10-09 11:52   ` Peter Maydell
2012-10-09 13:48     ` Peter Crosthwaite
2012-10-04  0:16 ` [Qemu-devel] [PATCH v2 2/4] zynq_slcr: Add links to the CPUs Peter Crosthwaite
2012-10-09 11:45   ` Peter Maydell
2012-10-04  0:16 ` [Qemu-devel] [PATCH v2 3/4] zynq_slcr: Fixed ResetValues enum Peter Crosthwaite
2012-10-09 11:53   ` Peter Maydell
2012-10-09 13:16     ` Peter Crosthwaite
2012-10-04  0:16 ` [Qemu-devel] [PATCH v2 4/4] zynq_slcr: Implement CPU reset and halting Peter Crosthwaite
2012-10-09 11:41   ` Peter Maydell
2012-10-09 13:38     ` Peter Crosthwaite
2012-10-09 13:52       ` Peter Maydell
2012-10-09 14:31         ` Peter Crosthwaite
2012-10-09 12:42   ` Andreas Färber [this message]
2012-10-09  7:43 ` [Qemu-devel] [PATCH v2 0/4] Xilinx-Zynq boot process patches Peter Crosthwaite

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