From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:57781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLeRe-0003KG-6X for qemu-devel@nongnu.org; Tue, 09 Oct 2012 14:22:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLeRY-0008Tq-GM for qemu-devel@nongnu.org; Tue, 09 Oct 2012 14:22:18 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:49766) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLeRY-0008TX-A3 for qemu-devel@nongnu.org; Tue, 09 Oct 2012 14:22:12 -0400 Received: by mail-pa0-f45.google.com with SMTP id fb10so5471649pad.4 for ; Tue, 09 Oct 2012 11:22:11 -0700 (PDT) Sender: Richard Henderson Message-ID: <50746B51.4050105@twiddle.net> Date: Tue, 09 Oct 2012 11:22:09 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1349788610-6380-1-git-send-email-peter.maydell@linaro.org> <50742696.5070306@twiddle.net> <50743BAA.8050306@redhat.com> In-Reply-To: <50743BAA.8050306@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 0/2] make guest-base support mandatory for TCG backends List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: Peter Maydell , patches@linaro.org, Riku Voipio , qemu-devel@nongnu.org, Laurent Desnogues , Aurelien Jarno On 10/09/2012 07:58 AM, Paolo Bonzini wrote: > Perhaps you want to revive this patch: > > http://lists.gnu.org/archive/html/qemu-devel/2010-06/msg00509.html That needs careful benchmarking. For i686 it's a small code size optimization. It's unlikely to pay off for guest_base. A variant of this that sets the bounds of the segment for -R size properly could be interesting for a different reason: ensuring that the guest cannot access host memory. I once had a patch that used %gs for i686 env (aka areg0). With that we get to free up a register for use by TCG, potentially mitigating any slowdown from segmentation. I suspect that the different semantics for 64-bit segments mean that it's more likely to pay off there. And when running on very recent silicon we may not even need to rely on OS support. See the wrfsbase insn that becomes available with Ivy Bridge. r~