From: "Andreas Färber" <afaerber@suse.de>
To: Bharat Bhushan <r65777@freescale.com>
Cc: Bharat Bhushan <Bharat.Bhushan@freescale.com>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org, agraf@suse.de
Subject: Re: [Qemu-devel] [PATCH 1/2 v2] e500: Adding CCSR memory region
Date: Tue, 09 Oct 2012 20:47:50 +0200 [thread overview]
Message-ID: <50747156.2040703@suse.de> (raw)
In-Reply-To: <1349806750-17652-2-git-send-email-Bharat.Bhushan@freescale.com>
Am 09.10.2012 20:19, schrieb Bharat Bhushan:
> All devices are also placed under CCSR memory region.
> The CCSR memory region is exported to pci device. The MSI interrupt
> generation is the main reason to export the CCSR region to PCI device.
> This put the requirement to move mpic under CCSR region, but logically
> all devices should be under CCSR. So this patch places all emulated
> devices under ccsr region.
>
> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Thanks,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
next prev parent reply other threads:[~2012-10-09 18:48 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-09 18:19 [Qemu-devel] [PATCH 0/2 v2] e500: creating CCSR region and registering bar0 Bharat Bhushan
2012-10-09 18:19 ` [Qemu-devel] [PATCH 1/2 v2] e500: Adding CCSR memory region Bharat Bhushan
2012-10-09 18:47 ` Andreas Färber [this message]
2012-10-09 18:19 ` [Qemu-devel] [PATCH 2/2 v2] Adding BAR0 for e500 PCI controller Bharat Bhushan
2012-10-09 18:45 ` Andreas Färber
2012-10-09 22:37 ` Scott Wood
2012-10-10 1:22 ` Bhushan Bharat-R65777
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